drivers/net/au1000_eth.h

   1 /*
   2  * Alchemy Semi Au1000 ethernet driver include file
   3  *
   4  * Author: Pete Popov <ppopov@mvista.com>
   5  *
   6  * Copyright 2001 MontaVista Software Inc.
   7  *
   8  *  This program is free software; you can distribute it and/or modify it
   9  *  under the terms of the GNU General Public License (Version 2) as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, write to the Free Software Foundation, Inc.,
  19  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  20  */
  21 #include <linux/config.h>
  22
  23
  24 #define NUM_INTERFACES 2
  25 #define MAC_IOSIZE 0x10000
  26 #define NUM_RX_DMA 4       /* Au1000 has 4 rx hardware descriptors */
  27 #define NUM_TX_DMA 4       /* Au1000 has 4 tx hardware descriptors */
  28
  29 #define NUM_RX_BUFFS 4
  30 #define NUM_TX_BUFFS 4
  31 #define MAX_BUF_SIZE 2048
  32
  33 #define ETH_TX_TIMEOUT HZ/4
  34 #define MAC_MIN_PKT_SIZE 64
  35
  36 #if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1100)
  37 #define PHY_ADDRESS              0
  38 #define PHY_CONTROL_DEFAULT 0x3000
  39 #define PHY_CONTROL_REG_ADDR     0
  40 #endif
  41
  42 #define MULTICAST_FILTER_LIMIT 64
  43
  44 /* FIXME
  45  * The PHY defines should be in a separate file.
  46  */
  47
  48 /* MII register offsets */
  49 #define MII_CONTROL 0x0000
  50 #define MII_STATUS  0x0001
  51 #define MII_PHY_ID0 0x0002
  52 #define MII_PHY_ID1 0x0003
  53 #define MII_ANADV   0x0004
  54 #define MII_ANLPAR  0x0005
  55 #define MII_AEXP    0x0006
  56 #define MII_ANEXT   0x0007
  57 #define MII_LSI_CONFIG 0x0011
  58 #define MII_LSI_STAT   0x0012
  59 #define MII_AUX_CNTRL  0x0018
  60 #define MII_INT        0x001A
  61
  62 /* mii registers specific to AMD 79C901 */
  63 #define MII_STATUS_SUMMARY = 0x0018
  64
  65 /* MII Control register bit definitions. */
  66 #define MII_CNTL_FDX      0x0100
  67 #define MII_CNTL_RST_AUTO 0x0200
  68 #define MII_CNTL_ISOLATE  0x0400
  69 #define MII_CNTL_PWRDWN   0x0800
  70 #define MII_CNTL_AUTO     0x1000
  71 #define MII_CNTL_F100     0x2000
  72 #define MII_CNTL_LPBK     0x4000
  73 #define MII_CNTL_RESET    0x8000
  74
  75 /* MII Status register bit  */
  76 #define MII_STAT_EXT        0x0001
  77 #define MII_STAT_JAB        0x0002
  78 #define MII_STAT_LINK       0x0004
  79 #define MII_STAT_CAN_AUTO   0x0008
  80 #define MII_STAT_FAULT      0x0010
  81 #define MII_STAT_AUTO_DONE  0x0020
  82 #define MII_STAT_CAN_T      0x0800
  83 #define MII_STAT_CAN_T_FDX  0x1000
  84 #define MII_STAT_CAN_TX     0x2000
  85 #define MII_STAT_CAN_TX_FDX 0x4000
  86 #define MII_STAT_CAN_T4     0x8000
  87
  88
  89 #define         MII_ID1_OUI_LO          0xFC00  /* low bits of OUI mask */
  90 #define         MII_ID1_MODEL           0x03F0  /* model number */
  91 #define         MII_ID1_REV             0x000F  /* model number */
  92
  93 /* MII NWAY Register Bits ...
  94    valid for the ANAR (Auto-Negotiation Advertisement) and
  95    ANLPAR (Auto-Negotiation Link Partner) registers */
  96 #define MII_NWAY_NODE_SEL 0x001f
  97 #define MII_NWAY_CSMA_CD  0x0001
  98 #define MII_NWAY_T        0x0020
  99 #define MII_NWAY_T_FDX    0x0040
 100 #define MII_NWAY_TX       0x0080
 101 #define MII_NWAY_TX_FDX   0x0100
 102 #define MII_NWAY_T4       0x0200
 103 #define MII_NWAY_PAUSE    0x0400
 104 #define MII_NWAY_RF       0x2000 /* Remote Fault */
 105 #define MII_NWAY_ACK      0x4000 /* Remote Acknowledge */
 106 #define MII_NWAY_NP       0x8000 /* Next Page (Enable) */
 107
 108 /* mii stsout register bits */
 109 #define MII_STSOUT_LINK_FAIL 0x4000
 110 #define MII_STSOUT_SPD       0x0080
 111 #define MII_STSOUT_DPLX      0x0040
 112
 113 /* mii stsics register bits */
 114 #define MII_STSICS_SPD       0x8000
 115 #define MII_STSICS_DPLX      0x4000
 116 #define MII_STSICS_LINKSTS   0x0001
 117
 118 /* mii stssum register bits */
 119 #define MII_STSSUM_LINK  0x0008
 120 #define MII_STSSUM_DPLX  0x0004
 121 #define MII_STSSUM_AUTO  0x0002
 122 #define MII_STSSUM_SPD   0x0001
 123
 124 /* lsi status register */
 125
 126 #define MII_LSI_STAT_FDX        0x0040
 127 #define MII_LSI_STAT_SPD        0x0080
 128
 129 /* Auxilliary Control/Status Register */
 130 #define MII_AUX_FDX      0x0001
 131 #define MII_AUX_100      0x0002
 132 #define MII_AUX_F100     0x0004
 133 #define MII_AUX_ANEG     0x0008
 134 #define MII_FDX_LED      0x8000
 135
 136 typedef struct mii_phy {
 137         struct mii_phy * next;
 138         struct mii_chip_info * chip_info;
 139         int phy_addr;
 140         u16 status;
 141 } mii_phy_t;
 142
 143 struct phy_ops {
 144         int (*phy_init) (struct net_device *, int);
 145         int (*phy_reset) (struct net_device *, int);
 146         int (*phy_status) (struct net_device *, int, u16 *, u16 *);
 147 };
 148
 149 /*
 150  * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
 151  * boundary for both, receive and transmit.
 152  */
 153 typedef struct db_dest {
 154         struct db_dest *pnext;
 155         volatile u32 *vaddr;
 156         dma_addr_t dma_addr;
 157 } db_dest_t;
 158
 159 /*
 160  * The transmit and receive descriptors are memory
 161  * mapped registers.
 162  */
 163 typedef struct tx_dma {
 164         u32 status;
 165         u32 buff_stat;
 166         u32 len;
 167         u32 pad;
 168 } tx_dma_t;
 169
 170 typedef struct rx_dma {
 171         u32 status;
 172         u32 buff_stat;
 173         u32 pad[2];
 174 } rx_dma_t;
 175
 176
 177 /*
 178  * MAC control registers, memory mapped.
 179  */
 180 typedef struct mac_reg {
 181         u32 control;
 182         u32 mac_addr_high;
 183         u32 mac_addr_low;
 184         u32 multi_hash_high;
 185         u32 multi_hash_low;
 186         u32 mii_control;
 187         u32 mii_data;
 188         u32 flow_control;
 189         u32 vlan1_tag;
 190         u32 vlan2_tag;
 191 } mac_reg_t;
 192
 193
 194 struct au1000_private {
 195
 196         db_dest_t *pDBfree;
 197         db_dest_t db[NUM_RX_BUFFS+NUM_TX_BUFFS];
 198         volatile rx_dma_t *rx_dma_ring[NUM_RX_DMA];
 199         volatile tx_dma_t *tx_dma_ring[NUM_TX_DMA];
 200         int tx_len[NUM_TX_DMA];
 201         db_dest_t *rx_db_inuse[NUM_RX_DMA];
 202         db_dest_t *tx_db_inuse[NUM_TX_DMA];
 203         u32 rx_head;
 204         u32 tx_head;
 205         u32 tx_tail;
 206         u32 tx_full;
 207
 208         mii_phy_t *mii;
 209         struct phy_ops *phy_ops;
 210
 211         /* These variables are just for quick access to certain regs addresses. */
 212         volatile mac_reg_t *mac;  /* mac registers                      */
 213         volatile u32 *enable;     /* address of MAC Enable Register     */
 214
 215         u32 vaddr;                /* virtual address of rx/tx buffers   */
 216         dma_addr_t dma_addr;      /* dma address of rx/tx buffers       */
 217
 218         u8 *hash_table;
 219         u32 hash_mode;
 220         u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */
 221         u32 phy_addr;          /* PHY address */
 222         u32 options;           /* User-settable misc. driver options. */
 223         u32 drv_flags;
 224         struct net_device_stats stats;
 225         struct timer_list timer;
 226         spinlock_t lock;       /* Serialise access to device */
 227 };