include/asm-arm/cacheflush.h

   1 /*
   2  *  linux/include/asm-arm/cacheflush.h
   3  *
   4  *  Copyright (C) 1999-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASMARM_CACHEFLUSH_H
  11 #define _ASMARM_CACHEFLUSH_H
  12
  13 #include <linux/sched.h>
  14 #include <linux/mm.h>
  15
  16 #include <asm/glue.h>
  17 #include <asm/shmparam.h>
  18
  19 #define CACHE_COLOUR(vaddr)     ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
  20
  21 /*
  22  *      Cache Model
  23  *      ===========
  24  */
  25 #undef _CACHE
  26 #undef MULTI_CACHE
  27
  28 #if defined(CONFIG_CPU_CACHE_V3)
  29 # ifdef _CACHE
  30 #  define MULTI_CACHE 1
  31 # else
  32 #  define _CACHE v3
  33 # endif
  34 #endif
  35
  36 #if defined(CONFIG_CPU_CACHE_V4)
  37 # ifdef _CACHE
  38 #  define MULTI_CACHE 1
  39 # else
  40 #  define _CACHE v4
  41 # endif
  42 #endif
  43
  44 #if defined(CONFIG_CPU_ARM7TDMI) || defined(CONFIG_CPU_ARM9TDMI)
  45 # ifdef _CACHE
  46 #  define MULTI_CACHE 1
  47 # else
  48 #  define _CACHE v4
  49 # endif
  50 #endif
  51
  52 #if defined(CONFIG_CPU_S3C4510B)
  53 # ifdef _CACHE
  54 #  define MULTI_CACHE 1
  55 # else
  56 #  define _CACHE s3c4510b
  57 # endif
  58 #endif
  59
  60 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
  61     defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
  62 # define MULTI_CACHE 1
  63 #endif
  64
  65 #if defined(CONFIG_CPU_ARM926T)
  66 # ifdef _CACHE
  67 #  define MULTI_CACHE 1
  68 # else
  69 #  define _CACHE arm926
  70 # endif
  71 #endif
  72
  73 #if defined(CONFIG_CPU_ARM940T)
  74 # ifdef _CACHE
  75 #  define MULTI_CACHE 1
  76 # else
  77 #  define _CACHE arm940
  78 # endif
  79 #endif
  80
  81 #if defined(CONFIG_CPU_ARM946E)
  82 # ifdef _CACHE
  83 #  define MULTI_CACHE 1
  84 # else
  85 #  define _CACHE arm946
  86 # endif
  87 #endif
  88
  89 #if defined(CONFIG_CPU_CACHE_V4WB)
  90 # ifdef _CACHE
  91 #  define MULTI_CACHE 1
  92 # else
  93 #  define _CACHE v4wb
  94 # endif
  95 #endif
  96
  97 #if defined(CONFIG_CPU_XSCALE)
  98 # ifdef _CACHE
  99 #  define MULTI_CACHE 1
 100 # else
 101 #  define _CACHE xscale
 102 # endif
 103 #endif
 104
 105 #if defined(CONFIG_CPU_XSC3)
 106 # ifdef _CACHE
 107 #  define MULTI_CACHE 1
 108 # else
 109 #  define _CACHE xsc3
 110 # endif
 111 #endif
 112
 113 #if defined(CONFIG_CPU_V6)
 114 //# ifdef _CACHE
 115 #  define MULTI_CACHE 1
 116 //# else
 117 //#  define _CACHE v6
 118 //# endif
 119 #endif
 120
 121 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 122 #error Unknown cache maintainence model
 123 #endif
 124
 125 /*
 126  * This flag is used to indicate that the page pointed to by a pte
 127  * is dirty and requires cleaning before returning it to the user.
 128  */
 129 #define PG_dcache_dirty PG_arch_1
 130
 131 /*
 132  *      MM Cache Management
 133  *      ===================
 134  *
 135  *      The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
 136  *      implement these methods.
 137  *
 138  *      Start addresses are inclusive and end addresses are exclusive;
 139  *      start addresses should be rounded down, end addresses up.
 140  *
 141  *      See Documentation/cachetlb.txt for more information.
 142  *      Please note that the implementation of these, and the required
 143  *      effects are cache-type (VIVT/VIPT/PIPT) specific.
 144  *
 145  *      flush_cache_kern_all()
 146  *
 147  *              Unconditionally clean and invalidate the entire cache.
 148  *
 149  *      flush_cache_user_mm(mm)
 150  *
 151  *              Clean and invalidate all user space cache entries
 152  *              before a change of page tables.
 153  *
 154  *      flush_cache_user_range(start, end, flags)
 155  *
 156  *              Clean and invalidate a range of cache entries in the
 157  *              specified address space before a change of page tables.
 158  *              - start - user start address (inclusive, page aligned)
 159  *              - end   - user end address   (exclusive, page aligned)
 160  *              - flags - vma->vm_flags field
 161  *
 162  *      coherent_kern_range(start, end)
 163  *
 164  *              Ensure coherency between the Icache and the Dcache in the
 165  *              region described by start, end.  If you have non-snooping
 166  *              Harvard caches, you need to implement this function.
 167  *              - start  - virtual start address
 168  *              - end    - virtual end address
 169  *
 170  *      DMA Cache Coherency
 171  *      ===================
 172  *
 173  *      dma_inv_range(start, end)
 174  *
 175  *              Invalidate (discard) the specified virtual address range.
 176  *              May not write back any entries.  If 'start' or 'end'
 177  *              are not cache line aligned, those lines must be written
 178  *              back.
 179  *              - start  - virtual start address
 180  *              - end    - virtual end address
 181  *
 182  *      dma_clean_range(start, end)
 183  *
 184  *              Clean (write back) the specified virtual address range.
 185  *              - start  - virtual start address
 186  *              - end    - virtual end address
 187  *
 188  *      dma_flush_range(start, end)
 189  *
 190  *              Clean and invalidate the specified virtual address range.
 191  *              - start  - virtual start address
 192  *              - end    - virtual end address
 193  */
 194
 195 struct cpu_cache_fns {
 196         void (*flush_kern_all)(void);
 197         void (*flush_user_all)(void);
 198         void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
 199
 200         void (*coherent_kern_range)(unsigned long, unsigned long);
 201         void (*coherent_user_range)(unsigned long, unsigned long);
 202         void (*flush_kern_dcache_page)(void *);
 203
 204         void (*dma_inv_range)(unsigned long, unsigned long);
 205         void (*dma_clean_range)(unsigned long, unsigned long);
 206         void (*dma_flush_range)(unsigned long, unsigned long);
 207 };
 208
 209 /*
 210  * Select the calling method
 211  */
 212 #ifdef MULTI_CACHE
 213
 214 extern struct cpu_cache_fns cpu_cache;
 215
 216 #define __cpuc_flush_kern_all           cpu_cache.flush_kern_all
 217 #define __cpuc_flush_user_all           cpu_cache.flush_user_all
 218 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
 219 #define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
 220 #define __cpuc_coherent_user_range      cpu_cache.coherent_user_range
 221 #define __cpuc_flush_dcache_page        cpu_cache.flush_kern_dcache_page
 222
 223 /*
 224  * These are private to the dma-mapping API.  Do not use directly.
 225  * Their sole purpose is to ensure that data held in the cache
 226  * is visible to DMA, or data written by DMA to system memory is
 227  * visible to the CPU.
 228  */
 229 #define dmac_inv_range                  cpu_cache.dma_inv_range
 230 #define dmac_clean_range                cpu_cache.dma_clean_range
 231 #define dmac_flush_range                cpu_cache.dma_flush_range
 232
 233 #else
 234
 235 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
 236 #define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
 237 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
 238 #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
 239 #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
 240 #define __cpuc_flush_dcache_page        __glue(_CACHE,_flush_kern_dcache_page)
 241
 242 extern void __cpuc_flush_kern_all(void);
 243 extern void __cpuc_flush_user_all(void);
 244 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 245 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
 246 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
 247 extern void __cpuc_flush_dcache_page(void *);
 248
 249 /*
 250  * These are private to the dma-mapping API.  Do not use directly.
 251  * Their sole purpose is to ensure that data held in the cache
 252  * is visible to DMA, or data written by DMA to system memory is
 253  * visible to the CPU.
 254  */
 255 #define dmac_inv_range                  __glue(_CACHE,_dma_inv_range)
 256 #define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
 257 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 258
 259 extern void dmac_inv_range(unsigned long, unsigned long);
 260 extern void dmac_clean_range(unsigned long, unsigned long);
 261 extern void dmac_flush_range(unsigned long, unsigned long);
 262
 263 #endif
 264
 265 /*
 266  * flush_cache_vmap() is used when creating mappings (eg, via vmap,
 267  * vmalloc, ioremap etc) in kernel space for pages.  Since the
 268  * direct-mappings of these pages may contain cached data, we need
 269  * to do a full cache flush to ensure that writebacks don't corrupt
 270  * data placed into these pages via the new mappings.
 271  */
 272 #define flush_cache_vmap(start, end)            flush_cache_all()
 273 #define flush_cache_vunmap(start, end)          flush_cache_all()
 274
 275 /*
 276  * Copy user data from/to a page which is mapped into a different
 277  * processes address space.  Really, we want to allow our "user
 278  * space" model to handle this.
 279  */
 280 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
 281         do {                                                    \
 282                 memcpy(dst, src, len);                          \
 283                 flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
 284         } while (0)
 285
 286 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 287         do {                                                    \
 288                 memcpy(dst, src, len);                          \
 289         } while (0)
 290
 291 /*
 292  * Convert calls to our calling convention.
 293  */
 294 #define flush_cache_all()               __cpuc_flush_kern_all()
 295 #ifndef CONFIG_CPU_CACHE_VIPT
 296 static inline void flush_cache_mm(struct mm_struct *mm)
 297 {
 298         if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
 299                 __cpuc_flush_user_all();
 300 }
 301
 302 static inline void
 303 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 304 {
 305         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
 306                 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
 307                                         vma->vm_flags);
 308 }
 309
 310 static inline void
 311 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
 312 {
 313         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
 314                 unsigned long addr = user_addr & PAGE_MASK;
 315                 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
 316         }
 317 }
 318
 319 static inline void
 320 flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 321                          unsigned long uaddr, void *kaddr,
 322                          unsigned long len, int write)
 323 {
 324         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
 325                 unsigned long addr = (unsigned long)kaddr;
 326                 __cpuc_coherent_kern_range(addr, addr + len);
 327         }
 328 }
 329 #else
 330 extern void flush_cache_mm(struct mm_struct *mm);
 331 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 332 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
 333 extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 334                                 unsigned long uaddr, void *kaddr,
 335                                 unsigned long len, int write);
 336 #endif
 337
 338 /*
 339  * flush_cache_user_range is used when we want to ensure that the
 340  * Harvard caches are synchronised for the user space address range.
 341  * This is used for the ARM private sys_cacheflush system call.
 342  */
 343 #define flush_cache_user_range(vma,start,end) \
 344         __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
 345
 346 /*
 347  * Perform necessary cache operations to ensure that data previously
 348  * stored within this range of addresses can be executed by the CPU.
 349  */
 350 #define flush_icache_range(s,e)         __cpuc_coherent_kern_range(s,e)
 351
 352 /*
 353  * Perform necessary cache operations to ensure that the TLB will
 354  * see data written in the specified area.
 355  */
 356 #define clean_dcache_area(start,size)   cpu_dcache_clean_area(start, size)
 357
 358 /*
 359  * flush_dcache_page is used when the kernel has written to the page
 360  * cache page at virtual address page->virtual.
 361  *
 362  * If this page isn't mapped (ie, page_mapping == NULL), or it might
 363  * have userspace mappings, then we _must_ always clean + invalidate
 364  * the dcache entries associated with the kernel mapping.
 365  *
 366  * Otherwise we can defer the operation, and clean the cache when we are
 367  * about to change to user space.  This is the same method as used on SPARC64.
 368  * See update_mmu_cache for the user space part.
 369  */
 370 extern void flush_dcache_page(struct page *);
 371
 372 #define flush_dcache_mmap_lock(mapping) \
 373         write_lock_irq(&(mapping)->tree_lock)
 374 #define flush_dcache_mmap_unlock(mapping) \
 375         write_unlock_irq(&(mapping)->tree_lock)
 376
 377 #define flush_icache_user_range(vma,page,addr,len) \
 378         flush_dcache_page(page)
 379
 380 /*
 381  * We don't appear to need to do anything here.  In fact, if we did, we'd
 382  * duplicate cache flushing elsewhere performed by flush_dcache_page().
 383  */
 384 #define flush_icache_page(vma,page)     do { } while (0)
 385
 386 #define __cacheid_present(val)          (val != read_cpuid(CPUID_ID))
 387 #define __cacheid_vivt(val)             ((val & (15 << 25)) != (14 << 25))
 388 #define __cacheid_vipt(val)             ((val & (15 << 25)) == (14 << 25))
 389 #define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
 390 #define __cacheid_vipt_aliasing(val)    ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
 391
 392 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
 393
 394 #define cache_is_vivt()                 1
 395 #define cache_is_vipt()                 0
 396 #define cache_is_vipt_nonaliasing()     0
 397 #define cache_is_vipt_aliasing()        0
 398
 399 #elif defined(CONFIG_CPU_CACHE_VIPT)
 400
 401 #define cache_is_vivt()                 0
 402 #define cache_is_vipt()                 1
 403 #define cache_is_vipt_nonaliasing()                                     \
 404         ({                                                              \
 405                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 406                 __cacheid_vipt_nonaliasing(__val);                      \
 407         })
 408
 409 #define cache_is_vipt_aliasing()                                        \
 410         ({                                                              \
 411                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 412                 __cacheid_vipt_aliasing(__val);                         \
 413         })
 414
 415 #else
 416
 417 #define cache_is_vivt()                                                 \
 418         ({                                                              \
 419                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 420                 (!__cacheid_present(__val)) || __cacheid_vivt(__val);   \
 421         })
 422
 423 #define cache_is_vipt()                                                 \
 424         ({                                                              \
 425                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 426                 __cacheid_present(__val) && __cacheid_vipt(__val);      \
 427         })
 428
 429 #define cache_is_vipt_nonaliasing()                                     \
 430         ({                                                              \
 431                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 432                 __cacheid_present(__val) &&                             \
 433                  __cacheid_vipt_nonaliasing(__val);                     \
 434         })
 435
 436 #define cache_is_vipt_aliasing()                                        \
 437         ({                                                              \
 438                 unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
 439                 __cacheid_present(__val) &&                             \
 440                  __cacheid_vipt_aliasing(__val);                        \
 441         })
 442
 443 #endif
 444
 445 #endif