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MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / drivers / net / r8169.c
blob8676fc875a4f76edd7a8c8ef00155be0ba74e19a
1 /*
2 =========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10 =========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23 =========================================================================
24 VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30 VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37 VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45 VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/pci.h>
56 #include <linux/netdevice.h>
57 #include <linux/etherdevice.h>
58 #include <linux/delay.h>
59 #include <linux/ethtool.h>
60 #include <linux/mii.h>
61 #include <linux/if_vlan.h>
62 #include <linux/crc32.h>
63 #include <linux/in.h>
64 #include <linux/ip.h>
65 #include <linux/tcp.h>
66 #include <linux/init.h>
67 #include <linux/dma-mapping.h>
68 #ifdef CONFIG_LEDMAN
69 #include <linux/ledman.h>
70 #endif
71
72 #include <asm/io.h>
73 #include <asm/irq.h>
74
75 #ifdef CONFIG_R8169_NAPI
76 #define NAPI_SUFFIX "-NAPI"
77 #else
78 #define NAPI_SUFFIX ""
79 #endif
80
81 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
82 #define MODULENAME "r8169"
83 #define PFX MODULENAME ": "
84
85 #ifdef RTL8169_DEBUG
86 #define assert(expr) \
87 if (!(expr)) { \
88 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
89 #expr,__FILE__,__FUNCTION__,__LINE__); \
90 }
91 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
92 #else
93 #define assert(expr) do {} while (0)
94 #define dprintk(fmt, args...) do {} while (0)
95 #endif /* RTL8169_DEBUG */
96
97 #define R8169_MSG_DEFAULT \
98 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
99
100 #define TX_BUFFS_AVAIL(tp) \
101 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
102
103 #ifdef CONFIG_R8169_NAPI
104 #define rtl8169_rx_skb netif_receive_skb
105 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
106 #define rtl8169_rx_quota(count, quota) min(count, quota)
107 #else
108 #define rtl8169_rx_skb netif_rx
109 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
110 #define rtl8169_rx_quota(count, quota) count
111 #endif
112
113 /* media options */
114 #define MAX_UNITS 8
115 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
116 static int num_media = 0;
117
118 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
119 static const int max_interrupt_work = 20;
120
121 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
122 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
123 static const int multicast_filter_limit = 32;
124
125 /* MAC address length */
126 #define MAC_ADDR_LEN 6
127
128 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
129 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
130 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
131 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
132 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
133 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
134 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
135
136 #define R8169_REGS_SIZE 256
137 #define R8169_NAPI_WEIGHT 64
138 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
139 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
140 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
141 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
142 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
143
144 #define RTL8169_TX_TIMEOUT (6*HZ)
145 #define RTL8169_PHY_TIMEOUT (10*HZ)
146
147 /* write/read MMIO register */
148 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
149 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
150 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
151 #define RTL_R8(reg) readb (ioaddr + (reg))
152 #define RTL_R16(reg) readw (ioaddr + (reg))
153 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
154
155 enum mac_version {
156 RTL_GIGA_MAC_VER_01 = 0x00,
157 RTL_GIGA_MAC_VER_02 = 0x01,
158 RTL_GIGA_MAC_VER_03 = 0x02,
159 RTL_GIGA_MAC_VER_04 = 0x03,
160 RTL_GIGA_MAC_VER_05 = 0x04,
161 RTL_GIGA_MAC_VER_11 = 0x0b,
162 RTL_GIGA_MAC_VER_12 = 0x0c,
163 RTL_GIGA_MAC_VER_13 = 0x0d,
164 RTL_GIGA_MAC_VER_14 = 0x0e,
165 RTL_GIGA_MAC_VER_15 = 0x0f
166 };
167
168 enum phy_version {
169 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
170 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
171 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
172 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
173 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
174 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
175 };
176
177 #define _R(NAME,MAC,MASK) \
178 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
179
180 static const struct {
181 const char *name;
182 u8 mac_version;
183 u32 RxConfigMask; /* Clears the bits supported by this chip */
184 } rtl_chip_info[] = {
185 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
186 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
187 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
188 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
189 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
190 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
191 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
192 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
193 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
194 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
195 };
196 #undef _R
197
198 enum cfg_version {
199 RTL_CFG_0 = 0x00,
200 RTL_CFG_1,
201 RTL_CFG_2
202 };
203
204 static const struct {
205 unsigned int region;
206 unsigned int align;
207 } rtl_cfg_info[] = {
208 [RTL_CFG_0] = { 1, NET_IP_ALIGN },
209 [RTL_CFG_1] = { 2, NET_IP_ALIGN },
210 [RTL_CFG_2] = { 2, 8 }
211 };
212
213 static struct pci_device_id rtl8169_pci_tbl[] = {
214 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
215 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
216 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
217 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
218 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
219 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
220 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
221 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
222 { PCI_VENDOR_ID_LINKSYS, 0x1032,
223 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
224 {0,},
225 };
226
227 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
228
229 static int rx_copybreak = 200;
230 static int use_dac;
231 static struct {
232 u32 msg_enable;
233 } debug = { -1 };
234
235 enum RTL8169_registers {
236 MAC0 = 0, /* Ethernet hardware address. */
237 MAR0 = 8, /* Multicast filter. */
238 CounterAddrLow = 0x10,
239 CounterAddrHigh = 0x14,
240 TxDescStartAddrLow = 0x20,
241 TxDescStartAddrHigh = 0x24,
242 TxHDescStartAddrLow = 0x28,
243 TxHDescStartAddrHigh = 0x2c,
244 FLASH = 0x30,
245 ERSR = 0x36,
246 ChipCmd = 0x37,
247 TxPoll = 0x38,
248 IntrMask = 0x3C,
249 IntrStatus = 0x3E,
250 TxConfig = 0x40,
251 RxConfig = 0x44,
252 RxMissed = 0x4C,
253 Cfg9346 = 0x50,
254 Config0 = 0x51,
255 Config1 = 0x52,
256 Config2 = 0x53,
257 Config3 = 0x54,
258 Config4 = 0x55,
259 Config5 = 0x56,
260 MultiIntr = 0x5C,
261 PHYAR = 0x60,
262 TBICSR = 0x64,
263 TBI_ANAR = 0x68,
264 TBI_LPAR = 0x6A,
265 PHYstatus = 0x6C,
266 RxMaxSize = 0xDA,
267 CPlusCmd = 0xE0,
268 IntrMitigate = 0xE2,
269 RxDescAddrLow = 0xE4,
270 RxDescAddrHigh = 0xE8,
271 EarlyTxThres = 0xEC,
272 FuncEvent = 0xF0,
273 FuncEventMask = 0xF4,
274 FuncPresetState = 0xF8,
275 FuncForceEvent = 0xFC,
276 };
277
278 enum RTL8169_register_content {
279 /* InterruptStatusBits */
280 SYSErr = 0x8000,
281 PCSTimeout = 0x4000,
282 SWInt = 0x0100,
283 TxDescUnavail = 0x80,
284 RxFIFOOver = 0x40,
285 LinkChg = 0x20,
286 RxOverflow = 0x10,
287 TxErr = 0x08,
288 TxOK = 0x04,
289 RxErr = 0x02,
290 RxOK = 0x01,
291
292 /* RxStatusDesc */
293 RxFOVF = (1 << 23),
294 RxRWT = (1 << 22),
295 RxRES = (1 << 21),
296 RxRUNT = (1 << 20),
297 RxCRC = (1 << 19),
298
299 /* ChipCmdBits */
300 CmdReset = 0x10,
301 CmdRxEnb = 0x08,
302 CmdTxEnb = 0x04,
303 RxBufEmpty = 0x01,
304
305 /* Cfg9346Bits */
306 Cfg9346_Lock = 0x00,
307 Cfg9346_Unlock = 0xC0,
308
309 /* rx_mode_bits */
310 AcceptErr = 0x20,
311 AcceptRunt = 0x10,
312 AcceptBroadcast = 0x08,
313 AcceptMulticast = 0x04,
314 AcceptMyPhys = 0x02,
315 AcceptAllPhys = 0x01,
316
317 /* RxConfigBits */
318 RxCfgFIFOShift = 13,
319 RxCfgDMAShift = 8,
320
321 /* TxConfigBits */
322 TxInterFrameGapShift = 24,
323 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
324
325 /* Config1 register p.24 */
326 PMEnable = (1 << 0), /* Power Management Enable */
327
328 /* Config3 register p.25 */
329 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
330 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
331
332 /* Config5 register p.27 */
333 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
334 MWF = (1 << 5), /* Accept Multicast wakeup frame */
335 UWF = (1 << 4), /* Accept Unicast wakeup frame */
336 LanWake = (1 << 1), /* LanWake enable/disable */
337 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
338
339 /* TBICSR p.28 */
340 TBIReset = 0x80000000,
341 TBILoopback = 0x40000000,
342 TBINwEnable = 0x20000000,
343 TBINwRestart = 0x10000000,
344 TBILinkOk = 0x02000000,
345 TBINwComplete = 0x01000000,
346
347 /* CPlusCmd p.31 */
348 RxVlan = (1 << 6),
349 RxChkSum = (1 << 5),
350 PCIDAC = (1 << 4),
351 PCIMulRW = (1 << 3),
352
353 /* rtl8169_PHYstatus */
354 TBI_Enable = 0x80,
355 TxFlowCtrl = 0x40,
356 RxFlowCtrl = 0x20,
357 _1000bpsF = 0x10,
358 _100bps = 0x08,
359 _10bps = 0x04,
360 LinkStatus = 0x02,
361 FullDup = 0x01,
362
363 /* _MediaType */
364 _10_Half = 0x01,
365 _10_Full = 0x02,
366 _100_Half = 0x04,
367 _100_Full = 0x08,
368 _1000_Full = 0x10,
369
370 /* _TBICSRBit */
371 TBILinkOK = 0x02000000,
372
373 /* DumpCounterCommand */
374 CounterDump = 0x8,
375 };
376
377 enum _DescStatusBit {
378 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
379 RingEnd = (1 << 30), /* End of descriptor ring */
380 FirstFrag = (1 << 29), /* First segment of a packet */
381 LastFrag = (1 << 28), /* Final segment of a packet */
382
383 /* Tx private */
384 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
385 MSSShift = 16, /* MSS value position */
386 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
387 IPCS = (1 << 18), /* Calculate IP checksum */
388 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
389 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
390 TxVlanTag = (1 << 17), /* Add VLAN tag */
391
392 /* Rx private */
393 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
394 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
395
396 #define RxProtoUDP (PID1)
397 #define RxProtoTCP (PID0)
398 #define RxProtoIP (PID1 | PID0)
399 #define RxProtoMask RxProtoIP
400
401 IPFail = (1 << 16), /* IP checksum failed */
402 UDPFail = (1 << 15), /* UDP/IP checksum failed */
403 TCPFail = (1 << 14), /* TCP/IP checksum failed */
404 RxVlanTag = (1 << 16), /* VLAN tag available */
405 };
406
407 #define RsvdMask 0x3fffc000
408
409 struct TxDesc {
410 u32 opts1;
411 u32 opts2;
412 u64 addr;
413 };
414
415 struct RxDesc {
416 u32 opts1;
417 u32 opts2;
418 u64 addr;
419 };
420
421 struct ring_info {
422 struct sk_buff *skb;
423 u32 len;
424 u8 __pad[sizeof(void *) - sizeof(u32)];
425 };
426
427 struct rtl8169_private {
428 void __iomem *mmio_addr; /* memory map physical address */
429 struct pci_dev *pci_dev; /* Index of PCI device */
430 struct net_device_stats stats; /* statistics of net device */
431 spinlock_t lock; /* spin lock flag */
432 u32 msg_enable;
433 int chipset;
434 int mac_version;
435 int phy_version;
436 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
437 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
438 u32 dirty_rx;
439 u32 dirty_tx;
440 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
441 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
442 dma_addr_t TxPhyAddr;
443 dma_addr_t RxPhyAddr;
444 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
445 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
446 unsigned align;
447 unsigned rx_buf_sz;
448 struct timer_list timer;
449 u16 cp_cmd;
450 u16 intr_mask;
451 int phy_auto_nego_reg;
452 int phy_1000_ctrl_reg;
453 #ifdef CONFIG_R8169_VLAN
454 struct vlan_group *vlgrp;
455 #endif
456 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
457 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
458 void (*phy_reset_enable)(void __iomem *);
459 unsigned int (*phy_reset_pending)(void __iomem *);
460 unsigned int (*link_ok)(void __iomem *);
461 struct work_struct task;
462 unsigned wol_enabled : 1;
463 };
464
465 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
466 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
467 module_param_array(media, int, &num_media, 0);
468 MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
469 module_param(rx_copybreak, int, 0);
470 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
471 module_param(use_dac, int, 0);
472 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
473 module_param_named(debug, debug.msg_enable, int, 0);
474 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
475 MODULE_LICENSE("GPL");
476 MODULE_VERSION(RTL8169_VERSION);
477
478 static int rtl8169_open(struct net_device *dev);
479 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
480 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
481 static int rtl8169_init_ring(struct net_device *dev);
482 static void rtl8169_hw_start(struct net_device *dev);
483 static int rtl8169_close(struct net_device *dev);
484 static void rtl8169_set_rx_mode(struct net_device *dev);
485 static void rtl8169_tx_timeout(struct net_device *dev);
486 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
487 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
488 void __iomem *);
489 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
490 static void rtl8169_down(struct net_device *dev);
491
492 #ifdef CONFIG_R8169_NAPI
493 static int rtl8169_poll(struct net_device *dev, int *budget);
494 #endif
495
496 static const u16 rtl8169_intr_mask =
497 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
498 static const u16 rtl8169_napi_event =
499 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
500 static const unsigned int rtl8169_rx_config =
501 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
502
503 static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
504 {
505 int i;
506
507 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
508
509 for (i = 20; i > 0; i--) {
510 /* Check if the RTL8169 has completed writing to the specified MII register */
511 if (!(RTL_R32(PHYAR) & 0x80000000))
512 break;
513 udelay(25);
514 }
515 }
516
517 static int mdio_read(void __iomem *ioaddr, int RegAddr)
518 {
519 int i, value = -1;
520
521 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
522
523 for (i = 20; i > 0; i--) {
524 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
525 if (RTL_R32(PHYAR) & 0x80000000) {
526 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
527 break;
528 }
529 udelay(25);
530 }
531 return value;
532 }
533
534 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
535 {
536 RTL_W16(IntrMask, 0x0000);
537 #if 0
538 RTL_W16(IntrStatus, 0xffff);
539 #endif
540 }
541
542 static void rtl8169_asic_down(void __iomem *ioaddr)
543 {
544 RTL_W8(ChipCmd, 0x00);
545 rtl8169_irq_mask_and_ack(ioaddr);
546 RTL_R16(CPlusCmd);
547 }
548
549 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
550 {
551 return RTL_R32(TBICSR) & TBIReset;
552 }
553
554 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
555 {
556 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
557 }
558
559 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
560 {
561 return RTL_R32(TBICSR) & TBILinkOk;
562 }
563
564 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
565 {
566 return RTL_R8(PHYstatus) & LinkStatus;
567 }
568
569 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
570 {
571 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
572 }
573
574 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
575 {
576 unsigned int val;
577
578 val = (mdio_read(ioaddr, MII_BMCR) | BMCR_RESET) & 0xffff;
579 mdio_write(ioaddr, MII_BMCR, val);
580 }
581
582 static void rtl8169_check_link_status(struct net_device *dev,
583 struct rtl8169_private *tp, void __iomem *ioaddr)
584 {
585 unsigned long flags;
586
587 spin_lock_irqsave(&tp->lock, flags);
588 if (tp->link_ok(ioaddr)) {
589 netif_carrier_on(dev);
590 if (netif_msg_ifup(tp))
591 printk(KERN_INFO PFX "%s: link up\n", dev->name);
592 } else {
593 if (netif_msg_ifdown(tp))
594 printk(KERN_INFO PFX "%s: link down\n", dev->name);
595 netif_carrier_off(dev);
596 }
597 spin_unlock_irqrestore(&tp->lock, flags);
598 }
599
600 static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
601 {
602 struct {
603 u16 speed;
604 u8 duplex;
605 u8 autoneg;
606 u8 media;
607 } link_settings[] = {
608 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
609 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
610 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
611 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
612 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
613 /* Make TBI happy */
614 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
615 }, *p;
616 unsigned char option;
617
618 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
619
620 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
621 printk(KERN_WARNING PFX "media option is deprecated.\n");
622
623 for (p = link_settings; p->media != 0xff; p++) {
624 if (p->media == option)
625 break;
626 }
627 *autoneg = p->autoneg;
628 *speed = p->speed;
629 *duplex = p->duplex;
630 }
631
632 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
633 {
634 struct rtl8169_private *tp = netdev_priv(dev);
635 void __iomem *ioaddr = tp->mmio_addr;
636 u8 options;
637
638 wol->wolopts = 0;
639
640 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
641 wol->supported = WAKE_ANY;
642
643 spin_lock_irq(&tp->lock);
644
645 options = RTL_R8(Config1);
646 if (!(options & PMEnable))
647 goto out_unlock;
648
649 options = RTL_R8(Config3);
650 if (options & LinkUp)
651 wol->wolopts |= WAKE_PHY;
652 if (options & MagicPacket)
653 wol->wolopts |= WAKE_MAGIC;
654
655 options = RTL_R8(Config5);
656 if (options & UWF)
657 wol->wolopts |= WAKE_UCAST;
658 if (options & BWF)
659 wol->wolopts |= WAKE_BCAST;
660 if (options & MWF)
661 wol->wolopts |= WAKE_MCAST;
662
663 out_unlock:
664 spin_unlock_irq(&tp->lock);
665 }
666
667 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
668 {
669 struct rtl8169_private *tp = netdev_priv(dev);
670 void __iomem *ioaddr = tp->mmio_addr;
671 int i;
672 static struct {
673 u32 opt;
674 u16 reg;
675 u8 mask;
676 } cfg[] = {
677 { WAKE_ANY, Config1, PMEnable },
678 { WAKE_PHY, Config3, LinkUp },
679 { WAKE_MAGIC, Config3, MagicPacket },
680 { WAKE_UCAST, Config5, UWF },
681 { WAKE_BCAST, Config5, BWF },
682 { WAKE_MCAST, Config5, MWF },
683 { WAKE_ANY, Config5, LanWake }
684 };
685
686 spin_lock_irq(&tp->lock);
687
688 RTL_W8(Cfg9346, Cfg9346_Unlock);
689
690 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
691 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
692 if (wol->wolopts & cfg[i].opt)
693 options |= cfg[i].mask;
694 RTL_W8(cfg[i].reg, options);
695 }
696
697 RTL_W8(Cfg9346, Cfg9346_Lock);
698
699 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
700
701 spin_unlock_irq(&tp->lock);
702
703 return 0;
704 }
705
706 static void rtl8169_get_drvinfo(struct net_device *dev,
707 struct ethtool_drvinfo *info)
708 {
709 struct rtl8169_private *tp = netdev_priv(dev);
710
711 strcpy(info->driver, MODULENAME);
712 strcpy(info->version, RTL8169_VERSION);
713 strcpy(info->bus_info, pci_name(tp->pci_dev));
714 }
715
716 static int rtl8169_get_regs_len(struct net_device *dev)
717 {
718 return R8169_REGS_SIZE;
719 }
720
721 static int rtl8169_set_speed_tbi(struct net_device *dev,
722 u8 autoneg, u16 speed, u8 duplex)
723 {
724 struct rtl8169_private *tp = netdev_priv(dev);
725 void __iomem *ioaddr = tp->mmio_addr;
726 int ret = 0;
727 u32 reg;
728
729 reg = RTL_R32(TBICSR);
730 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
731 (duplex == DUPLEX_FULL)) {
732 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
733 } else if (autoneg == AUTONEG_ENABLE)
734 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
735 else {
736 if (netif_msg_link(tp)) {
737 printk(KERN_WARNING "%s: "
738 "incorrect speed setting refused in TBI mode\n",
739 dev->name);
740 }
741 ret = -EOPNOTSUPP;
742 }
743
744 return ret;
745 }
746
747 static int rtl8169_set_speed_xmii(struct net_device *dev,
748 u8 autoneg, u16 speed, u8 duplex)
749 {
750 struct rtl8169_private *tp = netdev_priv(dev);
751 void __iomem *ioaddr = tp->mmio_addr;
752 int auto_nego, giga_ctrl;
753
754 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
755 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
756 ADVERTISE_100HALF | ADVERTISE_100FULL);
757 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
758 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
759
760 if (autoneg == AUTONEG_ENABLE) {
761 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
762 ADVERTISE_100HALF | ADVERTISE_100FULL);
763 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
764 } else {
765 if (speed == SPEED_10)
766 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
767 else if (speed == SPEED_100)
768 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
769 else if (speed == SPEED_1000)
770 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
771
772 if (duplex == DUPLEX_HALF)
773 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
774
775 if (duplex == DUPLEX_FULL)
776 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
777
778 /* This tweak comes straight from Realtek's driver. */
779 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
780 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
781 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
782 }
783 }
784
785 /* The 8100e/8101e do Fast Ethernet only. */
786 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
787 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
788 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
789 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
790 netif_msg_link(tp)) {
791 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
792 dev->name);
793 }
794 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
795 }
796
797 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
798
799 tp->phy_auto_nego_reg = auto_nego;
800 tp->phy_1000_ctrl_reg = giga_ctrl;
801
802 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
803 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
804 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
805 return 0;
806 }
807
808 static int rtl8169_set_speed(struct net_device *dev,
809 u8 autoneg, u16 speed, u8 duplex)
810 {
811 struct rtl8169_private *tp = netdev_priv(dev);
812 int ret;
813
814 ret = tp->set_speed(dev, autoneg, speed, duplex);
815
816 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
817 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
818
819 return ret;
820 }
821
822 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
823 {
824 struct rtl8169_private *tp = netdev_priv(dev);
825 unsigned long flags;
826 int ret;
827
828 spin_lock_irqsave(&tp->lock, flags);
829 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
830 spin_unlock_irqrestore(&tp->lock, flags);
831
832 return ret;
833 }
834
835 static u32 rtl8169_get_rx_csum(struct net_device *dev)
836 {
837 struct rtl8169_private *tp = netdev_priv(dev);
838
839 return tp->cp_cmd & RxChkSum;
840 }
841
842 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
843 {
844 struct rtl8169_private *tp = netdev_priv(dev);
845 void __iomem *ioaddr = tp->mmio_addr;
846 unsigned long flags;
847
848 spin_lock_irqsave(&tp->lock, flags);
849
850 if (data)
851 tp->cp_cmd |= RxChkSum;
852 else
853 tp->cp_cmd &= ~RxChkSum;
854
855 RTL_W16(CPlusCmd, tp->cp_cmd);
856 RTL_R16(CPlusCmd);
857
858 spin_unlock_irqrestore(&tp->lock, flags);
859
860 return 0;
861 }
862
863 #ifdef CONFIG_R8169_VLAN
864
865 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
866 struct sk_buff *skb)
867 {
868 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
869 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
870 }
871
872 static void rtl8169_vlan_rx_register(struct net_device *dev,
873 struct vlan_group *grp)
874 {
875 struct rtl8169_private *tp = netdev_priv(dev);
876 void __iomem *ioaddr = tp->mmio_addr;
877 unsigned long flags;
878
879 spin_lock_irqsave(&tp->lock, flags);
880 tp->vlgrp = grp;
881 if (tp->vlgrp)
882 tp->cp_cmd |= RxVlan;
883 else
884 tp->cp_cmd &= ~RxVlan;
885 RTL_W16(CPlusCmd, tp->cp_cmd);
886 RTL_R16(CPlusCmd);
887 spin_unlock_irqrestore(&tp->lock, flags);
888 }
889
890 static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
891 {
892 struct rtl8169_private *tp = netdev_priv(dev);
893 unsigned long flags;
894
895 spin_lock_irqsave(&tp->lock, flags);
896 if (tp->vlgrp)
897 tp->vlgrp->vlan_devices[vid] = NULL;
898 spin_unlock_irqrestore(&tp->lock, flags);
899 }
900
901 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
902 struct sk_buff *skb)
903 {
904 u32 opts2 = le32_to_cpu(desc->opts2);
905 int ret;
906
907 if (tp->vlgrp && (opts2 & RxVlanTag)) {
908 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
909 swab16(opts2 & 0xffff));
910 ret = 0;
911 } else
912 ret = -1;
913 desc->opts2 = 0;
914 return ret;
915 }
916
917 #else /* !CONFIG_R8169_VLAN */
918
919 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
920 struct sk_buff *skb)
921 {
922 return 0;
923 }
924
925 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
926 struct sk_buff *skb)
927 {
928 return -1;
929 }
930
931 #endif
932
933 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
934 {
935 struct rtl8169_private *tp = netdev_priv(dev);
936 void __iomem *ioaddr = tp->mmio_addr;
937 u32 status;
938
939 cmd->supported =
940 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
941 cmd->port = PORT_FIBRE;
942 cmd->transceiver = XCVR_INTERNAL;
943
944 status = RTL_R32(TBICSR);
945 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
946 cmd->autoneg = !!(status & TBINwEnable);
947
948 cmd->speed = SPEED_1000;
949 cmd->duplex = DUPLEX_FULL; /* Always set */
950 }
951
952 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
953 {
954 struct rtl8169_private *tp = netdev_priv(dev);
955 void __iomem *ioaddr = tp->mmio_addr;
956 u8 status;
957
958 cmd->supported = SUPPORTED_10baseT_Half |
959 SUPPORTED_10baseT_Full |
960 SUPPORTED_100baseT_Half |
961 SUPPORTED_100baseT_Full |
962 SUPPORTED_1000baseT_Full |
963 SUPPORTED_Autoneg |
964 SUPPORTED_TP;
965
966 cmd->autoneg = 1;
967 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
968
969 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
970 cmd->advertising |= ADVERTISED_10baseT_Half;
971 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
972 cmd->advertising |= ADVERTISED_10baseT_Full;
973 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
974 cmd->advertising |= ADVERTISED_100baseT_Half;
975 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
976 cmd->advertising |= ADVERTISED_100baseT_Full;
977 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
978 cmd->advertising |= ADVERTISED_1000baseT_Full;
979
980 status = RTL_R8(PHYstatus);
981
982 if (status & _1000bpsF)
983 cmd->speed = SPEED_1000;
984 else if (status & _100bps)
985 cmd->speed = SPEED_100;
986 else if (status & _10bps)
987 cmd->speed = SPEED_10;
988
989 if (status & TxFlowCtrl)
990 cmd->advertising |= ADVERTISED_Asym_Pause;
991 if (status & RxFlowCtrl)
992 cmd->advertising |= ADVERTISED_Pause;
993
994 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
995 DUPLEX_FULL : DUPLEX_HALF;
996 }
997
998 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
999 {
1000 struct rtl8169_private *tp = netdev_priv(dev);
1001 unsigned long flags;
1002
1003 spin_lock_irqsave(&tp->lock, flags);
1004
1005 tp->get_settings(dev, cmd);
1006
1007 spin_unlock_irqrestore(&tp->lock, flags);
1008 return 0;
1009 }
1010
1011 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1012 void *p)
1013 {
1014 struct rtl8169_private *tp = netdev_priv(dev);
1015 unsigned long flags;
1016
1017 if (regs->len > R8169_REGS_SIZE)
1018 regs->len = R8169_REGS_SIZE;
1019
1020 spin_lock_irqsave(&tp->lock, flags);
1021 memcpy_fromio(p, tp->mmio_addr, regs->len);
1022 spin_unlock_irqrestore(&tp->lock, flags);
1023 }
1024
1025 static u32 rtl8169_get_msglevel(struct net_device *dev)
1026 {
1027 struct rtl8169_private *tp = netdev_priv(dev);
1028
1029 return tp->msg_enable;
1030 }
1031
1032 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1033 {
1034 struct rtl8169_private *tp = netdev_priv(dev);
1035
1036 tp->msg_enable = value;
1037 }
1038
1039 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1040 "tx_packets",
1041 "rx_packets",
1042 "tx_errors",
1043 "rx_errors",
1044 "rx_missed",
1045 "align_errors",
1046 "tx_single_collisions",
1047 "tx_multi_collisions",
1048 "unicast",
1049 "broadcast",
1050 "multicast",
1051 "tx_aborted",
1052 "tx_underrun",
1053 };
1054
1055 struct rtl8169_counters {
1056 u64 tx_packets;
1057 u64 rx_packets;
1058 u64 tx_errors;
1059 u32 rx_errors;
1060 u16 rx_missed;
1061 u16 align_errors;
1062 u32 tx_one_collision;
1063 u32 tx_multi_collision;
1064 u64 rx_unicast;
1065 u64 rx_broadcast;
1066 u32 rx_multicast;
1067 u16 tx_aborted;
1068 u16 tx_underun;
1069 };
1070
1071 static int rtl8169_get_stats_count(struct net_device *dev)
1072 {
1073 return ARRAY_SIZE(rtl8169_gstrings);
1074 }
1075
1076 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1077 struct ethtool_stats *stats, u64 *data)
1078 {
1079 struct rtl8169_private *tp = netdev_priv(dev);
1080 void __iomem *ioaddr = tp->mmio_addr;
1081 struct rtl8169_counters *counters;
1082 dma_addr_t paddr;
1083 u32 cmd;
1084
1085 ASSERT_RTNL();
1086
1087 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1088 if (!counters)
1089 return;
1090
1091 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1092 cmd = (u64)paddr & DMA_32BIT_MASK;
1093 RTL_W32(CounterAddrLow, cmd);
1094 RTL_W32(CounterAddrLow, cmd | CounterDump);
1095
1096 while (RTL_R32(CounterAddrLow) & CounterDump) {
1097 if (msleep_interruptible(1))
1098 break;
1099 }
1100
1101 RTL_W32(CounterAddrLow, 0);
1102 RTL_W32(CounterAddrHigh, 0);
1103
1104 data[0] = le64_to_cpu(counters->tx_packets);
1105 data[1] = le64_to_cpu(counters->rx_packets);
1106 data[2] = le64_to_cpu(counters->tx_errors);
1107 data[3] = le32_to_cpu(counters->rx_errors);
1108 data[4] = le16_to_cpu(counters->rx_missed);
1109 data[5] = le16_to_cpu(counters->align_errors);
1110 data[6] = le32_to_cpu(counters->tx_one_collision);
1111 data[7] = le32_to_cpu(counters->tx_multi_collision);
1112 data[8] = le64_to_cpu(counters->rx_unicast);
1113 data[9] = le64_to_cpu(counters->rx_broadcast);
1114 data[10] = le32_to_cpu(counters->rx_multicast);
1115 data[11] = le16_to_cpu(counters->tx_aborted);
1116 data[12] = le16_to_cpu(counters->tx_underun);
1117
1118 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1119 }
1120
1121 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1122 {
1123 switch(stringset) {
1124 case ETH_SS_STATS:
1125 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1126 break;
1127 }
1128 }
1129
1130
1131 static const struct ethtool_ops rtl8169_ethtool_ops = {
1132 .get_drvinfo = rtl8169_get_drvinfo,
1133 .get_regs_len = rtl8169_get_regs_len,
1134 .get_link = ethtool_op_get_link,
1135 .get_settings = rtl8169_get_settings,
1136 .set_settings = rtl8169_set_settings,
1137 .get_msglevel = rtl8169_get_msglevel,
1138 .set_msglevel = rtl8169_set_msglevel,
1139 .get_rx_csum = rtl8169_get_rx_csum,
1140 .set_rx_csum = rtl8169_set_rx_csum,
1141 .get_tx_csum = ethtool_op_get_tx_csum,
1142 .set_tx_csum = ethtool_op_set_tx_csum,
1143 .get_sg = ethtool_op_get_sg,
1144 .set_sg = ethtool_op_set_sg,
1145 .get_tso = ethtool_op_get_tso,
1146 .set_tso = ethtool_op_set_tso,
1147 .get_regs = rtl8169_get_regs,
1148 .get_wol = rtl8169_get_wol,
1149 .set_wol = rtl8169_set_wol,
1150 .get_strings = rtl8169_get_strings,
1151 .get_stats_count = rtl8169_get_stats_count,
1152 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1153 .get_perm_addr = ethtool_op_get_perm_addr,
1154 };
1155
1156 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1157 int bitval)
1158 {
1159 int val;
1160
1161 val = mdio_read(ioaddr, reg);
1162 val = (bitval == 1) ?
1163 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1164 mdio_write(ioaddr, reg, val & 0xffff);
1165 }
1166
1167 static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1168 {
1169 const struct {
1170 u32 mask;
1171 int mac_version;
1172 } mac_info[] = {
1173 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1174 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1175 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1176 { 0x30800000, RTL_GIGA_MAC_VER_14 },
1177 { 0x30000000, RTL_GIGA_MAC_VER_11 },
1178 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1179 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1180 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1181 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1182 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1183 }, *p = mac_info;
1184 u32 reg;
1185
1186 reg = RTL_R32(TxConfig) & 0x7c800000;
1187 while ((reg & p->mask) != p->mask)
1188 p++;
1189 tp->mac_version = p->mac_version;
1190 }
1191
1192 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1193 {
1194 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1195 }
1196
1197 static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1198 {
1199 const struct {
1200 u16 mask;
1201 u16 set;
1202 int phy_version;
1203 } phy_info[] = {
1204 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1205 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1206 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1207 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1208 }, *p = phy_info;
1209 u16 reg;
1210
1211 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1212 while ((reg & p->mask) != p->set)
1213 p++;
1214 tp->phy_version = p->phy_version;
1215 }
1216
1217 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1218 {
1219 struct {
1220 int version;
1221 char *msg;
1222 u32 reg;
1223 } phy_print[] = {
1224 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1225 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1226 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1227 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1228 { 0, NULL, 0x0000 }
1229 }, *p;
1230
1231 for (p = phy_print; p->msg; p++) {
1232 if (tp->phy_version == p->version) {
1233 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1234 return;
1235 }
1236 }
1237 dprintk("phy_version == Unknown\n");
1238 }
1239
1240 static void rtl8169_hw_phy_config(struct net_device *dev)
1241 {
1242 struct rtl8169_private *tp = netdev_priv(dev);
1243 void __iomem *ioaddr = tp->mmio_addr;
1244 struct {
1245 u16 regs[5]; /* Beware of bit-sign propagation */
1246 } phy_magic[5] = { {
1247 { 0x0000, //w 4 15 12 0
1248 0x00a1, //w 3 15 0 00a1
1249 0x0008, //w 2 15 0 0008
1250 0x1020, //w 1 15 0 1020
1251 0x1000 } },{ //w 0 15 0 1000
1252 { 0x7000, //w 4 15 12 7
1253 0xff41, //w 3 15 0 ff41
1254 0xde60, //w 2 15 0 de60
1255 0x0140, //w 1 15 0 0140
1256 0x0077 } },{ //w 0 15 0 0077
1257 { 0xa000, //w 4 15 12 a
1258 0xdf01, //w 3 15 0 df01
1259 0xdf20, //w 2 15 0 df20
1260 0xff95, //w 1 15 0 ff95
1261 0xfa00 } },{ //w 0 15 0 fa00
1262 { 0xb000, //w 4 15 12 b
1263 0xff41, //w 3 15 0 ff41
1264 0xde20, //w 2 15 0 de20
1265 0x0140, //w 1 15 0 0140
1266 0x00bb } },{ //w 0 15 0 00bb
1267 { 0xf000, //w 4 15 12 f
1268 0xdf01, //w 3 15 0 df01
1269 0xdf20, //w 2 15 0 df20
1270 0xff95, //w 1 15 0 ff95
1271 0xbf00 } //w 0 15 0 bf00
1272 }
1273 }, *p = phy_magic;
1274 int i;
1275
1276 rtl8169_print_mac_version(tp);
1277 rtl8169_print_phy_version(tp);
1278
1279 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1280 return;
1281 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1282 return;
1283
1284 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1285 dprintk("Do final_reg2.cfg\n");
1286
1287 /* Shazam ! */
1288
1289 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1290 mdio_write(ioaddr, 31, 0x0001);
1291 mdio_write(ioaddr, 9, 0x273a);
1292 mdio_write(ioaddr, 14, 0x7bfb);
1293 mdio_write(ioaddr, 27, 0x841e);
1294
1295 mdio_write(ioaddr, 31, 0x0002);
1296 mdio_write(ioaddr, 1, 0x90d0);
1297 mdio_write(ioaddr, 31, 0x0000);
1298 return;
1299 }
1300
1301 /* phy config for RTL8169s mac_version C chip */
1302 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1303 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1304 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1305 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1306
1307 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1308 int val, pos = 4;
1309
1310 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1311 mdio_write(ioaddr, pos, val);
1312 while (--pos >= 0)
1313 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1314 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1315 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1316 }
1317 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1318 }
1319
1320 static void rtl8169_phy_timer(unsigned long __opaque)
1321 {
1322 struct net_device *dev = (struct net_device *)__opaque;
1323 struct rtl8169_private *tp = netdev_priv(dev);
1324 struct timer_list *timer = &tp->timer;
1325 void __iomem *ioaddr = tp->mmio_addr;
1326 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1327
1328 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1329 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1330
1331 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1332 return;
1333
1334 spin_lock_irq(&tp->lock);
1335
1336 if (tp->phy_reset_pending(ioaddr)) {
1337 /*
1338 * A busy loop could burn quite a few cycles on nowadays CPU.
1339 * Let's delay the execution of the timer for a few ticks.
1340 */
1341 timeout = HZ/10;
1342 goto out_mod_timer;
1343 }
1344
1345 if (tp->link_ok(ioaddr))
1346 goto out_unlock;
1347
1348 if (netif_msg_link(tp))
1349 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1350
1351 tp->phy_reset_enable(ioaddr);
1352
1353 out_mod_timer:
1354 mod_timer(timer, jiffies + timeout);
1355 out_unlock:
1356 spin_unlock_irq(&tp->lock);
1357 }
1358
1359 static inline void rtl8169_delete_timer(struct net_device *dev)
1360 {
1361 struct rtl8169_private *tp = netdev_priv(dev);
1362 struct timer_list *timer = &tp->timer;
1363
1364 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1365 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1366 return;
1367
1368 del_timer_sync(timer);
1369 }
1370
1371 static inline void rtl8169_request_timer(struct net_device *dev)
1372 {
1373 struct rtl8169_private *tp = netdev_priv(dev);
1374 struct timer_list *timer = &tp->timer;
1375
1376 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1377 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1378 return;
1379
1380 init_timer(timer);
1381 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1382 timer->data = (unsigned long)(dev);
1383 timer->function = rtl8169_phy_timer;
1384 add_timer(timer);
1385 }
1386
1387 #ifdef CONFIG_NET_POLL_CONTROLLER
1388 /*
1389 * Polling 'interrupt' - used by things like netconsole to send skbs
1390 * without having to re-enable interrupts. It's not called while
1391 * the interrupt routine is executing.
1392 */
1393 static void rtl8169_netpoll(struct net_device *dev)
1394 {
1395 struct rtl8169_private *tp = netdev_priv(dev);
1396 struct pci_dev *pdev = tp->pci_dev;
1397
1398 disable_irq(pdev->irq);
1399 rtl8169_interrupt(pdev->irq, dev);
1400 enable_irq(pdev->irq);
1401 }
1402 #endif
1403
1404 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1405 void __iomem *ioaddr)
1406 {
1407 iounmap(ioaddr);
1408 pci_release_regions(pdev);
1409 pci_disable_device(pdev);
1410 free_netdev(dev);
1411 }
1412
1413 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1414 {
1415 void __iomem *ioaddr = tp->mmio_addr;
1416 static int board_idx = -1;
1417 u8 autoneg, duplex;
1418 u16 speed;
1419
1420 board_idx++;
1421
1422 rtl8169_hw_phy_config(dev);
1423
1424 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1425 RTL_W8(0x82, 0x01);
1426
1427 if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
1428 dprintk("Set PCI Latency=0x40\n");
1429 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1430 }
1431
1432 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1433 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1434 RTL_W8(0x82, 0x01);
1435 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1436 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1437 }
1438
1439 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1440
1441 rtl8169_set_speed(dev, autoneg, speed, duplex);
1442
1443 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1444 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1445 }
1446
1447 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1448 {
1449 struct rtl8169_private *tp = netdev_priv(dev);
1450 struct mii_ioctl_data *data = if_mii(ifr);
1451
1452 if (!netif_running(dev))
1453 return -ENODEV;
1454
1455 switch (cmd) {
1456 case SIOCGMIIPHY:
1457 data->phy_id = 32; /* Internal PHY */
1458 return 0;
1459
1460 case SIOCGMIIREG:
1461 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1462 return 0;
1463
1464 case SIOCSMIIREG:
1465 if (!capable(CAP_NET_ADMIN))
1466 return -EPERM;
1467 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1468 return 0;
1469 }
1470 return -EOPNOTSUPP;
1471 }
1472
1473 static int __devinit
1474 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1475 {
1476 const unsigned int region = rtl_cfg_info[ent->driver_data].region;
1477 struct rtl8169_private *tp;
1478 struct net_device *dev;
1479 void __iomem *ioaddr;
1480 unsigned int pm_cap;
1481 int i, rc;
1482
1483 if (netif_msg_drv(&debug)) {
1484 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1485 MODULENAME, RTL8169_VERSION);
1486 }
1487
1488 dev = alloc_etherdev(sizeof (*tp));
1489 if (!dev) {
1490 if (netif_msg_drv(&debug))
1491 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1492 rc = -ENOMEM;
1493 goto out;
1494 }
1495
1496 SET_MODULE_OWNER(dev);
1497 SET_NETDEV_DEV(dev, &pdev->dev);
1498 tp = netdev_priv(dev);
1499 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1500
1501 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1502 rc = pci_enable_device(pdev);
1503 if (rc < 0) {
1504 if (netif_msg_probe(tp))
1505 dev_err(&pdev->dev, "enable failure\n");
1506 goto err_out_free_dev_1;
1507 }
1508
1509 rc = pci_set_mwi(pdev);
1510 if (rc < 0)
1511 goto err_out_disable_2;
1512
1513 /* save power state before pci_enable_device overwrites it */
1514 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1515 if (pm_cap) {
1516 u16 pwr_command, acpi_idle_state;
1517
1518 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1519 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1520 } else {
1521 if (netif_msg_probe(tp)) {
1522 dev_err(&pdev->dev,
1523 "PowerManagement capability not found.\n");
1524 }
1525 }
1526
1527 /* make sure PCI base addr 1 is MMIO */
1528 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1529 if (netif_msg_probe(tp)) {
1530 dev_err(&pdev->dev,
1531 "region #%d not an MMIO resource, aborting\n",
1532 region);
1533 }
1534 rc = -ENODEV;
1535 goto err_out_mwi_3;
1536 }
1537
1538 /* check for weird/broken PCI region reporting */
1539 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1540 if (netif_msg_probe(tp)) {
1541 dev_err(&pdev->dev,
1542 "Invalid PCI region size(s), aborting\n");
1543 }
1544 rc = -ENODEV;
1545 goto err_out_mwi_3;
1546 }
1547
1548 rc = pci_request_regions(pdev, MODULENAME);
1549 if (rc < 0) {
1550 if (netif_msg_probe(tp))
1551 dev_err(&pdev->dev, "could not request regions.\n");
1552 goto err_out_mwi_3;
1553 }
1554
1555 tp->cp_cmd = PCIMulRW | RxChkSum;
1556
1557 if ((sizeof(dma_addr_t) > 4) &&
1558 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1559 tp->cp_cmd |= PCIDAC;
1560 dev->features |= NETIF_F_HIGHDMA;
1561 } else {
1562 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1563 if (rc < 0) {
1564 if (netif_msg_probe(tp)) {
1565 dev_err(&pdev->dev,
1566 "DMA configuration failed.\n");
1567 }
1568 goto err_out_free_res_4;
1569 }
1570 }
1571
1572 pci_set_master(pdev);
1573
1574 /* ioremap MMIO region */
1575 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1576 if (!ioaddr) {
1577 if (netif_msg_probe(tp))
1578 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1579 rc = -EIO;
1580 goto err_out_free_res_4;
1581 }
1582
1583 /* Unneeded ? Don't mess with Mrs. Murphy. */
1584 rtl8169_irq_mask_and_ack(ioaddr);
1585
1586 /* Soft reset the chip. */
1587 RTL_W8(ChipCmd, CmdReset);
1588
1589 /* Check that the chip has finished the reset. */
1590 for (i = 100; i > 0; i--) {
1591 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1592 break;
1593 msleep_interruptible(1);
1594 }
1595
1596 /* Identify chip attached to board */
1597 rtl8169_get_mac_version(tp, ioaddr);
1598 rtl8169_get_phy_version(tp, ioaddr);
1599
1600 rtl8169_print_mac_version(tp);
1601 rtl8169_print_phy_version(tp);
1602
1603 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1604 if (tp->mac_version == rtl_chip_info[i].mac_version)
1605 break;
1606 }
1607 if (i < 0) {
1608 /* Unknown chip: assume array element #0, original RTL-8169 */
1609 if (netif_msg_probe(tp)) {
1610 dev_printk(KERN_DEBUG, &pdev->dev,
1611 "unknown chip version, assuming %s\n",
1612 rtl_chip_info[0].name);
1613 }
1614 i++;
1615 }
1616 tp->chipset = i;
1617
1618 RTL_W8(Cfg9346, Cfg9346_Unlock);
1619 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1620 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1621 RTL_W8(Cfg9346, Cfg9346_Lock);
1622
1623 if (RTL_R8(PHYstatus) & TBI_Enable) {
1624 tp->set_speed = rtl8169_set_speed_tbi;
1625 tp->get_settings = rtl8169_gset_tbi;
1626 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1627 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1628 tp->link_ok = rtl8169_tbi_link_ok;
1629
1630 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1631 } else {
1632 tp->set_speed = rtl8169_set_speed_xmii;
1633 tp->get_settings = rtl8169_gset_xmii;
1634 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1635 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1636 tp->link_ok = rtl8169_xmii_link_ok;
1637
1638 dev->do_ioctl = rtl8169_ioctl;
1639 }
1640
1641 /* Get MAC address. FIXME: read EEPROM */
1642 for (i = 0; i < MAC_ADDR_LEN; i++)
1643 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1644 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1645
1646 dev->open = rtl8169_open;
1647 dev->hard_start_xmit = rtl8169_start_xmit;
1648 dev->get_stats = rtl8169_get_stats;
1649 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1650 dev->stop = rtl8169_close;
1651 dev->tx_timeout = rtl8169_tx_timeout;
1652 dev->set_multicast_list = rtl8169_set_rx_mode;
1653 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1654 dev->irq = pdev->irq;
1655 dev->base_addr = (unsigned long) ioaddr;
1656 dev->change_mtu = rtl8169_change_mtu;
1657
1658 #ifdef CONFIG_R8169_NAPI
1659 dev->poll = rtl8169_poll;
1660 dev->weight = R8169_NAPI_WEIGHT;
1661 #endif
1662
1663 #ifdef CONFIG_R8169_VLAN
1664 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1665 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1666 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1667 #endif
1668
1669 #ifdef CONFIG_NET_POLL_CONTROLLER
1670 dev->poll_controller = rtl8169_netpoll;
1671 #endif
1672
1673 tp->intr_mask = 0xffff;
1674 tp->pci_dev = pdev;
1675 tp->mmio_addr = ioaddr;
1676 tp->align = rtl_cfg_info[ent->driver_data].align;
1677
1678 spin_lock_init(&tp->lock);
1679
1680 rc = register_netdev(dev);
1681 if (rc < 0)
1682 goto err_out_unmap_5;
1683
1684 pci_set_drvdata(pdev, dev);
1685
1686 if (netif_msg_probe(tp)) {
1687 printk(KERN_INFO "%s: %s at 0x%lx, "
1688 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1689 "IRQ %d\n",
1690 dev->name,
1691 rtl_chip_info[tp->chipset].name,
1692 dev->base_addr,
1693 dev->dev_addr[0], dev->dev_addr[1],
1694 dev->dev_addr[2], dev->dev_addr[3],
1695 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1696 }
1697
1698 rtl8169_init_phy(dev, tp);
1699
1700 out:
1701 return rc;
1702
1703 err_out_unmap_5:
1704 iounmap(ioaddr);
1705 err_out_free_res_4:
1706 pci_release_regions(pdev);
1707 err_out_mwi_3:
1708 pci_clear_mwi(pdev);
1709 err_out_disable_2:
1710 pci_disable_device(pdev);
1711 err_out_free_dev_1:
1712 free_netdev(dev);
1713 goto out;
1714 }
1715
1716 static void __devexit
1717 rtl8169_remove_one(struct pci_dev *pdev)
1718 {
1719 struct net_device *dev = pci_get_drvdata(pdev);
1720 struct rtl8169_private *tp = netdev_priv(dev);
1721
1722 assert(dev != NULL);
1723 assert(tp != NULL);
1724
1725 unregister_netdev(dev);
1726 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1727 pci_set_drvdata(pdev, NULL);
1728 }
1729
1730 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1731 struct net_device *dev)
1732 {
1733 unsigned int mtu = dev->mtu;
1734
1735 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1736 }
1737
1738 static int rtl8169_open(struct net_device *dev)
1739 {
1740 struct rtl8169_private *tp = netdev_priv(dev);
1741 struct pci_dev *pdev = tp->pci_dev;
1742 int retval;
1743
1744 rtl8169_set_rxbufsize(tp, dev);
1745
1746 retval =
1747 request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED, dev->name, dev);
1748 if (retval < 0)
1749 goto out;
1750
1751 retval = -ENOMEM;
1752
1753 /*
1754 * Rx and Tx desscriptors needs 256 bytes alignment.
1755 * pci_alloc_consistent provides more.
1756 */
1757 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1758 &tp->TxPhyAddr);
1759 if (!tp->TxDescArray)
1760 goto err_free_irq;
1761
1762 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1763 &tp->RxPhyAddr);
1764 if (!tp->RxDescArray)
1765 goto err_free_tx;
1766
1767 retval = rtl8169_init_ring(dev);
1768 if (retval < 0)
1769 goto err_free_rx;
1770
1771 INIT_WORK(&tp->task, NULL, dev);
1772
1773 rtl8169_hw_start(dev);
1774
1775 rtl8169_request_timer(dev);
1776
1777 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1778 out:
1779 return retval;
1780
1781 err_free_rx:
1782 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1783 tp->RxPhyAddr);
1784 err_free_tx:
1785 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1786 tp->TxPhyAddr);
1787 err_free_irq:
1788 free_irq(dev->irq, dev);
1789 goto out;
1790 }
1791
1792 static void rtl8169_hw_reset(void __iomem *ioaddr)
1793 {
1794 /* Disable interrupts */
1795 rtl8169_irq_mask_and_ack(ioaddr);
1796
1797 /* Reset the chipset */
1798 RTL_W8(ChipCmd, CmdReset);
1799
1800 /* PCI commit */
1801 RTL_R8(ChipCmd);
1802 }
1803
1804 static void rtl8169_set_rx_tx_config_registers(struct rtl8169_private *tp)
1805 {
1806 void __iomem *ioaddr = tp->mmio_addr;
1807 u32 cfg = rtl8169_rx_config;
1808
1809 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1810 RTL_W32(RxConfig, cfg);
1811
1812 /* Set DMA burst size and Interframe Gap Time */
1813 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1814 (InterFrameGap << TxInterFrameGapShift));
1815 }
1816
1817 static void rtl8169_hw_start(struct net_device *dev)
1818 {
1819 struct rtl8169_private *tp = netdev_priv(dev);
1820 void __iomem *ioaddr = tp->mmio_addr;
1821 struct pci_dev *pdev = tp->pci_dev;
1822 u16 cmd;
1823 u32 i;
1824
1825 /* Soft reset the chip. */
1826 RTL_W8(ChipCmd, CmdReset);
1827
1828 /* Check that the chip has finished the reset. */
1829 for (i = 100; i > 0; i--) {
1830 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1831 break;
1832 msleep_interruptible(1);
1833 }
1834
1835 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1836 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1837 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1838 }
1839
1840 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1841 pci_write_config_word(pdev, 0x68, 0x00);
1842 pci_write_config_word(pdev, 0x69, 0x08);
1843 }
1844
1845 /* Undocumented stuff. */
1846 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1847 /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
1848 if ((RTL_R8(Config2) & 0x07) & 0x01)
1849 RTL_W32(0x7c, 0x0007ffff);
1850
1851 RTL_W32(0x7c, 0x0007ff00);
1852
1853 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1854 cmd = cmd & 0xef;
1855 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1856 }
1857
1858 RTL_W8(Cfg9346, Cfg9346_Unlock);
1859 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1860 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1861 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1862 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1863 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1864
1865 RTL_W8(EarlyTxThres, EarlyTxThld);
1866
1867 /* Restore our idea of the MAC address */
1868 for (i = 0; i < MAC_ADDR_LEN; i++)
1869 RTL_W8(MAC0 + i, dev->dev_addr[i]);
1870
1871 /* Low hurts. Let's disable the filtering. */
1872 RTL_W16(RxMaxSize, 16383);
1873
1874 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1875 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1876 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1877 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1878 rtl8169_set_rx_tx_config_registers(tp);
1879
1880 cmd = RTL_R16(CPlusCmd);
1881 RTL_W16(CPlusCmd, cmd);
1882
1883 tp->cp_cmd |= cmd | PCIMulRW;
1884
1885 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1886 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1887 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1888 "Bit-3 and bit-14 MUST be 1\n");
1889 tp->cp_cmd |= (1 << 14);
1890 }
1891
1892 RTL_W16(CPlusCmd, tp->cp_cmd);
1893
1894 /*
1895 * Undocumented corner. Supposedly:
1896 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1897 */
1898 RTL_W16(IntrMitigate, 0x0000);
1899
1900 /*
1901 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1902 * register to be written before TxDescAddrLow to work.
1903 * Switching from MMIO to I/O access fixes the issue as well.
1904 */
1905 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1906 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1907 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1908 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1909
1910 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1911 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1912 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1913 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1914 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1915 rtl8169_set_rx_tx_config_registers(tp);
1916 }
1917
1918 RTL_W8(Cfg9346, Cfg9346_Lock);
1919
1920 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1921 RTL_R8(IntrMask);
1922
1923 RTL_W32(RxMissed, 0);
1924
1925 rtl8169_set_rx_mode(dev);
1926
1927 /* no early-rx interrupts */
1928 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1929
1930 /* Enable all known interrupts by setting the interrupt mask. */
1931 RTL_W16(IntrMask, rtl8169_intr_mask);
1932
1933 netif_start_queue(dev);
1934 }
1935
1936 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1937 {
1938 struct rtl8169_private *tp = netdev_priv(dev);
1939 int ret = 0;
1940
1941 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1942 return -EINVAL;
1943
1944 dev->mtu = new_mtu;
1945
1946 if (!netif_running(dev))
1947 goto out;
1948
1949 rtl8169_down(dev);
1950
1951 rtl8169_set_rxbufsize(tp, dev);
1952
1953 ret = rtl8169_init_ring(dev);
1954 if (ret < 0)
1955 goto out;
1956
1957 netif_poll_enable(dev);
1958
1959 rtl8169_hw_start(dev);
1960
1961 rtl8169_request_timer(dev);
1962
1963 out:
1964 return ret;
1965 }
1966
1967 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1968 {
1969 desc->addr = 0x0badbadbadbadbadull;
1970 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1971 }
1972
1973 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1974 struct sk_buff **sk_buff, struct RxDesc *desc)
1975 {
1976 struct pci_dev *pdev = tp->pci_dev;
1977
1978 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1979 PCI_DMA_FROMDEVICE);
1980 dev_kfree_skb(*sk_buff);
1981 *sk_buff = NULL;
1982 rtl8169_make_unusable_by_asic(desc);
1983 }
1984
1985 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1986 {
1987 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1988
1989 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1990 }
1991
1992 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1993 u32 rx_buf_sz)
1994 {
1995 desc->addr = cpu_to_le64(mapping);
1996 wmb();
1997 rtl8169_mark_to_asic(desc, rx_buf_sz);
1998 }
1999
2000 static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
2001 struct RxDesc *desc, int rx_buf_sz,
2002 unsigned int align)
2003 {
2004 struct sk_buff *skb;
2005 dma_addr_t mapping;
2006 int ret = 0;
2007
2008 skb = dev_alloc_skb(rx_buf_sz + align);
2009 if (!skb)
2010 goto err_out;
2011
2012 skb_reserve(skb, align);
2013 *sk_buff = skb;
2014
2015 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2016 PCI_DMA_FROMDEVICE);
2017
2018 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2019
2020 out:
2021 return ret;
2022
2023 err_out:
2024 ret = -ENOMEM;
2025 rtl8169_make_unusable_by_asic(desc);
2026 goto out;
2027 }
2028
2029 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2030 {
2031 int i;
2032
2033 for (i = 0; i < NUM_RX_DESC; i++) {
2034 if (tp->Rx_skbuff[i]) {
2035 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2036 tp->RxDescArray + i);
2037 }
2038 }
2039 }
2040
2041 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2042 u32 start, u32 end)
2043 {
2044 u32 cur;
2045
2046 for (cur = start; end - cur > 0; cur++) {
2047 int ret, i = cur % NUM_RX_DESC;
2048
2049 if (tp->Rx_skbuff[i])
2050 continue;
2051
2052 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
2053 tp->RxDescArray + i, tp->rx_buf_sz, tp->align);
2054 if (ret < 0)
2055 break;
2056 }
2057 return cur - start;
2058 }
2059
2060 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2061 {
2062 desc->opts1 |= cpu_to_le32(RingEnd);
2063 }
2064
2065 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2066 {
2067 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2068 }
2069
2070 static int rtl8169_init_ring(struct net_device *dev)
2071 {
2072 struct rtl8169_private *tp = netdev_priv(dev);
2073
2074 rtl8169_init_ring_indexes(tp);
2075
2076 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2077 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2078
2079 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2080 goto err_out;
2081
2082 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2083
2084 return 0;
2085
2086 err_out:
2087 rtl8169_rx_clear(tp);
2088 return -ENOMEM;
2089 }
2090
2091 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2092 struct TxDesc *desc)
2093 {
2094 unsigned int len = tx_skb->len;
2095
2096 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2097 desc->opts1 = 0x00;
2098 desc->opts2 = 0x00;
2099 desc->addr = 0x00;
2100 tx_skb->len = 0;
2101 }
2102
2103 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2104 {
2105 unsigned int i;
2106
2107 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2108 unsigned int entry = i % NUM_TX_DESC;
2109 struct ring_info *tx_skb = tp->tx_skb + entry;
2110 unsigned int len = tx_skb->len;
2111
2112 if (len) {
2113 struct sk_buff *skb = tx_skb->skb;
2114
2115 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2116 tp->TxDescArray + entry);
2117 if (skb) {
2118 dev_kfree_skb(skb);
2119 tx_skb->skb = NULL;
2120 }
2121 tp->stats.tx_dropped++;
2122 }
2123 }
2124 tp->cur_tx = tp->dirty_tx = 0;
2125 }
2126
2127 static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
2128 {
2129 struct rtl8169_private *tp = netdev_priv(dev);
2130
2131 PREPARE_WORK(&tp->task, task, dev);
2132 schedule_delayed_work(&tp->task, 4);
2133 }
2134
2135 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2136 {
2137 struct rtl8169_private *tp = netdev_priv(dev);
2138 void __iomem *ioaddr = tp->mmio_addr;
2139
2140 synchronize_irq(dev->irq);
2141
2142 /* Wait for any pending NAPI task to complete */
2143 netif_poll_disable(dev);
2144
2145 rtl8169_irq_mask_and_ack(ioaddr);
2146
2147 netif_poll_enable(dev);
2148 }
2149
2150 static void rtl8169_reinit_task(void *_data)
2151 {
2152 struct net_device *dev = _data;
2153 int ret;
2154
2155 if (netif_running(dev)) {
2156 rtl8169_wait_for_quiescence(dev);
2157 rtl8169_close(dev);
2158 }
2159
2160 ret = rtl8169_open(dev);
2161 if (unlikely(ret < 0)) {
2162 if (net_ratelimit()) {
2163 struct rtl8169_private *tp = netdev_priv(dev);
2164
2165 if (netif_msg_drv(tp)) {
2166 printk(PFX KERN_ERR
2167 "%s: reinit failure (status = %d)."
2168 " Rescheduling.\n", dev->name, ret);
2169 }
2170 }
2171 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2172 }
2173 }
2174
2175 static void rtl8169_reset_task(void *_data)
2176 {
2177 struct net_device *dev = _data;
2178 struct rtl8169_private *tp = netdev_priv(dev);
2179
2180 if (!netif_running(dev))
2181 return;
2182
2183 rtl8169_wait_for_quiescence(dev);
2184
2185 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2186 rtl8169_tx_clear(tp);
2187
2188 if (tp->dirty_rx == tp->cur_rx) {
2189 rtl8169_init_ring_indexes(tp);
2190 rtl8169_hw_start(dev);
2191 netif_wake_queue(dev);
2192 } else {
2193 if (net_ratelimit()) {
2194 struct rtl8169_private *tp = netdev_priv(dev);
2195
2196 if (netif_msg_intr(tp)) {
2197 printk(PFX KERN_EMERG
2198 "%s: Rx buffers shortage\n", dev->name);
2199 }
2200 }
2201 rtl8169_schedule_work(dev, rtl8169_reset_task);
2202 }
2203 }
2204
2205 static void rtl8169_tx_timeout(struct net_device *dev)
2206 {
2207 struct rtl8169_private *tp = netdev_priv(dev);
2208
2209 rtl8169_hw_reset(tp->mmio_addr);
2210
2211 /* Let's wait a bit while any (async) irq lands on */
2212 rtl8169_schedule_work(dev, rtl8169_reset_task);
2213 }
2214
2215 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2216 u32 opts1)
2217 {
2218 struct skb_shared_info *info = skb_shinfo(skb);
2219 unsigned int cur_frag, entry;
2220 struct TxDesc *txd;
2221
2222 entry = tp->cur_tx;
2223 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2224 skb_frag_t *frag = info->frags + cur_frag;
2225 dma_addr_t mapping;
2226 u32 status, len;
2227 void *addr;
2228
2229 entry = (entry + 1) % NUM_TX_DESC;
2230
2231 txd = tp->TxDescArray + entry;
2232 len = frag->size;
2233 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2234 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2235
2236 /* anti gcc 2.95.3 bugware (sic) */
2237 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2238
2239 txd->opts1 = cpu_to_le32(status);
2240 txd->addr = cpu_to_le64(mapping);
2241
2242 tp->tx_skb[entry].len = len;
2243 }
2244
2245 if (cur_frag) {
2246 tp->tx_skb[entry].skb = skb;
2247 txd->opts1 |= cpu_to_le32(LastFrag);
2248 }
2249
2250 return cur_frag;
2251 }
2252
2253 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2254 {
2255 if (dev->features & NETIF_F_TSO) {
2256 u32 mss = skb_shinfo(skb)->gso_size;
2257
2258 if (mss)
2259 return LargeSend | ((mss & MSSMask) << MSSShift);
2260 }
2261 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2262 const struct iphdr *ip = skb->nh.iph;
2263
2264 if (ip->protocol == IPPROTO_TCP)
2265 return IPCS | TCPCS;
2266 else if (ip->protocol == IPPROTO_UDP)
2267 return IPCS | UDPCS;
2268 WARN_ON(1); /* we need a WARN() */
2269 }
2270 return 0;
2271 }
2272
2273 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2274 {
2275 struct rtl8169_private *tp = netdev_priv(dev);
2276 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2277 struct TxDesc *txd = tp->TxDescArray + entry;
2278 void __iomem *ioaddr = tp->mmio_addr;
2279 dma_addr_t mapping;
2280 u32 status, len;
2281 u32 opts1;
2282 int ret = NETDEV_TX_OK;
2283
2284 #ifdef CONFIG_LEDMAN
2285 ledman_cmd(LEDMAN_CMD_SET,
2286 (dev->name[3] == '0') ? LEDMAN_LAN1_TX :
2287 (dev->name[3] == '1') ? LEDMAN_LAN2_TX :
2288 LEDMAN_LAN3_TX);
2289 #endif
2290
2291 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2292 if (netif_msg_drv(tp)) {
2293 printk(KERN_ERR
2294 "%s: BUG! Tx Ring full when queue awake!\n",
2295 dev->name);
2296 }
2297 goto err_stop;
2298 }
2299
2300 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2301 goto err_stop;
2302
2303 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2304
2305 frags = rtl8169_xmit_frags(tp, skb, opts1);
2306 if (frags) {
2307 len = skb_headlen(skb);
2308 opts1 |= FirstFrag;
2309 } else {
2310 len = skb->len;
2311
2312 if (unlikely(len < ETH_ZLEN)) {
2313 if (skb_padto(skb, ETH_ZLEN))
2314 goto err_update_stats;
2315 len = ETH_ZLEN;
2316 }
2317
2318 opts1 |= FirstFrag | LastFrag;
2319 tp->tx_skb[entry].skb = skb;
2320 }
2321
2322 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2323
2324 tp->tx_skb[entry].len = len;
2325 txd->addr = cpu_to_le64(mapping);
2326 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2327
2328 wmb();
2329
2330 /* anti gcc 2.95.3 bugware (sic) */
2331 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2332 txd->opts1 = cpu_to_le32(status);
2333
2334 dev->trans_start = jiffies;
2335
2336 tp->cur_tx += frags + 1;
2337
2338 smp_wmb();
2339
2340 RTL_W8(TxPoll, 0x40); /* set polling bit */
2341
2342 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2343 netif_stop_queue(dev);
2344 smp_rmb();
2345 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2346 netif_wake_queue(dev);
2347 }
2348
2349 out:
2350 return ret;
2351
2352 err_stop:
2353 netif_stop_queue(dev);
2354 ret = NETDEV_TX_BUSY;
2355 err_update_stats:
2356 tp->stats.tx_dropped++;
2357 goto out;
2358 }
2359
2360 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2361 {
2362 struct rtl8169_private *tp = netdev_priv(dev);
2363 struct pci_dev *pdev = tp->pci_dev;
2364 void __iomem *ioaddr = tp->mmio_addr;
2365 u16 pci_status, pci_cmd;
2366
2367 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2368 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2369
2370 if (netif_msg_intr(tp)) {
2371 printk(KERN_ERR
2372 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2373 dev->name, pci_cmd, pci_status);
2374 }
2375
2376 /*
2377 * The recovery sequence below admits a very elaborated explanation:
2378 * - it seems to work;
2379 * - I did not see what else could be done.
2380 *
2381 * Feel free to adjust to your needs.
2382 */
2383 pci_write_config_word(pdev, PCI_COMMAND,
2384 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2385
2386 pci_write_config_word(pdev, PCI_STATUS,
2387 pci_status & (PCI_STATUS_DETECTED_PARITY |
2388 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2389 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2390
2391 /* The infamous DAC f*ckup only happens at boot time */
2392 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2393 if (netif_msg_intr(tp))
2394 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2395 tp->cp_cmd &= ~PCIDAC;
2396 RTL_W16(CPlusCmd, tp->cp_cmd);
2397 dev->features &= ~NETIF_F_HIGHDMA;
2398 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2399 }
2400
2401 rtl8169_hw_reset(ioaddr);
2402 }
2403
2404 static void
2405 rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2406 void __iomem *ioaddr)
2407 {
2408 unsigned int dirty_tx, tx_left;
2409
2410 assert(dev != NULL);
2411 assert(tp != NULL);
2412 assert(ioaddr != NULL);
2413
2414 dirty_tx = tp->dirty_tx;
2415 smp_rmb();
2416 tx_left = tp->cur_tx - dirty_tx;
2417
2418 while (tx_left > 0) {
2419 unsigned int entry = dirty_tx % NUM_TX_DESC;
2420 struct ring_info *tx_skb = tp->tx_skb + entry;
2421 u32 len = tx_skb->len;
2422 u32 status;
2423
2424 rmb();
2425 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2426 if (status & DescOwn)
2427 break;
2428
2429 tp->stats.tx_bytes += len;
2430 tp->stats.tx_packets++;
2431
2432 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2433
2434 if (status & LastFrag) {
2435 dev_kfree_skb_irq(tx_skb->skb);
2436 tx_skb->skb = NULL;
2437 }
2438 dirty_tx++;
2439 tx_left--;
2440 }
2441
2442 if (tp->dirty_tx != dirty_tx) {
2443 tp->dirty_tx = dirty_tx;
2444 smp_wmb();
2445 if (netif_queue_stopped(dev) &&
2446 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2447 netif_wake_queue(dev);
2448 }
2449 }
2450 }
2451
2452 static inline int rtl8169_fragmented_frame(u32 status)
2453 {
2454 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2455 }
2456
2457 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2458 {
2459 u32 opts1 = le32_to_cpu(desc->opts1);
2460 u32 status = opts1 & RxProtoMask;
2461
2462 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2463 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2464 ((status == RxProtoIP) && !(opts1 & IPFail)))
2465 skb->ip_summed = CHECKSUM_UNNECESSARY;
2466 else
2467 skb->ip_summed = CHECKSUM_NONE;
2468 }
2469
2470 static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2471 struct RxDesc *desc, int rx_buf_sz,
2472 unsigned int align)
2473 {
2474 int ret = -1;
2475
2476 if (pkt_size < rx_copybreak) {
2477 struct sk_buff *skb;
2478
2479 skb = dev_alloc_skb(pkt_size + align);
2480 if (skb) {
2481 skb_reserve(skb, align);
2482 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
2483 *sk_buff = skb;
2484 rtl8169_mark_to_asic(desc, rx_buf_sz);
2485 ret = 0;
2486 }
2487 }
2488 return ret;
2489 }
2490
2491 static int
2492 rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2493 void __iomem *ioaddr)
2494 {
2495 unsigned int cur_rx, rx_left;
2496 unsigned int delta, count;
2497
2498 assert(dev != NULL);
2499 assert(tp != NULL);
2500 assert(ioaddr != NULL);
2501
2502 cur_rx = tp->cur_rx;
2503 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2504 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2505
2506 #ifdef CONFIG_LEDMAN
2507 ledman_cmd(LEDMAN_CMD_SET,
2508 (dev->name[3] == '0') ? LEDMAN_LAN1_RX :
2509 (dev->name[3] == '1') ? LEDMAN_LAN2_RX :
2510 LEDMAN_LAN3_RX);
2511 #endif
2512
2513 for (; rx_left > 0; rx_left--, cur_rx++) {
2514 unsigned int entry = cur_rx % NUM_RX_DESC;
2515 struct RxDesc *desc = tp->RxDescArray + entry;
2516 u32 status;
2517
2518 rmb();
2519 status = le32_to_cpu(desc->opts1);
2520
2521 if (status & DescOwn)
2522 break;
2523 if (unlikely(status & RxRES)) {
2524 if (netif_msg_rx_err(tp)) {
2525 printk(KERN_INFO
2526 "%s: Rx ERROR. status = %08x\n",
2527 dev->name, status);
2528 }
2529 tp->stats.rx_errors++;
2530 if (status & (RxRWT | RxRUNT))
2531 tp->stats.rx_length_errors++;
2532 if (status & RxCRC)
2533 tp->stats.rx_crc_errors++;
2534 if (status & RxFOVF) {
2535 rtl8169_schedule_work(dev, rtl8169_reset_task);
2536 tp->stats.rx_fifo_errors++;
2537 }
2538 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2539 } else {
2540 struct sk_buff *skb = tp->Rx_skbuff[entry];
2541 int pkt_size = (status & 0x00001FFF) - 4;
2542 void (*pci_action)(struct pci_dev *, dma_addr_t,
2543 size_t, int) = pci_dma_sync_single_for_device;
2544
2545 /*
2546 * The driver does not support incoming fragmented
2547 * frames. They are seen as a symptom of over-mtu
2548 * sized frames.
2549 */
2550 if (unlikely(rtl8169_fragmented_frame(status))) {
2551 tp->stats.rx_dropped++;
2552 tp->stats.rx_length_errors++;
2553 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2554 continue;
2555 }
2556
2557 rtl8169_rx_csum(skb, desc);
2558
2559 pci_dma_sync_single_for_cpu(tp->pci_dev,
2560 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2561 PCI_DMA_FROMDEVICE);
2562
2563 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2564 tp->rx_buf_sz, tp->align)) {
2565 pci_action = pci_unmap_single;
2566 tp->Rx_skbuff[entry] = NULL;
2567 }
2568
2569 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2570 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2571
2572 skb->dev = dev;
2573 skb_put(skb, pkt_size);
2574 skb->protocol = eth_type_trans(skb, dev);
2575
2576 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2577 rtl8169_rx_skb(skb);
2578
2579 dev->last_rx = jiffies;
2580 tp->stats.rx_bytes += pkt_size;
2581 tp->stats.rx_packets++;
2582 }
2583 }
2584
2585 count = cur_rx - tp->cur_rx;
2586 tp->cur_rx = cur_rx;
2587
2588 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2589 if (!delta && count && netif_msg_intr(tp))
2590 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2591 tp->dirty_rx += delta;
2592
2593 /*
2594 * FIXME: until there is periodic timer to try and refill the ring,
2595 * a temporary shortage may definitely kill the Rx process.
2596 * - disable the asic to try and avoid an overflow and kick it again
2597 * after refill ?
2598 * - how do others driver handle this condition (Uh oh...).
2599 */
2600 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2601 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2602
2603 return count;
2604 }
2605
2606 /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2607 static irqreturn_t
2608 rtl8169_interrupt(int irq, void *dev_instance)
2609 {
2610 struct net_device *dev = (struct net_device *) dev_instance;
2611 struct rtl8169_private *tp = netdev_priv(dev);
2612 int boguscnt = max_interrupt_work;
2613 void __iomem *ioaddr = tp->mmio_addr;
2614 int status;
2615 int handled = 0;
2616
2617 do {
2618 status = RTL_R16(IntrStatus);
2619
2620 /* hotplug/major error/no more work/shared irq */
2621 if ((status == 0xFFFF) || !status)
2622 break;
2623
2624 handled = 1;
2625
2626 if (unlikely(!netif_running(dev))) {
2627 rtl8169_asic_down(ioaddr);
2628 goto out;
2629 }
2630
2631 status &= tp->intr_mask;
2632 RTL_W16(IntrStatus,
2633 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2634
2635 if (!(status & rtl8169_intr_mask))
2636 break;
2637
2638 if (unlikely(status & SYSErr)) {
2639 rtl8169_pcierr_interrupt(dev);
2640 break;
2641 }
2642
2643 if (status & LinkChg)
2644 rtl8169_check_link_status(dev, tp, ioaddr);
2645
2646 #ifdef CONFIG_R8169_NAPI
2647 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2648 tp->intr_mask = ~rtl8169_napi_event;
2649
2650 if (likely(netif_rx_schedule_prep(dev)))
2651 __netif_rx_schedule(dev);
2652 else if (netif_msg_intr(tp)) {
2653 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2654 dev->name, status);
2655 }
2656 break;
2657 #else
2658 /* Rx interrupt */
2659 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2660 rtl8169_rx_interrupt(dev, tp, ioaddr);
2661 }
2662 /* Tx interrupt */
2663 if (status & (TxOK | TxErr))
2664 rtl8169_tx_interrupt(dev, tp, ioaddr);
2665 #endif
2666
2667 boguscnt--;
2668 } while (boguscnt > 0);
2669
2670 if (boguscnt <= 0) {
2671 if (netif_msg_intr(tp) && net_ratelimit() ) {
2672 printk(KERN_WARNING
2673 "%s: Too much work at interrupt!\n", dev->name);
2674 }
2675 /* Clear all interrupt sources. */
2676 RTL_W16(IntrStatus, 0xffff);
2677 }
2678 out:
2679 return IRQ_RETVAL(handled);
2680 }
2681
2682 #ifdef CONFIG_R8169_NAPI
2683 static int rtl8169_poll(struct net_device *dev, int *budget)
2684 {
2685 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2686 struct rtl8169_private *tp = netdev_priv(dev);
2687 void __iomem *ioaddr = tp->mmio_addr;
2688
2689 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2690 rtl8169_tx_interrupt(dev, tp, ioaddr);
2691
2692 *budget -= work_done;
2693 dev->quota -= work_done;
2694
2695 if (work_done < work_to_do) {
2696 netif_rx_complete(dev);
2697 tp->intr_mask = 0xffff;
2698 /*
2699 * 20040426: the barrier is not strictly required but the
2700 * behavior of the irq handler could be less predictable
2701 * without it. Btw, the lack of flush for the posted pci
2702 * write is safe - FR
2703 */
2704 smp_wmb();
2705 RTL_W16(IntrMask, rtl8169_intr_mask);
2706 }
2707
2708 return (work_done >= work_to_do);
2709 }
2710 #endif
2711
2712 static void rtl8169_down(struct net_device *dev)
2713 {
2714 struct rtl8169_private *tp = netdev_priv(dev);
2715 void __iomem *ioaddr = tp->mmio_addr;
2716 unsigned int poll_locked = 0;
2717 unsigned int intrmask;
2718
2719 rtl8169_delete_timer(dev);
2720
2721 netif_stop_queue(dev);
2722
2723 flush_scheduled_work();
2724
2725 core_down:
2726 spin_lock_irq(&tp->lock);
2727
2728 rtl8169_asic_down(ioaddr);
2729
2730 /* Update the error counts. */
2731 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2732 RTL_W32(RxMissed, 0);
2733
2734 spin_unlock_irq(&tp->lock);
2735
2736 synchronize_irq(dev->irq);
2737
2738 if (!poll_locked) {
2739 netif_poll_disable(dev);
2740 poll_locked++;
2741 }
2742
2743 /* Give a racing hard_start_xmit a few cycles to complete. */
2744 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2745
2746 /*
2747 * And now for the 50k$ question: are IRQ disabled or not ?
2748 *
2749 * Two paths lead here:
2750 * 1) dev->close
2751 * -> netif_running() is available to sync the current code and the
2752 * IRQ handler. See rtl8169_interrupt for details.
2753 * 2) dev->change_mtu
2754 * -> rtl8169_poll can not be issued again and re-enable the
2755 * interruptions. Let's simply issue the IRQ down sequence again.
2756 *
2757 * No loop if hotpluged or major error (0xffff).
2758 */
2759 intrmask = RTL_R16(IntrMask);
2760 if (intrmask && (intrmask != 0xffff))
2761 goto core_down;
2762
2763 rtl8169_tx_clear(tp);
2764
2765 rtl8169_rx_clear(tp);
2766 }
2767
2768 static int rtl8169_close(struct net_device *dev)
2769 {
2770 struct rtl8169_private *tp = netdev_priv(dev);
2771 struct pci_dev *pdev = tp->pci_dev;
2772
2773 rtl8169_down(dev);
2774
2775 free_irq(dev->irq, dev);
2776
2777 netif_poll_enable(dev);
2778
2779 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2780 tp->RxPhyAddr);
2781 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2782 tp->TxPhyAddr);
2783 tp->TxDescArray = NULL;
2784 tp->RxDescArray = NULL;
2785
2786 return 0;
2787 }
2788
2789 static void
2790 rtl8169_set_rx_mode(struct net_device *dev)
2791 {
2792 struct rtl8169_private *tp = netdev_priv(dev);
2793 void __iomem *ioaddr = tp->mmio_addr;
2794 unsigned long flags;
2795 u32 mc_filter[2]; /* Multicast hash filter */
2796 int i, rx_mode;
2797 u32 tmp = 0;
2798
2799 if (dev->flags & IFF_PROMISC) {
2800 /* Unconditionally log net taps. */
2801 if (netif_msg_link(tp)) {
2802 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2803 dev->name);
2804 }
2805 rx_mode =
2806 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2807 AcceptAllPhys;
2808 mc_filter[1] = mc_filter[0] = 0xffffffff;
2809 } else if ((dev->mc_count > multicast_filter_limit)
2810 || (dev->flags & IFF_ALLMULTI)) {
2811 /* Too many to filter perfectly -- accept all multicasts. */
2812 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2813 mc_filter[1] = mc_filter[0] = 0xffffffff;
2814 } else {
2815 struct dev_mc_list *mclist;
2816 rx_mode = AcceptBroadcast | AcceptMyPhys;
2817 mc_filter[1] = mc_filter[0] = 0;
2818 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2819 i++, mclist = mclist->next) {
2820 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2821 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2822 rx_mode |= AcceptMulticast;
2823 }
2824 }
2825
2826 spin_lock_irqsave(&tp->lock, flags);
2827
2828 tmp = rtl8169_rx_config | rx_mode |
2829 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2830
2831 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2832 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2833 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2834 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2835 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2836 mc_filter[0] = 0xffffffff;
2837 mc_filter[1] = 0xffffffff;
2838 }
2839
2840 RTL_W32(RxConfig, tmp);
2841 RTL_W32(MAR0 + 0, mc_filter[0]);
2842 RTL_W32(MAR0 + 4, mc_filter[1]);
2843
2844 spin_unlock_irqrestore(&tp->lock, flags);
2845 }
2846
2847 /**
2848 * rtl8169_get_stats - Get rtl8169 read/write statistics
2849 * @dev: The Ethernet Device to get statistics for
2850 *
2851 * Get TX/RX statistics for rtl8169
2852 */
2853 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2854 {
2855 struct rtl8169_private *tp = netdev_priv(dev);
2856 void __iomem *ioaddr = tp->mmio_addr;
2857 unsigned long flags;
2858
2859 if (netif_running(dev)) {
2860 spin_lock_irqsave(&tp->lock, flags);
2861 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2862 RTL_W32(RxMissed, 0);
2863 spin_unlock_irqrestore(&tp->lock, flags);
2864 }
2865
2866 return &tp->stats;
2867 }
2868
2869 #ifdef CONFIG_PM
2870
2871 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2872 {
2873 struct net_device *dev = pci_get_drvdata(pdev);
2874 struct rtl8169_private *tp = netdev_priv(dev);
2875 void __iomem *ioaddr = tp->mmio_addr;
2876
2877 if (!netif_running(dev))
2878 goto out;
2879
2880 netif_device_detach(dev);
2881 netif_stop_queue(dev);
2882
2883 spin_lock_irq(&tp->lock);
2884
2885 rtl8169_asic_down(ioaddr);
2886
2887 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2888 RTL_W32(RxMissed, 0);
2889
2890 spin_unlock_irq(&tp->lock);
2891
2892 pci_save_state(pdev);
2893 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
2894 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2895 out:
2896 return 0;
2897 }
2898
2899 static int rtl8169_resume(struct pci_dev *pdev)
2900 {
2901 struct net_device *dev = pci_get_drvdata(pdev);
2902
2903 if (!netif_running(dev))
2904 goto out;
2905
2906 netif_device_attach(dev);
2907
2908 pci_set_power_state(pdev, PCI_D0);
2909 pci_restore_state(pdev);
2910 pci_enable_wake(pdev, PCI_D0, 0);
2911
2912 rtl8169_schedule_work(dev, rtl8169_reset_task);
2913 out:
2914 return 0;
2915 }
2916
2917 #endif /* CONFIG_PM */
2918
2919 static struct pci_driver rtl8169_pci_driver = {
2920 .name = MODULENAME,
2921 .id_table = rtl8169_pci_tbl,
2922 .probe = rtl8169_init_one,
2923 .remove = __devexit_p(rtl8169_remove_one),
2924 #ifdef CONFIG_PM
2925 .suspend = rtl8169_suspend,
2926 .resume = rtl8169_resume,
2927 #endif
2928 };
2929
2930 static int __init
2931 rtl8169_init_module(void)
2932 {
2933 return pci_register_driver(&rtl8169_pci_driver);
2934 }
2935
2936 static void __exit
2937 rtl8169_cleanup_module(void)
2938 {
2939 pci_unregister_driver(&rtl8169_pci_driver);
2940 }
2941
2942 module_init(rtl8169_init_module);
2943 module_exit(rtl8169_cleanup_module);
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz