| blob | bdd1ec7199a0bb83df3f1266fa3b9a3b64fb3f7d |
1 /*
2 * linux/arch/armnommu/mm/arm740.S: MPU functions for ARM740
3 *
4 * Copyright (C) 1997-2000 Russell King
5 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
6 * Rob Scott (rscott@mtrob.fdns.net)
7 * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
8 * Copyright (C) 2004 Hyok S. Choi (hyok.choi@samsung.com)
9 */
11 #include <linux/linkage.h>
12 #include <linux/init.h>
13 #include <asm/assembler.h>
14 #include <asm/pgtable.h>
15 #include <asm/procinfo.h>
16 #include <asm/hardware.h>
17 #include <asm/page.h>
18 #include <asm/ptrace.h>
19 #include "proc-macros.S"
22 /*
23 * cpu_arm740_data_abort()
24 *
25 * obtain information about current aborted instruction
26 *
27 * r0 = address of aborted instruction
28 *
29 * Returns:
30 * r0 = address of abort
31 * r1 != 0 if writing
32 * r3 = FSR
33 */
34 .align 5
35 Ldata_ldmstm:
36 tst r4, #1 << 21 @ check writeback bit
37 beq Ldata_simple
38 mov r7, #0x11
39 orr r7, r7, r7, lsl #8
40 and r0, r4, r7
41 and r2, r4, r7, lsl #1
42 add r0, r0, r2, lsr #1
43 and r2, r4, r7, lsl #2
44 add r0, r0, r2, lsr #2
45 and r2, r4, r7, lsl #3
46 add r0, r0, r2, lsr #3
47 add r0, r0, r0, lsr #8
48 add r0, r0, r0, lsr #4
49 and r7, r0, #15 @ r7 = no. of registers to transfer.
50 and r5, r4, #15 << 16 @ Get Rn
51 ldr r0, [sp, r5, lsr #14] @ Get register
52 tst r4, #1 << 23 @ U bit
53 subne r7, r0, r7, lsl #2
54 addeq r7, r0, r7, lsl #2 @ Do correction (signed)
55 Ldata_saver7:
56 str r7, [sp, r5, lsr #14] @ Put register
57 Ldata_simple:
58 mrc p15, 0, r0, c6, c0, 0 @ get FAR
59 mrc p15, 0, r3, c5, c0, 0 @ get FSR
60 and r3, r3, #255
61 mov pc, lr
63 ENTRY(cpu_arm740_data_abort)
64 ldr r4, [r0] @ read instruction causing problem
65 tst r4, r4, lsr #21 @ C = bit 20
66 sbc r1, r1, r1 @ r1 = C - 1
67 and r2, r4, #15 << 24
68 add pc, pc, r2, lsr #22 @ Now branch to the relevent processing routine
69 movs pc, lr
71 b Ldata_lateldrhpost @ ldrh rd, [rn], #m/rm
72 b Ldata_lateldrhpre @ ldrh rd, [rn, #m/rm]
73 b Ldata_unknown
74 b Ldata_unknown
75 b Ldata_lateldrpostconst @ ldr rd, [rn], #m
76 b Ldata_lateldrpreconst @ ldr rd, [rn, #m]
77 b Ldata_lateldrpostreg @ ldr rd, [rn], rm
78 b Ldata_lateldrprereg @ ldr rd, [rn, rm]
79 b Ldata_ldmstm @ ldm*a rn, <rlist>
80 b Ldata_ldmstm @ ldm*b rn, <rlist>
81 b Ldata_unknown
82 b Ldata_unknown
83 b Ldata_simple @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
84 b Ldata_simple @ ldc rd, [rn, #m]
85 b Ldata_unknown
87 Ldata_unknown: @ Part of jumptable
88 mov r0, r2
89 mov r1, r4
90 mov r2, r3
91 bl baddataabort
92 b ret_from_exception
94 Ldata_lateldrhpre:
95 tst r4, #1 << 21 @ check writeback bit
96 beq Ldata_simple
97 Ldata_lateldrhpost:
98 and r5, r4, #0x00f @ get Rm / low nibble of immediate value
99 tst r4, #1 << 22 @ if (immediate offset)
100 andne r2, r4, #0xf00 @ { immediate high nibble
101 orrne r2, r5, r2, lsr #4 @ combine nibbles } else
102 ldreq r2, [sp, r5, lsl #2] @ { load Rm value }
103 and r5, r4, #15 << 16 @ get Rn
104 ldr r0, [sp, r5, lsr #14] @ load Rn value
105 tst r4, #1 << 23 @ U bit
106 subne r7, r0, r2
107 addeq r7, r0, r2
108 b Ldata_saver7
110 Ldata_lateldrpreconst:
111 tst r4, #1 << 21 @ check writeback bit
112 beq Ldata_simple
113 Ldata_lateldrpostconst:
114 movs r2, r4, lsl #20 @ Get offset
115 beq Ldata_simple
116 and r5, r4, #15 << 16 @ Get Rn
117 ldr r0, [sp, r5, lsr #14]
118 tst r4, #1 << 23 @ U bit
119 subne r7, r0, r2, lsr #20
120 addeq r7, r0, r2, lsr #20
121 b Ldata_saver7
123 Ldata_lateldrprereg:
124 tst r4, #1 << 21 @ check writeback bit
125 beq Ldata_simple
126 Ldata_lateldrpostreg:
127 and r5, r4, #15
128 ldr r2, [sp, r5, lsl #2] @ Get Rm
129 mov r3, r4, lsr #7
130 ands r3, r3, #31
131 and r6, r4, #0x70
132 orreq r6, r6, #8
133 add pc, pc, r6
134 mov r0, r0
136 mov r2, r2, lsl r3 @ 0: LSL #!0
137 b 1f
138 b 1f @ 1: LSL #0
139 mov r0, r0
140 b 1f @ 2: MUL?
141 mov r0, r0
142 b 1f @ 3: MUL?
143 mov r0, r0
144 mov r2, r2, lsr r3 @ 4: LSR #!0
145 b 1f
146 mov r2, r2, lsr #32 @ 5: LSR #32
147 b 1f
148 b 1f @ 6: MUL?
149 mov r0, r0
150 b 1f @ 7: MUL?
151 mov r0, r0
152 mov r2, r2, asr r3 @ 8: ASR #!0
153 b 1f
154 mov r2, r2, asr #32 @ 9: ASR #32
155 b 1f
156 b 1f @ A: MUL?
157 mov r0, r0
158 b 1f @ B: MUL?
159 mov r0, r0
160 mov r2, r2, ror r3 @ C: ROR #!0
161 b 1f
162 mov r2, r2, rrx @ D: RRX
163 b 1f
164 mov r0, r0 @ E: MUL?
165 mov r0, r0
166 mov r0, r0 @ F: MUL?
169 1: and r5, r4, #15 << 16 @ Get Rn
170 ldr r0, [sp, r5, lsr #14]
171 tst r4, #1 << 23 @ U bit
172 subne r7, r0, r2
173 addeq r7, r0, r2
174 b Ldata_saver7
177 /*
178 * cpu_arm740_check_bugs()
179 */
180 ENTRY(cpu_arm740_check_bugs)
181 mrs ip, cpsr
182 bic ip, ip, #PSR_F_BIT
183 msr cpsr, ip
184 mov pc, lr
186 /*
187 * cpu_arm740_proc_init()
188 */
189 ENTRY(cpu_arm740_proc_init)
190 mov pc, lr
192 /*
193 * cpu_arm740_proc_fin()
194 */
195 ENTRY(cpu_arm740_proc_fin)
196 stmfd sp!, {lr}
197 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
198 msr cpsr_c, ip
199 mrc p15, 0, r0, c1, c0, 0
200 bic r0, r0, #0x1000 @ ...i............
201 bic r0, r0, #0x000e @ ............wca.
202 mcr p15, 0, r0, c1, c0, 0 @ disable caches
203 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
204 ldmfd sp!, {pc}
206 /*
207 * cpu_arm740_reset(loc)
208 * Params : r0 = address to jump to
209 * Notes : This sets up everything for a reset
210 */
211 ENTRY(cpu_arm740_reset)
212 mov ip, #0
213 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
214 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
215 bic ip, ip, #0x000e @ ............wcam
216 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
217 mov pc, r0
219 /*
220 * idle mode processing
221 */
222 ENTRY(cpu_arm740_do_idle)
223 mov pc, lr
225 /*
226 * *FIXME*
227 */
228 ENTRY(cpu_arm740_dcache_clean_area)
229 mov r0, #0
230 mcr p15, 0, r0, c7, c7, 0 @ flush cache
231 mov pc, lr
233 /*
234 * Function: arm740_switch_mm(unsigned long pgd_phys)
235 * Params : pgd_phys Physical address of page table
236 * Purpose : Perform a task switch,
237 */
238 ENTRY(cpu_arm740_switch_mm)
239 mov pc, lr
242 /* .section ".text.init", #alloc, #execinstr */
243 __INIT
245 __arm740_setup:
246 mov r0, #0
247 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
249 mov r0, #0x0 @disable region 3-7
250 mcr p15, 0, r0, c6, c3
251 mcr p15, 0, r0, c6, c4
252 mcr p15, 0, r0, c6, c5
253 mcr p15, 0, r0, c6, c6
254 mcr p15, 0, r0, c6, c7
256 mov r0, #0x0000003F @ (base = 0, size = 4GB, non cacheable, no write buffer)
257 mcr p15, 0, r0, c6, c0 @ enable region 0, default
258 mov r0, #0x00000037 @ (base = 0, size = 256MB, cacheable, write buffered)
259 mcr p15, 0, r0, c6, c1 @enable region 1, RAM
260 mov r0, #0x20000000
261 add r0, r0, #0x37 @ (base = 512MB, size = 256MB, cacheable, write buffered)
262 mcr p15, 0, r0, c6, c2 @enable region 2, ROM/Flash
264 mov r0, #0x06
265 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
266 mov r0, #0x02
267 mcr p15, 0, r0, c3, c0 @ Region 1 write buferred
269 mov r0, #0xff00
270 add r0, r0, #0x00ff
271 mcr p15, 0, r0, c5, c0 @ all read/write access
273 mrc p15, 0, r0, c1, c0 @ get control register
274 orr r0, r0, #0x00030000 @ Split cache mode
275 orr r0, r0, #0x0000000d @ MPU, Cache, Write Buffer on
277 mov pc, lr @ __ret (head-armv.S)
279 .size __arm740_setup, . - __arm740_setup
281 __INITDATA
283 /*
284 * Purpose : Function pointers used to access above functions - all calls
285 * come through these
286 */
287 .type arm740_processor_functions, #object
288 ENTRY(arm740_processor_functions)
289 .word cpu_arm740_data_abort
290 .word cpu_arm740_proc_init
291 .word cpu_arm740_proc_fin
292 .word cpu_arm740_reset
293 .word cpu_arm740_do_idle
295 .word cpu_arm740_dcache_clean_area
296 .word cpu_arm740_switch_mm
297 .size arm740_processor_functions, . - arm740_processor_functions
299 .section ".rodata"
300 .type cpu_arch_name, #object
301 cpu_arch_name:
302 .asciz "armv4"
303 .size cpu_arch_name, . - cpu_arch_name
305 .type cpu_elf_name, #object
306 cpu_elf_name:
307 .asciz "v4"
308 .size cpu_elf_name, . - cpu_elf_name
310 .type cpu_arm740_name, #object
311 cpu_arm740_name:
312 .ascii "ARM740T"
313 .size cpu_arm740_name, . - cpu_arm740_name
315 .align
318 .section ".proc.info.init", #alloc, #execinstr
319 .type __arm740_proc_info,#object
320 __arm740_proc_info:
321 .long 0x41807400
322 .long 0xfffffff0
323 .long 0
324 .long 0
325 b __arm740_setup
326 .long cpu_arch_name
327 .long cpu_elf_name
328 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
329 .long cpu_arm740_name
330 .long arm740_processor_functions
331 .long 0
332 .long 0
333 .long v4_cache_fns @ cache model
334 .size __arm740_proc_info, . - __arm740_proc_info