include/jz4740.h

   1 /*
   2  * Copyright (c) 2009, yajin <yajin@vm-kernel.org>
   3  * Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
   4  *
   5  */
   6 #ifndef __JZ4740_H__
   7 #define __JZ4740_H__
   8
   9 #ifndef __ASSEMBLY__
  10
  11 #include <types.h>
  12
  13 #define REG8(addr)      *((volatile u8 *)(addr))
  14 #define REG16(addr)     *((volatile u16 *)(addr))
  15 #define REG32(addr)     *((volatile u32 *)(addr))
  16
  17 #else
  18
  19 #define REG8(addr)      (addr)
  20 #define REG16(addr)     (addr)
  21 #define REG32(addr)     (addr)
  22
  23 #endif                          /* !ASSEMBLY */
  24
  25 //----------------------------------------------------------------------
  26 // Boot ROM Specification
  27 //
  28
  29 /* NOR Boot config */
  30 #define JZ4740_NORBOOT_8BIT     0x00000000      /* 8-bit data bus flash */
  31 #define JZ4740_NORBOOT_16BIT    0x10101010      /* 16-bit data bus flash */
  32 #define JZ4740_NORBOOT_32BIT    0x20202020      /* 32-bit data bus flash */
  33
  34 /* NAND Boot config */
  35 #define JZ4740_NANDBOOT_B8R3    0xffffffff      /* 8-bit bus & 3 row cycles */
  36 #define JZ4740_NANDBOOT_B8R2    0xf0f0f0f0      /* 8-bit bus & 2 row cycles */
  37 #define JZ4740_NANDBOOT_B16R3   0x0f0f0f0f      /* 16-bit bus & 3 row cycles */
  38 #define JZ4740_NANDBOOT_B16R2   0x00000000      /* 16-bit bus & 2 row cycles */
  39
  40
  41 //----------------------------------------------------------------------
  42 // Register Definitions
  43 //
  44 #define CPM_BASE        0xB0000000
  45 #define INTC_BASE       0xB0001000
  46 #define TCU_BASE        0xB0002000
  47 #define WDT_BASE        0xB0002000
  48 #define RTC_BASE        0xB0003000
  49 #define GPIO_BASE       0xB0010000
  50 #define AIC_BASE        0xB0020000
  51 #define ICDC_BASE       0xB0020000
  52 #define MSC_BASE        0xB0021000
  53 #define UART0_BASE      0xB0030000
  54 #define I2C_BASE        0xB0042000
  55 #define SSI_BASE        0xB0043000
  56 #define SADC_BASE       0xB0070000
  57 #define EMC_BASE        0xB3010000
  58 #define DMAC_BASE       0xB3020000
  59 #define UHC_BASE        0xB3030000
  60 #define UDC_BASE        0xB3040000
  61 #define LCD_BASE        0xB3050000
  62 #define SLCD_BASE       0xB3050000
  63 #define CIM_BASE        0xB3060000
  64 #define ETH_BASE        0xB3100000
  65
  66
  67 /*************************************************************************
  68  * INTC (Interrupt Controller)
  69  *************************************************************************/
  70 #define INTC_ISR        (INTC_BASE + 0x00)
  71 #define INTC_IMR        (INTC_BASE + 0x04)
  72 #define INTC_IMSR       (INTC_BASE + 0x08)
  73 #define INTC_IMCR       (INTC_BASE + 0x0c)
  74 #define INTC_IPR        (INTC_BASE + 0x10)
  75
  76 #define REG_INTC_ISR    REG32(INTC_ISR)
  77 #define REG_INTC_IMR    REG32(INTC_IMR)
  78 #define REG_INTC_IMSR   REG32(INTC_IMSR)
  79 #define REG_INTC_IMCR   REG32(INTC_IMCR)
  80 #define REG_INTC_IPR    REG32(INTC_IPR)
  81
  82 // 1st-level interrupts
  83 #define IRQ_I2C         1
  84 #define IRQ_UHC         3
  85 #define IRQ_UART0       9
  86 #define IRQ_SADC        12
  87 #define IRQ_MSC         14
  88 #define IRQ_RTC         15
  89 #define IRQ_SSI         16
  90 #define IRQ_CIM         17
  91 #define IRQ_AIC         18
  92 #define IRQ_ETH         19
  93 #define IRQ_DMAC        20
  94 #define IRQ_TCU2        21
  95 #define IRQ_TCU1        22
  96 #define IRQ_TCU0        23
  97 #define IRQ_UDC         24
  98 #define IRQ_GPIO3       25
  99 #define IRQ_GPIO2       26
 100 #define IRQ_GPIO1       27
 101 #define IRQ_GPIO0       28
 102 #define IRQ_IPU         29
 103 #define IRQ_LCD         30
 104
 105 // 2nd-level interrupts
 106 #define IRQ_DMA_0       32      /* 32 to 37 for DMAC channel 0 to 5 */
 107 #define IRQ_GPIO_0      48      /* 48 to 175 for GPIO pin 0 to 127 */
 108
 109
 110 /*************************************************************************
 111  * RTC
 112  *************************************************************************/
 113 #define RTC_RCR         (RTC_BASE + 0x00)       /* RTC Control Register */
 114 #define RTC_RSR         (RTC_BASE + 0x04)       /* RTC Second Register */
 115 #define RTC_RSAR        (RTC_BASE + 0x08)       /* RTC Second Alarm Register */
 116 #define RTC_RGR         (RTC_BASE + 0x0c)       /* RTC Regulator Register */
 117
 118 #define RTC_HCR         (RTC_BASE + 0x20)       /* Hibernate Control Register */
 119 #define RTC_HWFCR       (RTC_BASE + 0x24)       /* Hibernate Wakeup Filter Counter Reg */
 120 #define RTC_HRCR        (RTC_BASE + 0x28)       /* Hibernate Reset Counter Register */
 121 #define RTC_HWCR        (RTC_BASE + 0x2c)       /* Hibernate Wakeup Control Register */
 122 #define RTC_HWRSR       (RTC_BASE + 0x30)       /* Hibernate Wakeup Status Register */
 123 #define RTC_HSPR        (RTC_BASE + 0x34)       /* Hibernate Scratch Pattern Register */
 124
 125 #define REG_RTC_RCR     REG32(RTC_RCR)
 126 #define REG_RTC_RSR     REG32(RTC_RSR)
 127 #define REG_RTC_RSAR    REG32(RTC_RSAR)
 128 #define REG_RTC_RGR     REG32(RTC_RGR)
 129 #define REG_RTC_HCR     REG32(RTC_HCR)
 130 #define REG_RTC_HWFCR   REG32(RTC_HWFCR)
 131 #define REG_RTC_HRCR    REG32(RTC_HRCR)
 132 #define REG_RTC_HWCR    REG32(RTC_HWCR)
 133 #define REG_RTC_HWRSR   REG32(RTC_HWRSR)
 134 #define REG_RTC_HSPR    REG32(RTC_HSPR)
 135
 136 /* RTC Control Register */
 137 #define RTC_RCR_WRDY    (1 << 7)        /* Write Ready Flag */
 138 #define RTC_RCR_HZ      (1 << 6)        /* 1Hz Flag */
 139 #define RTC_RCR_HZIE    (1 << 5)        /* 1Hz Interrupt Enable */
 140 #define RTC_RCR_AF      (1 << 4)        /* Alarm Flag */
 141 #define RTC_RCR_AIE     (1 << 3)        /* Alarm Interrupt Enable */
 142 #define RTC_RCR_AE      (1 << 2)        /* Alarm Enable */
 143 #define RTC_RCR_RTCE    (1 << 0)        /* RTC Enable */
 144
 145 /* RTC Regulator Register */
 146 #define RTC_RGR_LOCK            (1 << 31)       /* Lock Bit */
 147 #define RTC_RGR_ADJC_BIT        16
 148 #define RTC_RGR_ADJC_MASK       (0x3ff << RTC_RGR_ADJC_BIT)
 149 #define RTC_RGR_NC1HZ_BIT       0
 150 #define RTC_RGR_NC1HZ_MASK      (0xffff << RTC_RGR_NC1HZ_BIT)
 151
 152 /* Hibernate Control Register */
 153 #define RTC_HCR_PD              (1 << 0)        /* Power Down */
 154
 155 /* Hibernate Wakeup Filter Counter Register */
 156 #define RTC_HWFCR_BIT           5
 157 #define RTC_HWFCR_MASK          (0x7ff << RTC_HWFCR_BIT)
 158
 159 /* Hibernate Reset Counter Register */
 160 #define RTC_HRCR_BIT            5
 161 #define RTC_HRCR_MASK           (0x7f << RTC_HRCR_BIT)
 162
 163 /* Hibernate Wakeup Control Register */
 164 #define RTC_HWCR_EALM           (1 << 0)        /* RTC alarm wakeup enable */
 165
 166 /* Hibernate Wakeup Status Register */
 167 #define RTC_HWRSR_HR            (1 << 5)        /* Hibernate reset */
 168 #define RTC_HWRSR_PPR           (1 << 4)        /* PPR reset */
 169 #define RTC_HWRSR_PIN           (1 << 1)        /* Wakeup pin status bit */
 170 #define RTC_HWRSR_ALM           (1 << 0)        /* RTC alarm status bit */
 171
 172
 173 /*************************************************************************
 174  * CPM (Clock reset and Power control Management)
 175  *************************************************************************/
 176 #define CPM_CPCCR       (CPM_BASE+0x00)
 177 #define CPM_CPPCR       (CPM_BASE+0x10)
 178 #define CPM_I2SCDR      (CPM_BASE+0x60)
 179 #define CPM_LPCDR       (CPM_BASE+0x64)
 180 #define CPM_MSCCDR      (CPM_BASE+0x68)
 181 #define CPM_UHCCDR      (CPM_BASE+0x6C)
 182
 183 #define CPM_LCR         (CPM_BASE+0x04)
 184 #define CPM_CLKGR       (CPM_BASE+0x20)
 185 #define CPM_SCR         (CPM_BASE+0x24)
 186
 187 #define CPM_HCR         (CPM_BASE+0x30)
 188 #define CPM_HWFCR       (CPM_BASE+0x34)
 189 #define CPM_HRCR        (CPM_BASE+0x38)
 190 #define CPM_HWCR        (CPM_BASE+0x3c)
 191 #define CPM_HWSR        (CPM_BASE+0x40)
 192 #define CPM_HSPR        (CPM_BASE+0x44)
 193
 194 #define CPM_RSR         (CPM_BASE+0x08)
 195
 196
 197 #define REG_CPM_CPCCR   REG32(CPM_CPCCR)
 198 #define REG_CPM_CPPCR   REG32(CPM_CPPCR)
 199 #define REG_CPM_I2SCDR  REG32(CPM_I2SCDR)
 200 #define REG_CPM_LPCDR   REG32(CPM_LPCDR)
 201 #define REG_CPM_MSCCDR  REG32(CPM_MSCCDR)
 202 #define REG_CPM_UHCCDR  REG32(CPM_UHCCDR)
 203
 204 #define REG_CPM_LCR     REG32(CPM_LCR)
 205 #define REG_CPM_CLKGR   REG32(CPM_CLKGR)
 206 #define REG_CPM_SCR     REG32(CPM_SCR)
 207 #define REG_CPM_HCR     REG32(CPM_HCR)
 208 #define REG_CPM_HWFCR   REG32(CPM_HWFCR)
 209 #define REG_CPM_HRCR    REG32(CPM_HRCR)
 210 #define REG_CPM_HWCR    REG32(CPM_HWCR)
 211 #define REG_CPM_HWSR    REG32(CPM_HWSR)
 212 #define REG_CPM_HSPR    REG32(CPM_HSPR)
 213
 214 #define REG_CPM_RSR     REG32(CPM_RSR)
 215
 216
 217 /* Clock Control Register */
 218 #define CPM_CPCCR_I2CS          (1 << 31)
 219 #define CPM_CPCCR_CLKOEN        (1 << 30)
 220 #define CPM_CPCCR_UCS           (1 << 29)
 221 #define CPM_CPCCR_UDIV_BIT      23
 222 #define CPM_CPCCR_UDIV_MASK     (0x3f << CPM_CPCCR_UDIV_BIT)
 223 #define CPM_CPCCR_CE            (1 << 22)
 224 #define CPM_CPCCR_PCS           (1 << 21)
 225 #define CPM_CPCCR_LDIV_BIT      16
 226 #define CPM_CPCCR_LDIV_MASK     (0x1f << CPM_CPCCR_LDIV_BIT)
 227 #define CPM_CPCCR_MDIV_BIT      12
 228 #define CPM_CPCCR_MDIV_MASK     (0x0f << CPM_CPCCR_MDIV_BIT)
 229 #define CPM_CPCCR_PDIV_BIT      8
 230 #define CPM_CPCCR_PDIV_MASK     (0x0f << CPM_CPCCR_PDIV_BIT)
 231 #define CPM_CPCCR_HDIV_BIT      4
 232 #define CPM_CPCCR_HDIV_MASK     (0x0f << CPM_CPCCR_HDIV_BIT)
 233 #define CPM_CPCCR_CDIV_BIT      0
 234 #define CPM_CPCCR_CDIV_MASK     (0x0f << CPM_CPCCR_CDIV_BIT)
 235
 236 /* I2S Clock Divider Register */
 237 #define CPM_I2SCDR_I2SDIV_BIT   0
 238 #define CPM_I2SCDR_I2SDIV_MASK  (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
 239
 240 /* LCD Pixel Clock Divider Register */
 241 #define CPM_LPCDR_PIXDIV_BIT    0
 242 #define CPM_LPCDR_PIXDIV_MASK   (0x1ff << CPM_LPCDR_PIXDIV_BIT)
 243
 244 /* MSC Clock Divider Register */
 245 #define CPM_MSCCDR_MSCDIV_BIT   0
 246 #define CPM_MSCCDR_MSCDIV_MASK  (0x1f << CPM_MSCCDR_MSCDIV_BIT)
 247
 248 /* PLL Control Register */
 249 #define CPM_CPPCR_PLLM_BIT      23
 250 #define CPM_CPPCR_PLLM_MASK     (0x1ff << CPM_CPPCR_PLLM_BIT)
 251 #define CPM_CPPCR_PLLN_BIT      18
 252 #define CPM_CPPCR_PLLN_MASK     (0x1f << CPM_CPPCR_PLLN_BIT)
 253 #define CPM_CPPCR_PLLOD_BIT     16
 254 #define CPM_CPPCR_PLLOD_MASK    (0x03 << CPM_CPPCR_PLLOD_BIT)
 255 #define CPM_CPPCR_PLLS          (1 << 10)
 256 #define CPM_CPPCR_PLLBP         (1 << 9)
 257 #define CPM_CPPCR_PLLEN         (1 << 8)
 258 #define CPM_CPPCR_PLLST_BIT     0
 259 #define CPM_CPPCR_PLLST_MASK    (0xff << CPM_CPPCR_PLLST_BIT)
 260
 261 /* Low Power Control Register */
 262 #define CPM_LCR_DOZE_DUTY_BIT   3
 263 #define CPM_LCR_DOZE_DUTY_MASK  (0x1f << CPM_LCR_DOZE_DUTY_BIT)
 264 #define CPM_LCR_DOZE_ON         (1 << 2)
 265 #define CPM_LCR_LPM_BIT         0
 266 #define CPM_LCR_LPM_MASK        (0x3 << CPM_LCR_LPM_BIT)
 267 #define CPM_LCR_LPM_IDLE        (0x0 << CPM_LCR_LPM_BIT)
 268 #define CPM_LCR_LPM_SLEEP       (0x1 << CPM_LCR_LPM_BIT)
 269
 270 /* Clock Gate Register */
 271 #define CPM_CLKGR_UART1         (1 << 15)
 272 #define CPM_CLKGR_UHC           (1 << 14)
 273 #define CPM_CLKGR_IPU           (1 << 13)
 274 #define CPM_CLKGR_DMAC          (1 << 12)
 275 #define CPM_CLKGR_UDC           (1 << 11)
 276 #define CPM_CLKGR_LCD           (1 << 10)
 277 #define CPM_CLKGR_CIM           (1 << 9)
 278 #define CPM_CLKGR_SADC          (1 << 8)
 279 #define CPM_CLKGR_MSC           (1 << 7)
 280 #define CPM_CLKGR_AIC1          (1 << 6)
 281 #define CPM_CLKGR_AIC2          (1 << 5)
 282 #define CPM_CLKGR_SSI           (1 << 4)
 283 #define CPM_CLKGR_I2C           (1 << 3)
 284 #define CPM_CLKGR_RTC           (1 << 2)
 285 #define CPM_CLKGR_TCU           (1 << 1)
 286 #define CPM_CLKGR_UART0         (1 << 0)
 287
 288 /* Sleep Control Register */
 289 #define CPM_SCR_O1ST_BIT        8
 290 #define CPM_SCR_O1ST_MASK       (0xff << CPM_SCR_O1ST_BIT)
 291 #define CPM_SCR_USBPHY_ENABLE   (1 << 6)
 292 #define CPM_SCR_OSC_ENABLE      (1 << 4)
 293
 294 /* Hibernate Control Register */
 295 #define CPM_HCR_PD              (1 << 0)
 296
 297 /* Wakeup Filter Counter Register in Hibernate Mode */
 298 #define CPM_HWFCR_TIME_BIT      0
 299 #define CPM_HWFCR_TIME_MASK     (0x3ff << CPM_HWFCR_TIME_BIT)
 300
 301 /* Reset Counter Register in Hibernate Mode */
 302 #define CPM_HRCR_TIME_BIT       0
 303 #define CPM_HRCR_TIME_MASK      (0x7f << CPM_HRCR_TIME_BIT)
 304
 305 /* Wakeup Control Register in Hibernate Mode */
 306 #define CPM_HWCR_WLE_LOW        (0 << 2)
 307 #define CPM_HWCR_WLE_HIGH       (1 << 2)
 308 #define CPM_HWCR_PIN_WAKEUP     (1 << 1)
 309 #define CPM_HWCR_RTC_WAKEUP     (1 << 0)
 310
 311 /* Wakeup Status Register in Hibernate Mode */
 312 #define CPM_HWSR_WSR_PIN        (1 << 1)
 313 #define CPM_HWSR_WSR_RTC        (1 << 0)
 314
 315 /* Reset Status Register */
 316 #define CPM_RSR_HR              (1 << 2)
 317 #define CPM_RSR_WR              (1 << 1)
 318 #define CPM_RSR_PR              (1 << 0)
 319
 320
 321 /*************************************************************************
 322  * TCU (Timer Counter Unit)
 323  *************************************************************************/
 324 #define TCU_TSR         (TCU_BASE + 0x1C)       /* Timer Stop Register */
 325 #define TCU_TSSR        (TCU_BASE + 0x2C)       /* Timer Stop Set Register */
 326 #define TCU_TSCR        (TCU_BASE + 0x3C)       /* Timer Stop Clear Register */
 327 #define TCU_TER         (TCU_BASE + 0x10)       /* Timer Counter Enable Register */
 328 #define TCU_TESR        (TCU_BASE + 0x14)       /* Timer Counter Enable Set Register */
 329 #define TCU_TECR        (TCU_BASE + 0x18)       /* Timer Counter Enable Clear Register */
 330 #define TCU_TFR         (TCU_BASE + 0x20)       /* Timer Flag Register */
 331 #define TCU_TFSR        (TCU_BASE + 0x24)       /* Timer Flag Set Register */
 332 #define TCU_TFCR        (TCU_BASE + 0x28)       /* Timer Flag Clear Register */
 333 #define TCU_TMR         (TCU_BASE + 0x30)       /* Timer Mask Register */
 334 #define TCU_TMSR        (TCU_BASE + 0x34)       /* Timer Mask Set Register */
 335 #define TCU_TMCR        (TCU_BASE + 0x38)       /* Timer Mask Clear Register */
 336 #define TCU_TDFR0       (TCU_BASE + 0x40)       /* Timer Data Full Register */
 337 #define TCU_TDHR0       (TCU_BASE + 0x44)       /* Timer Data Half Register */
 338 #define TCU_TCNT0       (TCU_BASE + 0x48)       /* Timer Counter Register */
 339 #define TCU_TCSR0       (TCU_BASE + 0x4C)       /* Timer Control Register */
 340 #define TCU_TDFR1       (TCU_BASE + 0x50)
 341 #define TCU_TDHR1       (TCU_BASE + 0x54)
 342 #define TCU_TCNT1       (TCU_BASE + 0x58)
 343 #define TCU_TCSR1       (TCU_BASE + 0x5C)
 344 #define TCU_TDFR2       (TCU_BASE + 0x60)
 345 #define TCU_TDHR2       (TCU_BASE + 0x64)
 346 #define TCU_TCNT2       (TCU_BASE + 0x68)
 347 #define TCU_TCSR2       (TCU_BASE + 0x6C)
 348 #define TCU_TDFR3       (TCU_BASE + 0x70)
 349 #define TCU_TDHR3       (TCU_BASE + 0x74)
 350 #define TCU_TCNT3       (TCU_BASE + 0x78)
 351 #define TCU_TCSR3       (TCU_BASE + 0x7C)
 352 #define TCU_TDFR4       (TCU_BASE + 0x80)
 353 #define TCU_TDHR4       (TCU_BASE + 0x84)
 354 #define TCU_TCNT4       (TCU_BASE + 0x88)
 355 #define TCU_TCSR4       (TCU_BASE + 0x8C)
 356 #define TCU_TDFR5       (TCU_BASE + 0x90)
 357 #define TCU_TDHR5       (TCU_BASE + 0x94)
 358 #define TCU_TCNT5       (TCU_BASE + 0x98)
 359 #define TCU_TCSR5       (TCU_BASE + 0x9C)
 360
 361 #define REG_TCU_TSR     REG32(TCU_TSR)
 362 #define REG_TCU_TSSR    REG32(TCU_TSSR)
 363 #define REG_TCU_TSCR    REG32(TCU_TSCR)
 364 #define REG_TCU_TER     REG8(TCU_TER)
 365 #define REG_TCU_TESR    REG8(TCU_TESR)
 366 #define REG_TCU_TECR    REG8(TCU_TECR)
 367 #define REG_TCU_TFR     REG32(TCU_TFR)
 368 #define REG_TCU_TFSR    REG32(TCU_TFSR)
 369 #define REG_TCU_TFCR    REG32(TCU_TFCR)
 370 #define REG_TCU_TMR     REG32(TCU_TMR)
 371 #define REG_TCU_TMSR    REG32(TCU_TMSR)
 372 #define REG_TCU_TMCR    REG32(TCU_TMCR)
 373 #define REG_TCU_TDFR0   REG16(TCU_TDFR0)
 374 #define REG_TCU_TDHR0   REG16(TCU_TDHR0)
 375 #define REG_TCU_TCNT0   REG16(TCU_TCNT0)
 376 #define REG_TCU_TCSR0   REG16(TCU_TCSR0)
 377 #define REG_TCU_TDFR1   REG16(TCU_TDFR1)
 378 #define REG_TCU_TDHR1   REG16(TCU_TDHR1)
 379 #define REG_TCU_TCNT1   REG16(TCU_TCNT1)
 380 #define REG_TCU_TCSR1   REG16(TCU_TCSR1)
 381 #define REG_TCU_TDFR2   REG16(TCU_TDFR2)
 382 #define REG_TCU_TDHR2   REG16(TCU_TDHR2)
 383 #define REG_TCU_TCNT2   REG16(TCU_TCNT2)
 384 #define REG_TCU_TCSR2   REG16(TCU_TCSR2)
 385 #define REG_TCU_TDFR3   REG16(TCU_TDFR3)
 386 #define REG_TCU_TDHR3   REG16(TCU_TDHR3)
 387 #define REG_TCU_TCNT3   REG16(TCU_TCNT3)
 388 #define REG_TCU_TCSR3   REG16(TCU_TCSR3)
 389 #define REG_TCU_TDFR4   REG16(TCU_TDFR4)
 390 #define REG_TCU_TDHR4   REG16(TCU_TDHR4)
 391 #define REG_TCU_TCNT4   REG16(TCU_TCNT4)
 392 #define REG_TCU_TCSR4   REG16(TCU_TCSR4)
 393
 394 // n = 0,1,2,3,4,5
 395 #define TCU_TDFR(n)     (TCU_BASE + (0x40 + (n)*0x10))  /* Timer Data Full Reg */
 396 #define TCU_TDHR(n)     (TCU_BASE + (0x44 + (n)*0x10))  /* Timer Data Half Reg */
 397 #define TCU_TCNT(n)     (TCU_BASE + (0x48 + (n)*0x10))  /* Timer Counter Reg */
 398 #define TCU_TCSR(n)     (TCU_BASE + (0x4C + (n)*0x10))  /* Timer Control Reg */
 399
 400 #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
 401 #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
 402 #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
 403 #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
 404
 405 // Register definitions
 406 #define TCU_TCSR_PWM_SD         (1 << 9)
 407 #define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
 408 #define TCU_TCSR_PWM_EN         (1 << 7)
 409 #define TCU_TCSR_PRESCALE_BIT   3
 410 #define TCU_TCSR_PRESCALE_MASK  (0x7 << TCU_TCSR_PRESCALE_BIT)
 411 #define TCU_TCSR_PRESCALE1      (0x0 << TCU_TCSR_PRESCALE_BIT)
 412 #define TCU_TCSR_PRESCALE4      (0x1 << TCU_TCSR_PRESCALE_BIT)
 413 #define TCU_TCSR_PRESCALE16     (0x2 << TCU_TCSR_PRESCALE_BIT)
 414 #define TCU_TCSR_PRESCALE64     (0x3 << TCU_TCSR_PRESCALE_BIT)
 415 #define TCU_TCSR_PRESCALE256    (0x4 << TCU_TCSR_PRESCALE_BIT)
 416 #define TCU_TCSR_PRESCALE1024   (0x5 << TCU_TCSR_PRESCALE_BIT)
 417 #define TCU_TCSR_EXT_EN         (1 << 2)
 418 #define TCU_TCSR_RTC_EN         (1 << 1)
 419 #define TCU_TCSR_PCK_EN         (1 << 0)
 420
 421 #define TCU_TER_TCEN5           (1 << 5)
 422 #define TCU_TER_TCEN4           (1 << 4)
 423 #define TCU_TER_TCEN3           (1 << 3)
 424 #define TCU_TER_TCEN2           (1 << 2)
 425 #define TCU_TER_TCEN1           (1 << 1)
 426 #define TCU_TER_TCEN0           (1 << 0)
 427
 428 #define TCU_TESR_TCST5          (1 << 5)
 429 #define TCU_TESR_TCST4          (1 << 4)
 430 #define TCU_TESR_TCST3          (1 << 3)
 431 #define TCU_TESR_TCST2          (1 << 2)
 432 #define TCU_TESR_TCST1          (1 << 1)
 433 #define TCU_TESR_TCST0          (1 << 0)
 434
 435 #define TCU_TECR_TCCL5          (1 << 5)
 436 #define TCU_TECR_TCCL4          (1 << 4)
 437 #define TCU_TECR_TCCL3          (1 << 3)
 438 #define TCU_TECR_TCCL2          (1 << 2)
 439 #define TCU_TECR_TCCL1          (1 << 1)
 440 #define TCU_TECR_TCCL0          (1 << 0)
 441
 442 #define TCU_TFR_HFLAG5          (1 << 21)
 443 #define TCU_TFR_HFLAG4          (1 << 20)
 444 #define TCU_TFR_HFLAG3          (1 << 19)
 445 #define TCU_TFR_HFLAG2          (1 << 18)
 446 #define TCU_TFR_HFLAG1          (1 << 17)
 447 #define TCU_TFR_HFLAG0          (1 << 16)
 448 #define TCU_TFR_FFLAG5          (1 << 5)
 449 #define TCU_TFR_FFLAG4          (1 << 4)
 450 #define TCU_TFR_FFLAG3          (1 << 3)
 451 #define TCU_TFR_FFLAG2          (1 << 2)
 452 #define TCU_TFR_FFLAG1          (1 << 1)
 453 #define TCU_TFR_FFLAG0          (1 << 0)
 454
 455 #define TCU_TFSR_HFLAG5         (1 << 21)
 456 #define TCU_TFSR_HFLAG4         (1 << 20)
 457 #define TCU_TFSR_HFLAG3         (1 << 19)
 458 #define TCU_TFSR_HFLAG2         (1 << 18)
 459 #define TCU_TFSR_HFLAG1         (1 << 17)
 460 #define TCU_TFSR_HFLAG0         (1 << 16)
 461 #define TCU_TFSR_FFLAG5         (1 << 5)
 462 #define TCU_TFSR_FFLAG4         (1 << 4)
 463 #define TCU_TFSR_FFLAG3         (1 << 3)
 464 #define TCU_TFSR_FFLAG2         (1 << 2)
 465 #define TCU_TFSR_FFLAG1         (1 << 1)
 466 #define TCU_TFSR_FFLAG0         (1 << 0)
 467
 468 #define TCU_TFCR_HFLAG5         (1 << 21)
 469 #define TCU_TFCR_HFLAG4         (1 << 20)
 470 #define TCU_TFCR_HFLAG3         (1 << 19)
 471 #define TCU_TFCR_HFLAG2         (1 << 18)
 472 #define TCU_TFCR_HFLAG1         (1 << 17)
 473 #define TCU_TFCR_HFLAG0         (1 << 16)
 474 #define TCU_TFCR_FFLAG5         (1 << 5)
 475 #define TCU_TFCR_FFLAG4         (1 << 4)
 476 #define TCU_TFCR_FFLAG3         (1 << 3)
 477 #define TCU_TFCR_FFLAG2         (1 << 2)
 478 #define TCU_TFCR_FFLAG1         (1 << 1)
 479 #define TCU_TFCR_FFLAG0         (1 << 0)
 480
 481 #define TCU_TMR_HMASK5          (1 << 21)
 482 #define TCU_TMR_HMASK4          (1 << 20)
 483 #define TCU_TMR_HMASK3          (1 << 19)
 484 #define TCU_TMR_HMASK2          (1 << 18)
 485 #define TCU_TMR_HMASK1          (1 << 17)
 486 #define TCU_TMR_HMASK0          (1 << 16)
 487 #define TCU_TMR_FMASK5          (1 << 5)
 488 #define TCU_TMR_FMASK4          (1 << 4)
 489 #define TCU_TMR_FMASK3          (1 << 3)
 490 #define TCU_TMR_FMASK2          (1 << 2)
 491 #define TCU_TMR_FMASK1          (1 << 1)
 492 #define TCU_TMR_FMASK0          (1 << 0)
 493
 494 #define TCU_TMSR_HMST5          (1 << 21)
 495 #define TCU_TMSR_HMST4          (1 << 20)
 496 #define TCU_TMSR_HMST3          (1 << 19)
 497 #define TCU_TMSR_HMST2          (1 << 18)
 498 #define TCU_TMSR_HMST1          (1 << 17)
 499 #define TCU_TMSR_HMST0          (1 << 16)
 500 #define TCU_TMSR_FMST5          (1 << 5)
 501 #define TCU_TMSR_FMST4          (1 << 4)
 502 #define TCU_TMSR_FMST3          (1 << 3)
 503 #define TCU_TMSR_FMST2          (1 << 2)
 504 #define TCU_TMSR_FMST1          (1 << 1)
 505 #define TCU_TMSR_FMST0          (1 << 0)
 506
 507 #define TCU_TMCR_HMCL5          (1 << 21)
 508 #define TCU_TMCR_HMCL4          (1 << 20)
 509 #define TCU_TMCR_HMCL3          (1 << 19)
 510 #define TCU_TMCR_HMCL2          (1 << 18)
 511 #define TCU_TMCR_HMCL1          (1 << 17)
 512 #define TCU_TMCR_HMCL0          (1 << 16)
 513 #define TCU_TMCR_FMCL5          (1 << 5)
 514 #define TCU_TMCR_FMCL4          (1 << 4)
 515 #define TCU_TMCR_FMCL3          (1 << 3)
 516 #define TCU_TMCR_FMCL2          (1 << 2)
 517 #define TCU_TMCR_FMCL1          (1 << 1)
 518 #define TCU_TMCR_FMCL0          (1 << 0)
 519
 520 #define TCU_TSR_WDTS            (1 << 16)
 521 #define TCU_TSR_STOP5           (1 << 5)
 522 #define TCU_TSR_STOP4           (1 << 4)
 523 #define TCU_TSR_STOP3           (1 << 3)
 524 #define TCU_TSR_STOP2           (1 << 2)
 525 #define TCU_TSR_STOP1           (1 << 1)
 526 #define TCU_TSR_STOP0           (1 << 0)
 527
 528 #define TCU_TSSR_WDTSS          (1 << 16)
 529 #define TCU_TSSR_STPS5          (1 << 5)
 530 #define TCU_TSSR_STPS4          (1 << 4)
 531 #define TCU_TSSR_STPS3          (1 << 3)
 532 #define TCU_TSSR_STPS2          (1 << 2)
 533 #define TCU_TSSR_STPS1          (1 << 1)
 534 #define TCU_TSSR_STPS0          (1 << 0)
 535
 536 #define TCU_TSSR_WDTSC          (1 << 16)
 537 #define TCU_TSSR_STPC5          (1 << 5)
 538 #define TCU_TSSR_STPC4          (1 << 4)
 539 #define TCU_TSSR_STPC3          (1 << 3)
 540 #define TCU_TSSR_STPC2          (1 << 2)
 541 #define TCU_TSSR_STPC1          (1 << 1)
 542 #define TCU_TSSR_STPC0          (1 << 0)
 543
 544
 545 /*************************************************************************
 546  * WDT (WatchDog Timer)
 547  *************************************************************************/
 548 #define WDT_TDR         (WDT_BASE + 0x00)
 549 #define WDT_TCER        (WDT_BASE + 0x04)
 550 #define WDT_TCNT        (WDT_BASE + 0x08)
 551 #define WDT_TCSR        (WDT_BASE + 0x0C)
 552
 553 #define REG_WDT_TDR     REG16(WDT_TDR)
 554 #define REG_WDT_TCER    REG8(WDT_TCER)
 555 #define REG_WDT_TCNT    REG16(WDT_TCNT)
 556 #define REG_WDT_TCSR    REG16(WDT_TCSR)
 557
 558 // Register definition
 559 #define WDT_TCSR_PRESCALE_BIT   3
 560 #define WDT_TCSR_PRESCALE_MASK  (0x7 << WDT_TCSR_PRESCALE_BIT)
 561 #define WDT_TCSR_PRESCALE1      (0x0 << WDT_TCSR_PRESCALE_BIT)
 562 #define WDT_TCSR_PRESCALE4      (0x1 << WDT_TCSR_PRESCALE_BIT)
 563 #define WDT_TCSR_PRESCALE16     (0x2 << WDT_TCSR_PRESCALE_BIT)
 564 #define WDT_TCSR_PRESCALE64     (0x3 << WDT_TCSR_PRESCALE_BIT)
 565 #define WDT_TCSR_PRESCALE256    (0x4 << WDT_TCSR_PRESCALE_BIT)
 566 #define WDT_TCSR_PRESCALE1024   (0x5 << WDT_TCSR_PRESCALE_BIT)
 567 #define WDT_TCSR_EXT_EN         (1 << 2)
 568 #define WDT_TCSR_RTC_EN         (1 << 1)
 569 #define WDT_TCSR_PCK_EN         (1 << 0)
 570
 571 #define WDT_TCER_TCEN           (1 << 0)
 572
 573
 574 /*************************************************************************
 575  * DMAC (DMA Controller)
 576  *************************************************************************/
 577
 578 #define MAX_DMA_NUM     6       /* max 6 channels */
 579
 580 #define DMAC_DSAR(n)    (DMAC_BASE + (0x00 + (n) * 0x20))       /* DMA source address */
 581 #define DMAC_DTAR(n)    (DMAC_BASE + (0x04 + (n) * 0x20))       /* DMA target address */
 582 #define DMAC_DTCR(n)    (DMAC_BASE + (0x08 + (n) * 0x20))       /* DMA transfer count */
 583 #define DMAC_DRSR(n)    (DMAC_BASE + (0x0c + (n) * 0x20))       /* DMA request source */
 584 #define DMAC_DCCSR(n)   (DMAC_BASE + (0x10 + (n) * 0x20))       /* DMA control/status */
 585 #define DMAC_DCMD(n)    (DMAC_BASE + (0x14 + (n) * 0x20))       /* DMA command */
 586 #define DMAC_DDA(n)     (DMAC_BASE + (0x18 + (n) * 0x20))       /* DMA descriptor address */
 587 #define DMAC_DMACR      (DMAC_BASE + 0x0300)    /* DMA control register */
 588 #define DMAC_DMAIPR     (DMAC_BASE + 0x0304)    /* DMA interrupt pending */
 589 #define DMAC_DMADBR     (DMAC_BASE + 0x0308)    /* DMA doorbell */
 590 #define DMAC_DMADBSR    (DMAC_BASE + 0x030C)    /* DMA doorbell set */
 591
 592 // channel 0
 593 #define DMAC_DSAR0      DMAC_DSAR(0)
 594 #define DMAC_DTAR0      DMAC_DTAR(0)
 595 #define DMAC_DTCR0      DMAC_DTCR(0)
 596 #define DMAC_DRSR0      DMAC_DRSR(0)
 597 #define DMAC_DCCSR0     DMAC_DCCSR(0)
 598 #define DMAC_DCMD0      DMAC_DCMD(0)
 599 #define DMAC_DDA0       DMAC_DDA(0)
 600
 601 // channel 1
 602 #define DMAC_DSAR1      DMAC_DSAR(1)
 603 #define DMAC_DTAR1      DMAC_DTAR(1)
 604 #define DMAC_DTCR1      DMAC_DTCR(1)
 605 #define DMAC_DRSR1      DMAC_DRSR(1)
 606 #define DMAC_DCCSR1     DMAC_DCCSR(1)
 607 #define DMAC_DCMD1      DMAC_DCMD(1)
 608 #define DMAC_DDA1       DMAC_DDA(1)
 609
 610 // channel 2
 611 #define DMAC_DSAR2      DMAC_DSAR(2)
 612 #define DMAC_DTAR2      DMAC_DTAR(2)
 613 #define DMAC_DTCR2      DMAC_DTCR(2)
 614 #define DMAC_DRSR2      DMAC_DRSR(2)
 615 #define DMAC_DCCSR2     DMAC_DCCSR(2)
 616 #define DMAC_DCMD2      DMAC_DCMD(2)
 617 #define DMAC_DDA2       DMAC_DDA(2)
 618
 619 // channel 3
 620 #define DMAC_DSAR3      DMAC_DSAR(3)
 621 #define DMAC_DTAR3      DMAC_DTAR(3)
 622 #define DMAC_DTCR3      DMAC_DTCR(3)
 623 #define DMAC_DRSR3      DMAC_DRSR(3)
 624 #define DMAC_DCCSR3     DMAC_DCCSR(3)
 625 #define DMAC_DCMD3      DMAC_DCMD(3)
 626 #define DMAC_DDA3       DMAC_DDA(3)
 627
 628 // channel 4
 629 #define DMAC_DSAR4      DMAC_DSAR(4)
 630 #define DMAC_DTAR4      DMAC_DTAR(4)
 631 #define DMAC_DTCR4      DMAC_DTCR(4)
 632 #define DMAC_DRSR4      DMAC_DRSR(4)
 633 #define DMAC_DCCSR4     DMAC_DCCSR(4)
 634 #define DMAC_DCMD4      DMAC_DCMD(4)
 635 #define DMAC_DDA4       DMAC_DDA(4)
 636
 637 // channel 5
 638 #define DMAC_DSAR5      DMAC_DSAR(5)
 639 #define DMAC_DTAR5      DMAC_DTAR(5)
 640 #define DMAC_DTCR5      DMAC_DTCR(5)
 641 #define DMAC_DRSR5      DMAC_DRSR(5)
 642 #define DMAC_DCCSR5     DMAC_DCCSR(5)
 643 #define DMAC_DCMD5      DMAC_DCMD(5)
 644 #define DMAC_DDA5       DMAC_DDA(5)
 645
 646 #define REG_DMAC_DSAR(n)        REG32(DMAC_DSAR((n)))
 647 #define REG_DMAC_DTAR(n)        REG32(DMAC_DTAR((n)))
 648 #define REG_DMAC_DTCR(n)        REG32(DMAC_DTCR((n)))
 649 #define REG_DMAC_DRSR(n)        REG32(DMAC_DRSR((n)))
 650 #define REG_DMAC_DCCSR(n)       REG32(DMAC_DCCSR((n)))
 651 #define REG_DMAC_DCMD(n)        REG32(DMAC_DCMD((n)))
 652 #define REG_DMAC_DDA(n)         REG32(DMAC_DDA((n)))
 653 #define REG_DMAC_DMACR          REG32(DMAC_DMACR)
 654 #define REG_DMAC_DMAIPR         REG32(DMAC_DMAIPR)
 655 #define REG_DMAC_DMADBR         REG32(DMAC_DMADBR)
 656 #define REG_DMAC_DMADBSR        REG32(DMAC_DMADBSR)
 657
 658 // DMA request source register
 659 #define DMAC_DRSR_RS_BIT        0
 660 #define DMAC_DRSR_RS_MASK       (0x1f << DMAC_DRSR_RS_BIT)
 661 #define DMAC_DRSR_RS_AUTO       (8 << DMAC_DRSR_RS_BIT)
 662 #define DMAC_DRSR_RS_UART0OUT   (20 << DMAC_DRSR_RS_BIT)
 663 #define DMAC_DRSR_RS_UART0IN    (21 << DMAC_DRSR_RS_BIT)
 664 #define DMAC_DRSR_RS_SSIOUT     (22 << DMAC_DRSR_RS_BIT)
 665 #define DMAC_DRSR_RS_SSIIN      (23 << DMAC_DRSR_RS_BIT)
 666 #define DMAC_DRSR_RS_AICOUT     (24 << DMAC_DRSR_RS_BIT)
 667 #define DMAC_DRSR_RS_AICIN      (25 << DMAC_DRSR_RS_BIT)
 668 #define DMAC_DRSR_RS_MSCOUT     (26 << DMAC_DRSR_RS_BIT)
 669 #define DMAC_DRSR_RS_MSCIN      (27 << DMAC_DRSR_RS_BIT)
 670 #define DMAC_DRSR_RS_TCU        (28 << DMAC_DRSR_RS_BIT)
 671 #define DMAC_DRSR_RS_SADC       (29 << DMAC_DRSR_RS_BIT)
 672 #define DMAC_DRSR_RS_SLCD       (30 << DMAC_DRSR_RS_BIT)
 673
 674 // DMA channel control/status register
 675 #define DMAC_DCCSR_NDES         (1 << 31)       /* descriptor (0) or not (1) ? */
 676 #define DMAC_DCCSR_CDOA_BIT     16      /* copy of DMA offset address */
 677 #define DMAC_DCCSR_CDOA_MASK    (0xff << DMAC_DCCSR_CDOA_BIT)
 678 #define DMAC_DCCSR_INV          (1 << 6)        /* descriptor invalid */
 679 #define DMAC_DCCSR_AR           (1 << 4)        /* address error */
 680 #define DMAC_DCCSR_TT           (1 << 3)        /* transfer terminated */
 681 #define DMAC_DCCSR_HLT          (1 << 2)        /* DMA halted */
 682 #define DMAC_DCCSR_CT           (1 << 1)        /* count terminated */
 683 #define DMAC_DCCSR_EN           (1 << 0)        /* channel enable bit */
 684
 685 // DMA channel command register
 686 #define DMAC_DCMD_SAI           (1 << 23)       /* source address increment */
 687 #define DMAC_DCMD_DAI           (1 << 22)       /* dest address increment */
 688 #define DMAC_DCMD_RDIL_BIT      16      /* request detection interval length */
 689 #define DMAC_DCMD_RDIL_MASK     (0x0f << DMAC_DCMD_RDIL_BIT)
 690 #define DMAC_DCMD_RDIL_IGN      (0 << DMAC_DCMD_RDIL_BIT)
 691 #define DMAC_DCMD_RDIL_2        (1 << DMAC_DCMD_RDIL_BIT)
 692 #define DMAC_DCMD_RDIL_4        (2 << DMAC_DCMD_RDIL_BIT)
 693 #define DMAC_DCMD_RDIL_8        (3 << DMAC_DCMD_RDIL_BIT)
 694 #define DMAC_DCMD_RDIL_12       (4 << DMAC_DCMD_RDIL_BIT)
 695 #define DMAC_DCMD_RDIL_16       (5 << DMAC_DCMD_RDIL_BIT)
 696 #define DMAC_DCMD_RDIL_20       (6 << DMAC_DCMD_RDIL_BIT)
 697 #define DMAC_DCMD_RDIL_24       (7 << DMAC_DCMD_RDIL_BIT)
 698 #define DMAC_DCMD_RDIL_28       (8 << DMAC_DCMD_RDIL_BIT)
 699 #define DMAC_DCMD_RDIL_32       (9 << DMAC_DCMD_RDIL_BIT)
 700 #define DMAC_DCMD_RDIL_48       (10 << DMAC_DCMD_RDIL_BIT)
 701 #define DMAC_DCMD_RDIL_60       (11 << DMAC_DCMD_RDIL_BIT)
 702 #define DMAC_DCMD_RDIL_64       (12 << DMAC_DCMD_RDIL_BIT)
 703 #define DMAC_DCMD_RDIL_124      (13 << DMAC_DCMD_RDIL_BIT)
 704 #define DMAC_DCMD_RDIL_128      (14 << DMAC_DCMD_RDIL_BIT)
 705 #define DMAC_DCMD_RDIL_200      (15 << DMAC_DCMD_RDIL_BIT)
 706 #define DMAC_DCMD_SWDH_BIT      14      /* source port width */
 707 #define DMAC_DCMD_SWDH_MASK     (0x03 << DMAC_DCMD_SWDH_BIT)
 708 #define DMAC_DCMD_SWDH_32       (0 << DMAC_DCMD_SWDH_BIT)
 709 #define DMAC_DCMD_SWDH_8        (1 << DMAC_DCMD_SWDH_BIT)
 710 #define DMAC_DCMD_SWDH_16       (2 << DMAC_DCMD_SWDH_BIT)
 711 #define DMAC_DCMD_DWDH_BIT      12      /* dest port width */
 712 #define DMAC_DCMD_DWDH_MASK     (0x03 << DMAC_DCMD_DWDH_BIT)
 713 #define DMAC_DCMD_DWDH_32       (0 << DMAC_DCMD_DWDH_BIT)
 714 #define DMAC_DCMD_DWDH_8        (1 << DMAC_DCMD_DWDH_BIT)
 715 #define DMAC_DCMD_DWDH_16       (2 << DMAC_DCMD_DWDH_BIT)
 716 #define DMAC_DCMD_DS_BIT        8       /* transfer data size of a data unit */
 717 #define DMAC_DCMD_DS_MASK       (0x07 << DMAC_DCMD_DS_BIT)
 718 #define DMAC_DCMD_DS_32BIT      (0 << DMAC_DCMD_DS_BIT)
 719 #define DMAC_DCMD_DS_8BIT       (1 << DMAC_DCMD_DS_BIT)
 720 #define DMAC_DCMD_DS_16BIT      (2 << DMAC_DCMD_DS_BIT)
 721 #define DMAC_DCMD_DS_16BYTE     (3 << DMAC_DCMD_DS_BIT)
 722 #define DMAC_DCMD_DS_32BYTE     (4 << DMAC_DCMD_DS_BIT)
 723 #define DMAC_DCMD_TM            (1 << 7)        /* transfer mode: 0-single 1-block */
 724 #define DMAC_DCMD_DES_V         (1 << 4)        /* descriptor valid flag */
 725 #define DMAC_DCMD_DES_VM        (1 << 3)        /* descriptor valid mask: 1:support V-bit */
 726 #define DMAC_DCMD_DES_VIE       (1 << 2)        /* DMA valid error interrupt enable */
 727 #define DMAC_DCMD_TIE           (1 << 1)        /* DMA transfer interrupt enable */
 728 #define DMAC_DCMD_LINK          (1 << 0)        /* descriptor link enable */
 729
 730 // DMA descriptor address register
 731 #define DMAC_DDA_BASE_BIT       12      /* descriptor base address */
 732 #define DMAC_DDA_BASE_MASK      (0x0fffff << DMAC_DDA_BASE_BIT)
 733 #define DMAC_DDA_OFFSET_BIT     4       /* descriptor offset address */
 734 #define DMAC_DDA_OFFSET_MASK    (0x0ff << DMAC_DDA_OFFSET_BIT)
 735
 736 // DMA control register
 737 #define DMAC_DMACR_PR_BIT       8       /* channel priority mode */
 738 #define DMAC_DMACR_PR_MASK      (0x03 << DMAC_DMACR_PR_BIT)
 739 #define DMAC_DMACR_PR_012345    (0 << DMAC_DMACR_PR_BIT)
 740 #define DMAC_DMACR_PR_023145    (1 << DMAC_DMACR_PR_BIT)
 741 #define DMAC_DMACR_PR_201345    (2 << DMAC_DMACR_PR_BIT)
 742 #define DMAC_DMACR_PR_RR        (3 << DMAC_DMACR_PR_BIT)        /* round robin */
 743 #define DMAC_DMACR_HLT          (1 << 3)        /* DMA halt flag */
 744 #define DMAC_DMACR_AR           (1 << 2)        /* address error flag */
 745 #define DMAC_DMACR_DMAE         (1 << 0)        /* DMA enable bit */
 746
 747 // DMA doorbell register
 748 #define DMAC_DMADBR_DB5         (1 << 5)        /* doorbell for channel 5 */
 749 #define DMAC_DMADBR_DB4         (1 << 5)        /* doorbell for channel 4 */
 750 #define DMAC_DMADBR_DB3         (1 << 5)        /* doorbell for channel 3 */
 751 #define DMAC_DMADBR_DB2         (1 << 5)        /* doorbell for channel 2 */
 752 #define DMAC_DMADBR_DB1         (1 << 5)        /* doorbell for channel 1 */
 753 #define DMAC_DMADBR_DB0         (1 << 5)        /* doorbell for channel 0 */
 754
 755 // DMA doorbell set register
 756 #define DMAC_DMADBSR_DBS5       (1 << 5)        /* enable doorbell for channel 5 */
 757 #define DMAC_DMADBSR_DBS4       (1 << 5)        /* enable doorbell for channel 4 */
 758 #define DMAC_DMADBSR_DBS3       (1 << 5)        /* enable doorbell for channel 3 */
 759 #define DMAC_DMADBSR_DBS2       (1 << 5)        /* enable doorbell for channel 2 */
 760 #define DMAC_DMADBSR_DBS1       (1 << 5)        /* enable doorbell for channel 1 */
 761 #define DMAC_DMADBSR_DBS0       (1 << 5)        /* enable doorbell for channel 0 */
 762
 763 // DMA interrupt pending register
 764 #define DMAC_DMAIPR_CIRQ5       (1 << 5)        /* irq pending status for channel 5 */
 765 #define DMAC_DMAIPR_CIRQ4       (1 << 4)        /* irq pending status for channel 4 */
 766 #define DMAC_DMAIPR_CIRQ3       (1 << 3)        /* irq pending status for channel 3 */
 767 #define DMAC_DMAIPR_CIRQ2       (1 << 2)        /* irq pending status for channel 2 */
 768 #define DMAC_DMAIPR_CIRQ1       (1 << 1)        /* irq pending status for channel 1 */
 769 #define DMAC_DMAIPR_CIRQ0       (1 << 0)        /* irq pending status for channel 0 */
 770
 771
 772 /*************************************************************************
 773  * GPIO (General-Purpose I/O Ports)
 774  *************************************************************************/
 775 #define MAX_GPIO_NUM    128
 776
 777 //n = 0,1,2,3
 778 #define GPIO_PXPIN(n)   (GPIO_BASE + (0x00 + (n)*0x100))        /* PIN Level Register */
 779 #define GPIO_PXDAT(n)   (GPIO_BASE + (0x10 + (n)*0x100))        /* Port Data Register */
 780 #define GPIO_PXDATS(n)  (GPIO_BASE + (0x14 + (n)*0x100))        /* Port Data Set Register */
 781 #define GPIO_PXDATC(n)  (GPIO_BASE + (0x18 + (n)*0x100))        /* Port Data Clear Register */
 782 #define GPIO_PXIM(n)    (GPIO_BASE + (0x20 + (n)*0x100))        /* Interrupt Mask Register */
 783 #define GPIO_PXIMS(n)   (GPIO_BASE + (0x24 + (n)*0x100))        /* Interrupt Mask Set Reg */
 784 #define GPIO_PXIMC(n)   (GPIO_BASE + (0x28 + (n)*0x100))        /* Interrupt Mask Clear Reg */
 785 #define GPIO_PXPE(n)    (GPIO_BASE + (0x30 + (n)*0x100))        /* Pull Enable Register */
 786 #define GPIO_PXPES(n)   (GPIO_BASE + (0x34 + (n)*0x100))        /* Pull Enable Set Reg. */
 787 #define GPIO_PXPEC(n)   (GPIO_BASE + (0x38 + (n)*0x100))        /* Pull Enable Clear Reg. */
 788 #define GPIO_PXFUN(n)   (GPIO_BASE + (0x40 + (n)*0x100))        /* Function Register */
 789 #define GPIO_PXFUNS(n)  (GPIO_BASE + (0x44 + (n)*0x100))        /* Function Set Register */
 790 #define GPIO_PXFUNC(n)  (GPIO_BASE + (0x48 + (n)*0x100))        /* Function Clear Register */
 791 #define GPIO_PXSEL(n)   (GPIO_BASE + (0x50 + (n)*0x100))        /* Select Register */
 792 #define GPIO_PXSELS(n)  (GPIO_BASE + (0x54 + (n)*0x100))        /* Select Set Register */
 793 #define GPIO_PXSELC(n)  (GPIO_BASE + (0x58 + (n)*0x100))        /* Select Clear Register */
 794 #define GPIO_PXDIR(n)   (GPIO_BASE + (0x60 + (n)*0x100))        /* Direction Register */
 795 #define GPIO_PXDIRS(n)  (GPIO_BASE + (0x64 + (n)*0x100))        /* Direction Set Register */
 796 #define GPIO_PXDIRC(n)  (GPIO_BASE + (0x68 + (n)*0x100))        /* Direction Clear Register */
 797 #define GPIO_PXTRG(n)   (GPIO_BASE + (0x70 + (n)*0x100))        /* Trigger Register */
 798 #define GPIO_PXTRGS(n)  (GPIO_BASE + (0x74 + (n)*0x100))        /* Trigger Set Register */
 799 #define GPIO_PXTRGC(n)  (GPIO_BASE + (0x78 + (n)*0x100))        /* Trigger Set Register */
 800 #define GPIO_PXFLG(n)   (GPIO_BASE + (0x80 + (n)*0x100))        /* Port Flag Register */
 801 #define GPIO_PXFLGC(n)  (GPIO_BASE + (0x14 + (n)*0x100))        /* Port Flag clear Register */
 802
 803 #define REG_GPIO_PXPIN(n)       REG32(GPIO_PXPIN((n)))  /* PIN level */
 804 #define REG_GPIO_PXDAT(n)       REG32(GPIO_PXDAT((n)))  /* 1: interrupt pending */
 805 #define REG_GPIO_PXDATS(n)      REG32(GPIO_PXDATS((n)))
 806 #define REG_GPIO_PXDATC(n)      REG32(GPIO_PXDATC((n)))
 807 #define REG_GPIO_PXIM(n)        REG32(GPIO_PXIM((n)))   /* 1: mask pin interrupt */
 808 #define REG_GPIO_PXIMS(n)       REG32(GPIO_PXIMS((n)))
 809 #define REG_GPIO_PXIMC(n)       REG32(GPIO_PXIMC((n)))
 810 #define REG_GPIO_PXPE(n)        REG32(GPIO_PXPE((n)))   /* 1: disable pull up/down */
 811 #define REG_GPIO_PXPES(n)       REG32(GPIO_PXPES((n)))
 812 #define REG_GPIO_PXPEC(n)       REG32(GPIO_PXPEC((n)))
 813 #define REG_GPIO_PXFUN(n)       REG32(GPIO_PXFUN((n)))  /* 0:GPIO or intr, 1:FUNC */
 814 #define REG_GPIO_PXFUNS(n)      REG32(GPIO_PXFUNS((n)))
 815 #define REG_GPIO_PXFUNC(n)      REG32(GPIO_PXFUNC((n)))
 816 #define REG_GPIO_PXSEL(n)       REG32(GPIO_PXSEL((n)))  /* 0:GPIO/Fun0,1:intr/fun1 */
 817 #define REG_GPIO_PXSELS(n)      REG32(GPIO_PXSELS((n)))
 818 #define REG_GPIO_PXSELC(n)      REG32(GPIO_PXSELC((n)))
 819 #define REG_GPIO_PXDIR(n)       REG32(GPIO_PXDIR((n)))  /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
 820 #define REG_GPIO_PXDIRS(n)      REG32(GPIO_PXDIRS((n)))
 821 #define REG_GPIO_PXDIRC(n)      REG32(GPIO_PXDIRC((n)))
 822 #define REG_GPIO_PXTRG(n)       REG32(GPIO_PXTRG((n)))  /* 0:level-trigger, 1:edge-trigger */
 823 #define REG_GPIO_PXTRGS(n)      REG32(GPIO_PXTRGS((n)))
 824 #define REG_GPIO_PXTRGC(n)      REG32(GPIO_PXTRGC((n)))
 825 #define REG_GPIO_PXFLG(n)       REG32(GPIO_PXFLG((n)))  /* interrupt flag */
 826 #define REG_GPIO_PXFLGC(n)      REG32(GPIO_PXFLGC((n))) /* interrupt flag */
 827
 828
 829 /*************************************************************************
 830  * UART
 831  *************************************************************************/
 832
 833 #define IRDA_BASE       UART0_BASE
 834 #define UART_BASE       UART0_BASE
 835 #define UART_OFF        0x1000
 836
 837 /* Register Offset */
 838 #define OFF_RDR         (0x00)  /* R  8b H'xx */
 839 #define OFF_TDR         (0x00)  /* W  8b H'xx */
 840 #define OFF_DLLR        (0x00)  /* RW 8b H'00 */
 841 #define OFF_DLHR        (0x04)  /* RW 8b H'00 */
 842 #define OFF_IER         (0x04)  /* RW 8b H'00 */
 843 #define OFF_ISR         (0x08)  /* R  8b H'01 */
 844 #define OFF_FCR         (0x08)  /* W  8b H'00 */
 845 #define OFF_LCR         (0x0C)  /* RW 8b H'00 */
 846 #define OFF_MCR         (0x10)  /* RW 8b H'00 */
 847 #define OFF_LSR         (0x14)  /* R  8b H'00 */
 848 #define OFF_MSR         (0x18)  /* R  8b H'00 */
 849 #define OFF_SPR         (0x1C)  /* RW 8b H'00 */
 850 #define OFF_SIRCR       (0x20)  /* RW 8b H'00, UART0 */
 851 #define OFF_UMR         (0x24)  /* RW 8b H'00, UART M Register */
 852 #define OFF_UACR        (0x28)  /* RW 8b H'00, UART Add Cycle Register */
 853
 854 /* Register Address */
 855 #define UART0_RDR       (UART0_BASE + OFF_RDR)
 856 #define UART0_TDR       (UART0_BASE + OFF_TDR)
 857 #define UART0_DLLR      (UART0_BASE + OFF_DLLR)
 858 #define UART0_DLHR      (UART0_BASE + OFF_DLHR)
 859 #define UART0_IER       (UART0_BASE + OFF_IER)
 860 #define UART0_ISR       (UART0_BASE + OFF_ISR)
 861 #define UART0_FCR       (UART0_BASE + OFF_FCR)
 862 #define UART0_LCR       (UART0_BASE + OFF_LCR)
 863 #define UART0_MCR       (UART0_BASE + OFF_MCR)
 864 #define UART0_LSR       (UART0_BASE + OFF_LSR)
 865 #define UART0_MSR       (UART0_BASE + OFF_MSR)
 866 #define UART0_SPR       (UART0_BASE + OFF_SPR)
 867 #define UART0_SIRCR     (UART0_BASE + OFF_SIRCR)
 868 #define UART0_UMR       (UART0_BASE + OFF_UMR)
 869 #define UART0_UACR      (UART0_BASE + OFF_UACR)
 870
 871 /*
 872  * Define macros for UART_IER
 873  * UART Interrupt Enable Register
 874  */
 875 #define UART_IER_RIE    (1 << 0)        /* 0: receive fifo "full" interrupt disable */
 876 #define UART_IER_TIE    (1 << 1)        /* 0: transmit fifo "empty" interrupt disable */
 877 #define UART_IER_RLIE   (1 << 2)        /* 0: receive line status interrupt disable */
 878 #define UART_IER_MIE    (1 << 3)        /* 0: modem status interrupt disable */
 879 #define UART_IER_RTIE   (1 << 4)        /* 0: receive timeout interrupt disable */
 880
 881 /*
 882  * Define macros for UART_ISR
 883  * UART Interrupt Status Register
 884  */
 885 #define UART_ISR_IP     (1 << 0)        /* 0: interrupt is pending  1: no interrupt */
 886 #define UART_ISR_IID    (7 << 1)        /* Source of Interrupt */
 887 #define UART_ISR_IID_MSI                (0 << 1)        /* Modem status interrupt */
 888 #define UART_ISR_IID_THRI       (1 << 1)        /* Transmitter holding register empty */
 889 #define UART_ISR_IID_RDI                (2 << 1)        /* Receiver data interrupt */
 890 #define UART_ISR_IID_RLSI       (3 << 1)        /* Receiver line status interrupt */
 891 #define UART_ISR_FFMS   (3 << 6)        /* FIFO mode select, set when UART_FCR.FE is set to 1 */
 892 #define UART_ISR_FFMS_NO_FIFO   (0 << 6)
 893 #define UART_ISR_FFMS_FIFO_MODE (3 << 6)
 894
 895 /*
 896  * Define macros for UART_FCR
 897  * UART FIFO Control Register
 898  */
 899 #define UART_FCR_FE     (1 << 0)        /* 0: non-FIFO mode  1: FIFO mode */
 900 #define UART_FCR_RFLS   (1 << 1)        /* write 1 to flush receive FIFO */
 901 #define UART_FCR_TFLS   (1 << 2)        /* write 1 to flush transmit FIFO */
 902 #define UART_FCR_DMS    (1 << 3)        /* 0: disable DMA mode */
 903 #define UART_FCR_UUE    (1 << 4)        /* 0: disable UART */
 904 #define UART_FCR_RTRG   (3 << 6)        /* Receive FIFO Data Trigger */
 905 #define UART_FCR_RTRG_1 (0 << 6)
 906 #define UART_FCR_RTRG_4 (1 << 6)
 907 #define UART_FCR_RTRG_8 (2 << 6)
 908 #define UART_FCR_RTRG_15        (3 << 6)
 909
 910 /*
 911  * Define macros for UART_LCR
 912  * UART Line Control Register
 913  */
 914 #define UART_LCR_WLEN   (3 << 0)        /* word length */
 915 #define UART_LCR_WLEN_5 (0 << 0)
 916 #define UART_LCR_WLEN_6 (1 << 0)
 917 #define UART_LCR_WLEN_7 (2 << 0)
 918 #define UART_LCR_WLEN_8 (3 << 0)
 919 #define UART_LCR_STOP   (1 << 2)        /* 0: 1 stop bit when word length is 5,6,7,8
 920                                            1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
 921 #define UART_LCR_STOP_1 (0 << 2)        /* 0: 1 stop bit when word length is 5,6,7,8
 922                                            1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
 923 #define UART_LCR_STOP_2 (1 << 2)        /* 0: 1 stop bit when word length is 5,6,7,8
 924                                            1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
 925
 926 #define UART_LCR_PE     (1 << 3)        /* 0: parity disable */
 927 #define UART_LCR_PROE   (1 << 4)        /* 0: even parity  1: odd parity */
 928 #define UART_LCR_SPAR   (1 << 5)        /* 0: sticky parity disable */
 929 #define UART_LCR_SBRK   (1 << 6)        /* write 0 normal, write 1 send break */
 930 #define UART_LCR_DLAB   (1 << 7)        /* 0: access UART_RDR/TDR/IER  1: access UART_DLLR/DLHR */
 931
 932 /*
 933  * Define macros for UART_LSR
 934  * UART Line Status Register
 935  */
 936 #define UART_LSR_DR     (1 << 0)        /* 0: receive FIFO is empty  1: receive data is ready */
 937 #define UART_LSR_ORER   (1 << 1)        /* 0: no overrun error */
 938 #define UART_LSR_PER    (1 << 2)        /* 0: no parity error */
 939 #define UART_LSR_FER    (1 << 3)        /* 0; no framing error */
 940 #define UART_LSR_BRK    (1 << 4)        /* 0: no break detected  1: receive a break signal */
 941 #define UART_LSR_TDRQ   (1 << 5)        /* 1: transmit FIFO half "empty" */
 942 #define UART_LSR_TEMT   (1 << 6)        /* 1: transmit FIFO and shift registers empty */
 943 #define UART_LSR_RFER   (1 << 7)        /* 0: no receive error  1: receive error in FIFO mode */
 944
 945 /*
 946  * Define macros for UART_MCR
 947  * UART Modem Control Register
 948  */
 949 #define UART_MCR_DTR    (1 << 0)        /* 0: DTR_ ouput high */
 950 #define UART_MCR_RTS    (1 << 1)        /* 0: RTS_ output high */
 951 #define UART_MCR_OUT1   (1 << 2)        /* 0: UART_MSR.RI is set to 0 and RI_ input high */
 952 #define UART_MCR_OUT2   (1 << 3)        /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
 953 #define UART_MCR_LOOP   (1 << 4)        /* 0: normal  1: loopback mode */
 954 #define UART_MCR_MCE    (1 << 7)        /* 0: modem function is disable */
 955
 956 /*
 957  * Define macros for UART_MSR
 958  * UART Modem Status Register
 959  */
 960 #define UART_MSR_DCTS   (1 << 0)        /* 0: no change on CTS_ pin since last read of UART_MSR */
 961 #define UART_MSR_DDSR   (1 << 1)        /* 0: no change on DSR_ pin since last read of UART_MSR */
 962 #define UART_MSR_DRI    (1 << 2)        /* 0: no change on RI_ pin since last read of UART_MSR */
 963 #define UART_MSR_DDCD   (1 << 3)        /* 0: no change on DCD_ pin since last read of UART_MSR */
 964 #define UART_MSR_CTS    (1 << 4)        /* 0: CTS_ pin is high */
 965 #define UART_MSR_DSR    (1 << 5)        /* 0: DSR_ pin is high */
 966 #define UART_MSR_RI     (1 << 6)        /* 0: RI_ pin is high */
 967 #define UART_MSR_DCD    (1 << 7)        /* 0: DCD_ pin is high */
 968
 969 /*
 970  * Define macros for SIRCR
 971  * Slow IrDA Control Register
 972  */
 973 #define SIRCR_TSIRE     (1 << 0)        /* 0: transmitter is in UART mode  1: IrDA mode */
 974 #define SIRCR_RSIRE     (1 << 1)        /* 0: receiver is in UART mode  1: IrDA mode */
 975 #define SIRCR_TPWS      (1 << 2)        /* 0: transmit 0 pulse width is 3/16 of bit length
 976                                            1: 0 pulse width is 1.6us for 115.2Kbps */
 977 #define SIRCR_TXPL      (1 << 3)        /* 0: encoder generates a positive pulse for 0 */
 978 #define SIRCR_RXPL      (1 << 4)        /* 0: decoder interprets positive pulse as 0 */
 979
 980
 981 /*************************************************************************
 982  * AIC (AC97/I2S Controller)
 983  *************************************************************************/
 984 #define AIC_FR                  (AIC_BASE + 0x000)
 985 #define AIC_CR                  (AIC_BASE + 0x004)
 986 #define AIC_ACCR1               (AIC_BASE + 0x008)
 987 #define AIC_ACCR2               (AIC_BASE + 0x00C)
 988 #define AIC_I2SCR               (AIC_BASE + 0x010)
 989 #define AIC_SR                  (AIC_BASE + 0x014)
 990 #define AIC_ACSR                (AIC_BASE + 0x018)
 991 #define AIC_I2SSR               (AIC_BASE + 0x01C)
 992 #define AIC_ACCAR               (AIC_BASE + 0x020)
 993 #define AIC_ACCDR               (AIC_BASE + 0x024)
 994 #define AIC_ACSAR               (AIC_BASE + 0x028)
 995 #define AIC_ACSDR               (AIC_BASE + 0x02C)
 996 #define AIC_I2SDIV              (AIC_BASE + 0x030)
 997 #define AIC_DR                  (AIC_BASE + 0x034)
 998
 999 #define REG_AIC_FR              REG32(AIC_FR)
1000 #define REG_AIC_CR              REG32(AIC_CR)
1001 #define REG_AIC_ACCR1           REG32(AIC_ACCR1)
1002 #define REG_AIC_ACCR2           REG32(AIC_ACCR2)
1003 #define REG_AIC_I2SCR           REG32(AIC_I2SCR)
1004 #define REG_AIC_SR              REG32(AIC_SR)
1005 #define REG_AIC_ACSR            REG32(AIC_ACSR)
1006 #define REG_AIC_I2SSR           REG32(AIC_I2SSR)
1007 #define REG_AIC_ACCAR           REG32(AIC_ACCAR)
1008 #define REG_AIC_ACCDR           REG32(AIC_ACCDR)
1009 #define REG_AIC_ACSAR           REG32(AIC_ACSAR)
1010 #define REG_AIC_ACSDR           REG32(AIC_ACSDR)
1011 #define REG_AIC_I2SDIV          REG32(AIC_I2SDIV)
1012 #define REG_AIC_DR              REG32(AIC_DR)
1013
1014 /* AIC Controller Configuration Register (AIC_FR) */
1015
1016 #define AIC_FR_RFTH_BIT         12      /* Receive FIFO Threshold */
1017 #define AIC_FR_RFTH_MASK        (0xf << AIC_FR_RFTH_BIT)
1018 #define AIC_FR_TFTH_BIT         8       /* Transmit FIFO Threshold */
1019 #define AIC_FR_TFTH_MASK        (0xf << AIC_FR_TFTH_BIT)
1020 #define AIC_FR_ICDC             (1 << 5)        /* External(0) or Internal CODEC(1) */
1021 #define AIC_FR_AUSEL            (1 << 4)        /* AC97(0) or I2S/MSB-justified(1) */
1022 #define AIC_FR_RST              (1 << 3)        /* AIC registers reset */
1023 #define AIC_FR_BCKD             (1 << 2)        /* I2S BIT_CLK direction, 0:input,1:output */
1024 #define AIC_FR_SYNCD            (1 << 1)        /* I2S SYNC direction, 0:input,1:output */
1025 #define AIC_FR_ENB              (1 << 0)        /* AIC enable bit */
1026
1027 /* AIC Controller Common Control Register (AIC_CR) */
1028
1029 #define AIC_CR_OSS_BIT          19      /* Output Sample Size from memory (AIC V2 only) */
1030 #define AIC_CR_OSS_MASK         (0x7 << AIC_CR_OSS_BIT)
1031 #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1032 #define AIC_CR_OSS_16BIT        (0x1 << AIC_CR_OSS_BIT)
1033 #define AIC_CR_OSS_18BIT        (0x2 << AIC_CR_OSS_BIT)
1034 #define AIC_CR_OSS_20BIT        (0x3 << AIC_CR_OSS_BIT)
1035 #define AIC_CR_OSS_24BIT        (0x4 << AIC_CR_OSS_BIT)
1036 #define AIC_CR_ISS_BIT          16      /* Input Sample Size from memory (AIC V2 only) */
1037 #define AIC_CR_ISS_MASK         (0x7 << AIC_CR_ISS_BIT)
1038 #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1039 #define AIC_CR_ISS_16BIT        (0x1 << AIC_CR_ISS_BIT)
1040 #define AIC_CR_ISS_18BIT        (0x2 << AIC_CR_ISS_BIT)
1041 #define AIC_CR_ISS_20BIT        (0x3 << AIC_CR_ISS_BIT)
1042 #define AIC_CR_ISS_24BIT        (0x4 << AIC_CR_ISS_BIT)
1043 #define AIC_CR_RDMS             (1 << 15)       /* Receive DMA enable */
1044 #define AIC_CR_TDMS             (1 << 14)       /* Transmit DMA enable */
1045 #define AIC_CR_M2S              (1 << 11)       /* Mono to Stereo enable */
1046 #define AIC_CR_ENDSW            (1 << 10)       /* Endian switch enable */
1047 #define AIC_CR_AVSTSU           (1 << 9)        /* Signed <-> Unsigned toggle enable */
1048 #define AIC_CR_FLUSH            (1 << 8)        /* Flush FIFO */
1049 #define AIC_CR_EROR             (1 << 6)        /* Enable ROR interrupt */
1050 #define AIC_CR_ETUR             (1 << 5)        /* Enable TUR interrupt */
1051 #define AIC_CR_ERFS             (1 << 4)        /* Enable RFS interrupt */
1052 #define AIC_CR_ETFS             (1 << 3)        /* Enable TFS interrupt */
1053 #define AIC_CR_ENLBF            (1 << 2)        /* Enable Loopback Function */
1054 #define AIC_CR_ERPL             (1 << 1)        /* Enable Playback Function */
1055 #define AIC_CR_EREC             (1 << 0)        /* Enable Record Function */
1056
1057 /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1058
1059 #define AIC_ACCR1_RS_BIT        16      /* Receive Valid Slots */
1060 #define AIC_ACCR1_RS_MASK       (0x3ff << AIC_ACCR1_RS_BIT)
1061 #define AIC_ACCR1_RS_SLOT12       (1 << 25)     /* Slot 12 valid bit */
1062 #define AIC_ACCR1_RS_SLOT11       (1 << 24)     /* Slot 11 valid bit */
1063 #define AIC_ACCR1_RS_SLOT10       (1 << 23)     /* Slot 10 valid bit */
1064 #define AIC_ACCR1_RS_SLOT9        (1 << 22)     /* Slot 9 valid bit, LFE */
1065 #define AIC_ACCR1_RS_SLOT8        (1 << 21)     /* Slot 8 valid bit, Surround Right */
1066 #define AIC_ACCR1_RS_SLOT7        (1 << 20)     /* Slot 7 valid bit, Surround Left */
1067 #define AIC_ACCR1_RS_SLOT6        (1 << 19)     /* Slot 6 valid bit, PCM Center */
1068 #define AIC_ACCR1_RS_SLOT5        (1 << 18)     /* Slot 5 valid bit */
1069 #define AIC_ACCR1_RS_SLOT4        (1 << 17)     /* Slot 4 valid bit, PCM Right */
1070 #define AIC_ACCR1_RS_SLOT3        (1 << 16)     /* Slot 3 valid bit, PCM Left */
1071 #define AIC_ACCR1_XS_BIT        0       /* Transmit Valid Slots */
1072 #define AIC_ACCR1_XS_MASK       (0x3ff << AIC_ACCR1_XS_BIT)
1073 #define AIC_ACCR1_XS_SLOT12       (1 << 9)      /* Slot 12 valid bit */
1074 #define AIC_ACCR1_XS_SLOT11       (1 << 8)      /* Slot 11 valid bit */
1075 #define AIC_ACCR1_XS_SLOT10       (1 << 7)      /* Slot 10 valid bit */
1076 #define AIC_ACCR1_XS_SLOT9        (1 << 6)      /* Slot 9 valid bit, LFE */
1077 #define AIC_ACCR1_XS_SLOT8        (1 << 5)      /* Slot 8 valid bit, Surround Right */
1078 #define AIC_ACCR1_XS_SLOT7        (1 << 4)      /* Slot 7 valid bit, Surround Left */
1079 #define AIC_ACCR1_XS_SLOT6        (1 << 3)      /* Slot 6 valid bit, PCM Center */
1080 #define AIC_ACCR1_XS_SLOT5        (1 << 2)      /* Slot 5 valid bit */
1081 #define AIC_ACCR1_XS_SLOT4        (1 << 1)      /* Slot 4 valid bit, PCM Right */
1082 #define AIC_ACCR1_XS_SLOT3        (1 << 0)      /* Slot 3 valid bit, PCM Left */
1083
1084 /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1085
1086 #define AIC_ACCR2_ERSTO         (1 << 18)       /* Enable RSTO interrupt */
1087 #define AIC_ACCR2_ESADR         (1 << 17)       /* Enable SADR interrupt */
1088 #define AIC_ACCR2_ECADT         (1 << 16)       /* Enable CADT interrupt */
1089 #define AIC_ACCR2_OASS_BIT      8       /* Output Sample Size for AC-link */
1090 #define AIC_ACCR2_OASS_MASK     (0x3 << AIC_ACCR2_OASS_BIT)
1091 #define AIC_ACCR2_OASS_20BIT      (0 << AIC_ACCR2_OASS_BIT)     /* Output Audio Sample Size is 20-bit */
1092 #define AIC_ACCR2_OASS_18BIT      (1 << AIC_ACCR2_OASS_BIT)     /* Output Audio Sample Size is 18-bit */
1093 #define AIC_ACCR2_OASS_16BIT      (2 << AIC_ACCR2_OASS_BIT)     /* Output Audio Sample Size is 16-bit */
1094 #define AIC_ACCR2_OASS_8BIT       (3 << AIC_ACCR2_OASS_BIT)     /* Output Audio Sample Size is 8-bit */
1095 #define AIC_ACCR2_IASS_BIT      6       /* Output Sample Size for AC-link */
1096 #define AIC_ACCR2_IASS_MASK     (0x3 << AIC_ACCR2_IASS_BIT)
1097 #define AIC_ACCR2_IASS_20BIT      (0 << AIC_ACCR2_IASS_BIT)     /* Input Audio Sample Size is 20-bit */
1098 #define AIC_ACCR2_IASS_18BIT      (1 << AIC_ACCR2_IASS_BIT)     /* Input Audio Sample Size is 18-bit */
1099 #define AIC_ACCR2_IASS_16BIT      (2 << AIC_ACCR2_IASS_BIT)     /* Input Audio Sample Size is 16-bit */
1100 #define AIC_ACCR2_IASS_8BIT       (3 << AIC_ACCR2_IASS_BIT)     /* Input Audio Sample Size is 8-bit */
1101 #define AIC_ACCR2_SO            (1 << 3)        /* SDATA_OUT output value */
1102 #define AIC_ACCR2_SR            (1 << 2)        /* RESET# pin level */
1103 #define AIC_ACCR2_SS            (1 << 1)        /* SYNC pin level */
1104 #define AIC_ACCR2_SA            (1 << 0)        /* SYNC and SDATA_OUT alternation */
1105
1106 /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1107
1108 #define AIC_I2SCR_STPBK         (1 << 12)       /* Stop BIT_CLK for I2S/MSB-justified */
1109 #define AIC_I2SCR_WL_BIT        1       /* Input/Output Sample Size for I2S/MSB-justified */
1110 #define AIC_I2SCR_WL_MASK       (0x7 << AIC_I2SCR_WL_BIT)
1111 #define AIC_I2SCR_WL_24BIT        (0 << AIC_I2SCR_WL_BIT)       /* Word Length is 24 bit */
1112 #define AIC_I2SCR_WL_20BIT        (1 << AIC_I2SCR_WL_BIT)       /* Word Length is 20 bit */
1113 #define AIC_I2SCR_WL_18BIT        (2 << AIC_I2SCR_WL_BIT)       /* Word Length is 18 bit */
1114 #define AIC_I2SCR_WL_16BIT        (3 << AIC_I2SCR_WL_BIT)       /* Word Length is 16 bit */
1115 #define AIC_I2SCR_WL_8BIT         (4 << AIC_I2SCR_WL_BIT)       /* Word Length is 8 bit */
1116 #define AIC_I2SCR_AMSL          (1 << 0)        /* 0:I2S, 1:MSB-justified */
1117
1118 /* AIC Controller FIFO Status Register (AIC_SR) */
1119
1120 #define AIC_SR_RFL_BIT          24      /* Receive FIFO Level */
1121 #define AIC_SR_RFL_MASK         (0x3f << AIC_SR_RFL_BIT)
1122 #define AIC_SR_TFL_BIT          8       /* Transmit FIFO level */
1123 #define AIC_SR_TFL_MASK         (0x3f << AIC_SR_TFL_BIT)
1124 #define AIC_SR_ROR              (1 << 6)        /* Receive FIFO Overrun */
1125 #define AIC_SR_TUR              (1 << 5)        /* Transmit FIFO Underrun */
1126 #define AIC_SR_RFS              (1 << 4)        /* Receive FIFO Service Request */
1127 #define AIC_SR_TFS              (1 << 3)        /* Transmit FIFO Service Request */
1128
1129 /* AIC Controller AC-link Status Register (AIC_ACSR) */
1130
1131 #define AIC_ACSR_SLTERR         (1 << 21)       /* Slot Error Flag */
1132 #define AIC_ACSR_CRDY           (1 << 20)       /* External CODEC Ready Flag */
1133 #define AIC_ACSR_CLPM           (1 << 19)       /* External CODEC low power mode flag */
1134 #define AIC_ACSR_RSTO           (1 << 18)       /* External CODEC regs read status timeout */
1135 #define AIC_ACSR_SADR           (1 << 17)       /* External CODEC regs status addr and data received */
1136 #define AIC_ACSR_CADT           (1 << 16)       /* Command Address and Data Transmitted */
1137
1138 /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1139
1140 #define AIC_I2SSR_BSY           (1 << 2)        /* AIC Busy in I2S/MSB-justified format */
1141
1142 /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1143
1144 #define AIC_ACCAR_CAR_BIT       0
1145 #define AIC_ACCAR_CAR_MASK      (0xfffff << AIC_ACCAR_CAR_BIT)
1146
1147 /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1148
1149 #define AIC_ACCDR_CDR_BIT       0
1150 #define AIC_ACCDR_CDR_MASK      (0xfffff << AIC_ACCDR_CDR_BIT)
1151
1152 /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1153
1154 #define AIC_ACSAR_SAR_BIT       0
1155 #define AIC_ACSAR_SAR_MASK      (0xfffff << AIC_ACSAR_SAR_BIT)
1156
1157 /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1158
1159 #define AIC_ACSDR_SDR_BIT       0
1160 #define AIC_ACSDR_SDR_MASK      (0xfffff << AIC_ACSDR_SDR_BIT)
1161
1162 /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1163
1164 #define AIC_I2SDIV_DIV_BIT      0
1165 #define AIC_I2SDIV_DIV_MASK     (0x7f << AIC_I2SDIV_DIV_BIT)
1166 #define AIC_I2SDIV_BITCLK_3072KHZ       (0x0C << AIC_I2SDIV_DIV_BIT)    /* BIT_CLK of 3.072MHz */
1167 #define AIC_I2SDIV_BITCLK_2836KHZ       (0x0D << AIC_I2SDIV_DIV_BIT)    /* BIT_CLK of 2.836MHz */
1168 #define AIC_I2SDIV_BITCLK_1418KHZ       (0x1A << AIC_I2SDIV_DIV_BIT)    /* BIT_CLK of 1.418MHz */
1169 #define AIC_I2SDIV_BITCLK_1024KHZ       (0x24 << AIC_I2SDIV_DIV_BIT)    /* BIT_CLK of 1.024MHz */
1170 #define AIC_I2SDIV_BITCLK_7089KHZ       (0x34 << AIC_I2SDIV_DIV_BIT)    /* BIT_CLK of 708.92KHz */
1171 #define AIC_I2SDIV_BITCLK_512KHZ        (0x48 << AIC_I2SDIV_DIV_BIT)    /* BIT_CLK of 512.00KHz */
1172
1173
1174 /*************************************************************************
1175  * ICDC (Internal CODEC)
1176  *************************************************************************/
1177 #define ICDC_CR                 (ICDC_BASE + 0x0400)    /* ICDC Control Register */
1178 #define ICDC_APWAIT             (ICDC_BASE + 0x0404)    /* Anti-Pop WAIT Stage Timing Control Register */
1179 #define ICDC_APPRE              (ICDC_BASE + 0x0408)    /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1180 #define ICDC_APHPEN             (ICDC_BASE + 0x040C)    /* Anti-Pop HPEN Stage Timing Control Register */
1181 #define ICDC_APSR               (ICDC_BASE + 0x0410)    /* Anti-Pop Status Register */
1182 #define ICDC_CDCCR1             (ICDC_BASE + 0x0080)
1183 #define ICDC_CDCCR2             (ICDC_BASE + 0x0084)
1184
1185 #define REG_ICDC_CR             REG32(ICDC_CR)
1186 #define REG_ICDC_APWAIT         REG32(ICDC_APWAIT)
1187 #define REG_ICDC_APPRE          REG32(ICDC_APPRE)
1188 #define REG_ICDC_APHPEN         REG32(ICDC_APHPEN)
1189 #define REG_ICDC_APSR           REG32(ICDC_APSR)
1190 #define REG_ICDC_CDCCR1         REG32(ICDC_CDCCR1)
1191 #define REG_ICDC_CDCCR2         REG32(ICDC_CDCCR2)
1192
1193 /* ICDC Control Register */
1194 #define ICDC_CR_LINVOL_BIT      24      /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1195 #define ICDC_CR_LINVOL_MASK     (0x1f << ICDC_CR_LINVOL_BIT)
1196 #define ICDC_CR_ASRATE_BIT      20      /* Audio Sample Rate */
1197 #define ICDC_CR_ASRATE_MASK     (0x0f << ICDC_CR_ASRATE_BIT)
1198 #define ICDC_CR_ASRATE_8000     (0x0 << ICDC_CR_ASRATE_BIT)
1199 #define ICDC_CR_ASRATE_11025    (0x1 << ICDC_CR_ASRATE_BIT)
1200 #define ICDC_CR_ASRATE_12000    (0x2 << ICDC_CR_ASRATE_BIT)
1201 #define ICDC_CR_ASRATE_16000    (0x3 << ICDC_CR_ASRATE_BIT)
1202 #define ICDC_CR_ASRATE_22050    (0x4 << ICDC_CR_ASRATE_BIT)
1203 #define ICDC_CR_ASRATE_24000    (0x5 << ICDC_CR_ASRATE_BIT)
1204 #define ICDC_CR_ASRATE_32000    (0x6 << ICDC_CR_ASRATE_BIT)
1205 #define ICDC_CR_ASRATE_44100    (0x7 << ICDC_CR_ASRATE_BIT)
1206 #define ICDC_CR_ASRATE_48000    (0x8 << ICDC_CR_ASRATE_BIT)
1207 #define ICDC_CR_MICBG_BIT       18      /* MIC Boost Gain */
1208 #define ICDC_CR_MICBG_MASK      (0x3 << ICDC_CR_MICBG_BIT)
1209 #define ICDC_CR_MICBG_0DB       (0x0 << ICDC_CR_MICBG_BIT)
1210 #define ICDC_CR_MICBG_6DB       (0x1 << ICDC_CR_MICBG_BIT)
1211 #define ICDC_CR_MICBG_12DB      (0x2 << ICDC_CR_MICBG_BIT)
1212 #define ICDC_CR_MICBG_20DB      (0x3 << ICDC_CR_MICBG_BIT)
1213 #define ICDC_CR_HPVOL_BIT       16      /* Headphone Volume Gain */
1214 #define ICDC_CR_HPVOL_MASK      (0x3 << ICDC_CR_HPVOL_BIT)
1215 #define ICDC_CR_HPVOL_0DB       (0x0 << ICDC_CR_HPVOL_BIT)
1216 #define ICDC_CR_HPVOL_2DB       (0x1 << ICDC_CR_HPVOL_BIT)
1217 #define ICDC_CR_HPVOL_4DB       (0x2 << ICDC_CR_HPVOL_BIT)
1218 #define ICDC_CR_HPVOL_6DB       (0x3 << ICDC_CR_HPVOL_BIT)
1219 #define ICDC_CR_ELINEIN         (1 << 13)       /* Enable LINE Input */
1220 #define ICDC_CR_EMIC            (1 << 12)       /* Enable MIC Input */
1221 #define ICDC_CR_SW1ON           (1 << 11)       /* Switch 1 in CODEC is on */
1222 #define ICDC_CR_EADC            (1 << 10)       /* Enable ADC */
1223 #define ICDC_CR_SW2ON           (1 << 9)        /* Switch 2 in CODEC is on */
1224 #define ICDC_CR_EDAC            (1 << 8)        /* Enable DAC */
1225 #define ICDC_CR_HPMUTE          (1 << 5)        /* Headphone Mute */
1226 #define ICDC_CR_HPTON           (1 << 4)        /* Headphone Amplifier Trun On */
1227 #define ICDC_CR_HPTOFF          (1 << 3)        /* Headphone Amplifier Trun Off */
1228 #define ICDC_CR_TAAP            (1 << 2)        /* Turn Around of the Anti-Pop Procedure */
1229 #define ICDC_CR_EAP             (1 << 1)        /* Enable Anti-Pop Procedure */
1230 #define ICDC_CR_SUSPD           (1 << 0)        /* CODEC Suspend */
1231
1232 /* Anti-Pop WAIT Stage Timing Control Register */
1233 #define ICDC_APWAIT_WAITSN_BIT  0
1234 #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1235
1236 /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1237 #define ICDC_APPRE_PRESN_BIT    0
1238 #define ICDC_APPRE_PRESN_MASK   (0x1ff << ICDC_APPRE_PRESN_BIT)
1239
1240 /* Anti-Pop HPEN Stage Timing Control Register */
1241 #define ICDC_APHPEN_HPENSN_BIT  0
1242 #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1243
1244 /* Anti-Pop Status Register */
1245 #define ICDC_SR_HPST_BIT        14      /* Headphone Amplifier State */
1246 #define ICDC_SR_HPST_MASK       (0x7 << ICDC_SR_HPST_BIT)
1247 #define ICDC_SR_HPST_HP_OFF      (0x0 << ICDC_SR_HPST_BIT)      /* HP amplifier is off */
1248 #define ICDC_SR_HPST_TON_WAIT    (0x1 << ICDC_SR_HPST_BIT)      /* wait state in turn-on */
1249 #define ICDC_SR_HPST_TON_PRE     (0x2 << ICDC_SR_HPST_BIT)      /* pre-enable state in turn-on */
1250 #define ICDC_SR_HPST_TON_HPEN    (0x3 << ICDC_SR_HPST_BIT)      /* HP enable state in turn-on */
1251 #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT)        /* HP enable state in turn-off */
1252 #define ICDC_SR_HPST_TOFF_PRE  (0x5 << ICDC_SR_HPST_BIT)        /* pre-enable state in turn-off */
1253 #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT)        /* wait state in turn-off */
1254 #define ICDC_SR_HPST_HP_ON       (0x7 << ICDC_SR_HPST_BIT)      /* HP amplifier is on */
1255 #define ICDC_SR_SNCNT_BIT       0       /* Sample Number Counter */
1256 #define ICDC_SR_SNCNT_MASK      (0x3fff << ICDC_SR_SNCNT_BIT)
1257
1258
1259 /*************************************************************************
1260  * I2C
1261  *************************************************************************/
1262 #define I2C_DR                  (I2C_BASE + 0x000)
1263 #define I2C_CR                  (I2C_BASE + 0x004)
1264 #define I2C_SR                  (I2C_BASE + 0x008)
1265 #define I2C_GR                  (I2C_BASE + 0x00C)
1266
1267 #define REG_I2C_DR              REG8(I2C_DR)
1268 #define REG_I2C_CR              REG8(I2C_CR)
1269 #define REG_I2C_SR              REG8(I2C_SR)
1270 #define REG_I2C_GR              REG16(I2C_GR)
1271
1272 /* I2C Control Register (I2C_CR) */
1273
1274 #define I2C_CR_IEN              (1 << 4)
1275 #define I2C_CR_STA              (1 << 3)
1276 #define I2C_CR_STO              (1 << 2)
1277 #define I2C_CR_AC               (1 << 1)
1278 #define I2C_CR_I2CE             (1 << 0)
1279
1280 /* I2C Status Register (I2C_SR) */
1281
1282 #define I2C_SR_STX              (1 << 4)
1283 #define I2C_SR_BUSY             (1 << 3)
1284 #define I2C_SR_TEND             (1 << 2)
1285 #define I2C_SR_DRF              (1 << 1)
1286 #define I2C_SR_ACKF             (1 << 0)
1287
1288
1289 /*************************************************************************
1290  * SSI
1291  *************************************************************************/
1292 #define SSI_DR                  (SSI_BASE + 0x000)
1293 #define SSI_CR0                 (SSI_BASE + 0x004)
1294 #define SSI_CR1                 (SSI_BASE + 0x008)
1295 #define SSI_SR                  (SSI_BASE + 0x00C)
1296 #define SSI_ITR                 (SSI_BASE + 0x010)
1297 #define SSI_ICR                 (SSI_BASE + 0x014)
1298 #define SSI_GR                  (SSI_BASE + 0x018)
1299
1300 #define REG_SSI_DR              REG32(SSI_DR)
1301 #define REG_SSI_CR0             REG16(SSI_CR0)
1302 #define REG_SSI_CR1             REG32(SSI_CR1)
1303 #define REG_SSI_SR              REG32(SSI_SR)
1304 #define REG_SSI_ITR             REG16(SSI_ITR)
1305 #define REG_SSI_ICR             REG8(SSI_ICR)
1306 #define REG_SSI_GR              REG16(SSI_GR)
1307
1308 /* SSI Data Register (SSI_DR) */
1309
1310 #define SSI_DR_GPC_BIT          0
1311 #define SSI_DR_GPC_MASK         (0x1ff << SSI_DR_GPC_BIT)
1312
1313 /* SSI Control Register 0 (SSI_CR0) */
1314
1315 #define SSI_CR0_SSIE            (1 << 15)
1316 #define SSI_CR0_TIE             (1 << 14)
1317 #define SSI_CR0_RIE             (1 << 13)
1318 #define SSI_CR0_TEIE            (1 << 12)
1319 #define SSI_CR0_REIE            (1 << 11)
1320 #define SSI_CR0_LOOP            (1 << 10)
1321 #define SSI_CR0_RFINE           (1 << 9)
1322 #define SSI_CR0_RFINC           (1 << 8)
1323 #define SSI_CR0_FSEL            (1 << 6)
1324 #define SSI_CR0_TFLUSH          (1 << 2)
1325 #define SSI_CR0_RFLUSH          (1 << 1)
1326 #define SSI_CR0_DISREV          (1 << 0)
1327
1328 /* SSI Control Register 1 (SSI_CR1) */
1329
1330 #define SSI_CR1_FRMHL_BIT       30
1331 #define SSI_CR1_FRMHL_MASK      (0x3 << SSI_CR1_FRMHL_BIT)
1332 #define SSI_CR1_FRMHL_CELOW_CE2LOW      (0 << SSI_CR1_FRMHL_BIT)        /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1333 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW     (1 << SSI_CR1_FRMHL_BIT)        /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1334 #define SSI_CR1_FRMHL_CELOW_CE2HIGH     (2 << SSI_CR1_FRMHL_BIT)        /* SSI_CE_ is low valid  and SSI_CE2_ is high valid */
1335 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH    (3 << SSI_CR1_FRMHL_BIT)        /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1336 #define SSI_CR1_TFVCK_BIT       28
1337 #define SSI_CR1_TFVCK_MASK      (0x3 << SSI_CR1_TFVCK_BIT)
1338 #define SSI_CR1_TFVCK_0   (0 << SSI_CR1_TFVCK_BIT)
1339 #define SSI_CR1_TFVCK_1   (1 << SSI_CR1_TFVCK_BIT)
1340 #define SSI_CR1_TFVCK_2   (2 << SSI_CR1_TFVCK_BIT)
1341 #define SSI_CR1_TFVCK_3   (3 << SSI_CR1_TFVCK_BIT)
1342 #define SSI_CR1_TCKFI_BIT       26
1343 #define SSI_CR1_TCKFI_MASK      (0x3 << SSI_CR1_TCKFI_BIT)
1344 #define SSI_CR1_TCKFI_0   (0 << SSI_CR1_TCKFI_BIT)
1345 #define SSI_CR1_TCKFI_1   (1 << SSI_CR1_TCKFI_BIT)
1346 #define SSI_CR1_TCKFI_2   (2 << SSI_CR1_TCKFI_BIT)
1347 #define SSI_CR1_TCKFI_3   (3 << SSI_CR1_TCKFI_BIT)
1348 #define SSI_CR1_LFST            (1 << 25)
1349 #define SSI_CR1_ITFRM           (1 << 24)
1350 #define SSI_CR1_UNFIN           (1 << 23)
1351 #define SSI_CR1_MULTS           (1 << 22)
1352 #define SSI_CR1_FMAT_BIT        20
1353 #define SSI_CR1_FMAT_MASK       (0x3 << SSI_CR1_FMAT_BIT)
1354 #define SSI_CR1_FMAT_SPI          (0 << SSI_CR1_FMAT_BIT)       /* Motorola¡¯s SPI format */
1355 #define SSI_CR1_FMAT_SSP          (1 << SSI_CR1_FMAT_BIT)       /* TI's SSP format */
1356 #define SSI_CR1_FMAT_MW1          (2 << SSI_CR1_FMAT_BIT)       /* National Microwire 1 format */
1357 #define SSI_CR1_FMAT_MW2          (3 << SSI_CR1_FMAT_BIT)       /* National Microwire 2 format */
1358 #define SSI_CR1_TTRG_BIT        16
1359 #define SSI_CR1_TTRG_MASK       (0xf << SSI_CR1_TTRG_BIT)
1360 #define SSI_CR1_TTRG_1    (0 << SSI_CR1_TTRG_BIT)
1361 #define SSI_CR1_TTRG_8    (1 << SSI_CR1_TTRG_BIT)
1362 #define SSI_CR1_TTRG_16   (2 << SSI_CR1_TTRG_BIT)
1363 #define SSI_CR1_TTRG_24   (3 << SSI_CR1_TTRG_BIT)
1364 #define SSI_CR1_TTRG_32   (4 << SSI_CR1_TTRG_BIT)
1365 #define SSI_CR1_TTRG_40   (5 << SSI_CR1_TTRG_BIT)
1366 #define SSI_CR1_TTRG_48   (6 << SSI_CR1_TTRG_BIT)
1367 #define SSI_CR1_TTRG_56   (7 << SSI_CR1_TTRG_BIT)
1368 #define SSI_CR1_TTRG_64   (8 << SSI_CR1_TTRG_BIT)
1369 #define SSI_CR1_TTRG_72   (9 << SSI_CR1_TTRG_BIT)
1370 #define SSI_CR1_TTRG_80   (10<< SSI_CR1_TTRG_BIT)
1371 #define SSI_CR1_TTRG_88   (11<< SSI_CR1_TTRG_BIT)
1372 #define SSI_CR1_TTRG_96   (12<< SSI_CR1_TTRG_BIT)
1373 #define SSI_CR1_TTRG_104          (13<< SSI_CR1_TTRG_BIT)
1374 #define SSI_CR1_TTRG_112          (14<< SSI_CR1_TTRG_BIT)
1375 #define SSI_CR1_TTRG_120          (15<< SSI_CR1_TTRG_BIT)
1376 #define SSI_CR1_MCOM_BIT        12
1377 #define SSI_CR1_MCOM_MASK       (0xf << SSI_CR1_MCOM_BIT)
1378 #define SSI_CR1_MCOM_1BIT         (0x0 << SSI_CR1_MCOM_BIT)     /* 1-bit command selected */
1379 #define SSI_CR1_MCOM_2BIT         (0x1 << SSI_CR1_MCOM_BIT)     /* 2-bit command selected */
1380 #define SSI_CR1_MCOM_3BIT         (0x2 << SSI_CR1_MCOM_BIT)     /* 3-bit command selected */
1381 #define SSI_CR1_MCOM_4BIT         (0x3 << SSI_CR1_MCOM_BIT)     /* 4-bit command selected */
1382 #define SSI_CR1_MCOM_5BIT         (0x4 << SSI_CR1_MCOM_BIT)     /* 5-bit command selected */
1383 #define SSI_CR1_MCOM_6BIT         (0x5 << SSI_CR1_MCOM_BIT)     /* 6-bit command selected */
1384 #define SSI_CR1_MCOM_7BIT         (0x6 << SSI_CR1_MCOM_BIT)     /* 7-bit command selected */
1385 #define SSI_CR1_MCOM_8BIT         (0x7 << SSI_CR1_MCOM_BIT)     /* 8-bit command selected */
1386 #define SSI_CR1_MCOM_9BIT         (0x8 << SSI_CR1_MCOM_BIT)     /* 9-bit command selected */
1387 #define SSI_CR1_MCOM_10BIT        (0x9 << SSI_CR1_MCOM_BIT)     /* 10-bit command selected */
1388 #define SSI_CR1_MCOM_11BIT        (0xA << SSI_CR1_MCOM_BIT)     /* 11-bit command selected */
1389 #define SSI_CR1_MCOM_12BIT        (0xB << SSI_CR1_MCOM_BIT)     /* 12-bit command selected */
1390 #define SSI_CR1_MCOM_13BIT        (0xC << SSI_CR1_MCOM_BIT)     /* 13-bit command selected */
1391 #define SSI_CR1_MCOM_14BIT        (0xD << SSI_CR1_MCOM_BIT)     /* 14-bit command selected */
1392 #define SSI_CR1_MCOM_15BIT        (0xE << SSI_CR1_MCOM_BIT)     /* 15-bit command selected */
1393 #define SSI_CR1_MCOM_16BIT        (0xF << SSI_CR1_MCOM_BIT)     /* 16-bit command selected */
1394 #define SSI_CR1_RTRG_BIT        8
1395 #define SSI_CR1_RTRG_MASK       (0xf << SSI_CR1_RTRG_BIT)
1396 #define SSI_CR1_RTRG_1    (0 << SSI_CR1_RTRG_BIT)
1397 #define SSI_CR1_RTRG_8    (1 << SSI_CR1_RTRG_BIT)
1398 #define SSI_CR1_RTRG_16   (2 << SSI_CR1_RTRG_BIT)
1399 #define SSI_CR1_RTRG_24   (3 << SSI_CR1_RTRG_BIT)
1400 #define SSI_CR1_RTRG_32   (4 << SSI_CR1_RTRG_BIT)
1401 #define SSI_CR1_RTRG_40   (5 << SSI_CR1_RTRG_BIT)
1402 #define SSI_CR1_RTRG_48   (6 << SSI_CR1_RTRG_BIT)
1403 #define SSI_CR1_RTRG_56   (7 << SSI_CR1_RTRG_BIT)
1404 #define SSI_CR1_RTRG_64   (8 << SSI_CR1_RTRG_BIT)
1405 #define SSI_CR1_RTRG_72   (9 << SSI_CR1_RTRG_BIT)
1406 #define SSI_CR1_RTRG_80   (10<< SSI_CR1_RTRG_BIT)
1407 #define SSI_CR1_RTRG_88   (11<< SSI_CR1_RTRG_BIT)
1408 #define SSI_CR1_RTRG_96   (12<< SSI_CR1_RTRG_BIT)
1409 #define SSI_CR1_RTRG_104          (13<< SSI_CR1_RTRG_BIT)
1410 #define SSI_CR1_RTRG_112          (14<< SSI_CR1_RTRG_BIT)
1411 #define SSI_CR1_RTRG_120          (15<< SSI_CR1_RTRG_BIT)
1412 #define SSI_CR1_FLEN_BIT        4
1413 #define SSI_CR1_FLEN_MASK       (0xf << SSI_CR1_FLEN_BIT)
1414 #define SSI_CR1_FLEN_2BIT         (0x0 << SSI_CR1_FLEN_BIT)
1415 #define SSI_CR1_FLEN_3BIT         (0x1 << SSI_CR1_FLEN_BIT)
1416 #define SSI_CR1_FLEN_4BIT         (0x2 << SSI_CR1_FLEN_BIT)
1417 #define SSI_CR1_FLEN_5BIT         (0x3 << SSI_CR1_FLEN_BIT)
1418 #define SSI_CR1_FLEN_6BIT         (0x4 << SSI_CR1_FLEN_BIT)
1419 #define SSI_CR1_FLEN_7BIT         (0x5 << SSI_CR1_FLEN_BIT)
1420 #define SSI_CR1_FLEN_8BIT         (0x6 << SSI_CR1_FLEN_BIT)
1421 #define SSI_CR1_FLEN_9BIT         (0x7 << SSI_CR1_FLEN_BIT)
1422 #define SSI_CR1_FLEN_10BIT        (0x8 << SSI_CR1_FLEN_BIT)
1423 #define SSI_CR1_FLEN_11BIT        (0x9 << SSI_CR1_FLEN_BIT)
1424 #define SSI_CR1_FLEN_12BIT        (0xA << SSI_CR1_FLEN_BIT)
1425 #define SSI_CR1_FLEN_13BIT        (0xB << SSI_CR1_FLEN_BIT)
1426 #define SSI_CR1_FLEN_14BIT        (0xC << SSI_CR1_FLEN_BIT)
1427 #define SSI_CR1_FLEN_15BIT        (0xD << SSI_CR1_FLEN_BIT)
1428 #define SSI_CR1_FLEN_16BIT        (0xE << SSI_CR1_FLEN_BIT)
1429 #define SSI_CR1_FLEN_17BIT        (0xF << SSI_CR1_FLEN_BIT)
1430 #define SSI_CR1_PHA             (1 << 1)
1431 #define SSI_CR1_POL             (1 << 0)
1432
1433 /* SSI Status Register (SSI_SR) */
1434
1435 #define SSI_SR_TFIFONUM_BIT     16
1436 #define SSI_SR_TFIFONUM_MASK    (0xff << SSI_SR_TFIFONUM_BIT)
1437 #define SSI_SR_RFIFONUM_BIT     8
1438 #define SSI_SR_RFIFONUM_MASK    (0xff << SSI_SR_RFIFONUM_BIT)
1439 #define SSI_SR_END              (1 << 7)
1440 #define SSI_SR_BUSY             (1 << 6)
1441 #define SSI_SR_TFF              (1 << 5)
1442 #define SSI_SR_RFE              (1 << 4)
1443 #define SSI_SR_TFHE             (1 << 3)
1444 #define SSI_SR_RFHF             (1 << 2)
1445 #define SSI_SR_UNDR             (1 << 1)
1446 #define SSI_SR_OVER             (1 << 0)
1447
1448 /* SSI Interval Time Control Register (SSI_ITR) */
1449
1450 #define SSI_ITR_CNTCLK          (1 << 15)
1451 #define SSI_ITR_IVLTM_BIT       0
1452 #define SSI_ITR_IVLTM_MASK      (0x7fff << SSI_ITR_IVLTM_BIT)
1453
1454
1455 /*************************************************************************
1456  * MSC
1457  *************************************************************************/
1458 #define MSC_STRPCL              (MSC_BASE + 0x000)
1459 #define MSC_STAT                (MSC_BASE + 0x004)
1460 #define MSC_CLKRT               (MSC_BASE + 0x008)
1461 #define MSC_CMDAT               (MSC_BASE + 0x00C)
1462 #define MSC_RESTO               (MSC_BASE + 0x010)
1463 #define MSC_RDTO                (MSC_BASE + 0x014)
1464 #define MSC_BLKLEN              (MSC_BASE + 0x018)
1465 #define MSC_NOB                 (MSC_BASE + 0x01C)
1466 #define MSC_SNOB                (MSC_BASE + 0x020)
1467 #define MSC_IMASK               (MSC_BASE + 0x024)
1468 #define MSC_IREG                (MSC_BASE + 0x028)
1469 #define MSC_CMD                 (MSC_BASE + 0x02C)
1470 #define MSC_ARG                 (MSC_BASE + 0x030)
1471 #define MSC_RES                 (MSC_BASE + 0x034)
1472 #define MSC_RXFIFO              (MSC_BASE + 0x038)
1473 #define MSC_TXFIFO              (MSC_BASE + 0x03C)
1474
1475 #define REG_MSC_STRPCL          REG16(MSC_STRPCL)
1476 #define REG_MSC_STAT            REG32(MSC_STAT)
1477 #define REG_MSC_CLKRT           REG16(MSC_CLKRT)
1478 #define REG_MSC_CMDAT           REG32(MSC_CMDAT)
1479 #define REG_MSC_RESTO           REG16(MSC_RESTO)
1480 #define REG_MSC_RDTO            REG16(MSC_RDTO)
1481 #define REG_MSC_BLKLEN          REG16(MSC_BLKLEN)
1482 #define REG_MSC_NOB             REG16(MSC_NOB)
1483 #define REG_MSC_SNOB            REG16(MSC_SNOB)
1484 #define REG_MSC_IMASK           REG16(MSC_IMASK)
1485 #define REG_MSC_IREG            REG16(MSC_IREG)
1486 #define REG_MSC_CMD             REG8(MSC_CMD)
1487 #define REG_MSC_ARG             REG32(MSC_ARG)
1488 #define REG_MSC_RES             REG16(MSC_RES)
1489 #define REG_MSC_RXFIFO          REG32(MSC_RXFIFO)
1490 #define REG_MSC_TXFIFO          REG32(MSC_TXFIFO)
1491
1492 /* MSC Clock and Control Register (MSC_STRPCL) */
1493
1494 #define MSC_STRPCL_EXIT_MULTIPLE        (1 << 7)
1495 #define MSC_STRPCL_EXIT_TRANSFER        (1 << 6)
1496 #define MSC_STRPCL_START_READWAIT       (1 << 5)
1497 #define MSC_STRPCL_STOP_READWAIT        (1 << 4)
1498 #define MSC_STRPCL_RESET                (1 << 3)
1499 #define MSC_STRPCL_START_OP             (1 << 2)
1500 #define MSC_STRPCL_CLOCK_CONTROL_BIT    0
1501 #define MSC_STRPCL_CLOCK_CONTROL_MASK   (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1502 #define MSC_STRPCL_CLOCK_CONTROL_STOP     (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1503 #define MSC_STRPCL_CLOCK_CONTROL_START  (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT)   /* Start MMC/SD clock */
1504
1505 /* MSC Status Register (MSC_STAT) */
1506
1507 #define MSC_STAT_IS_RESETTING           (1 << 15)
1508 #define MSC_STAT_SDIO_INT_ACTIVE        (1 << 14)
1509 #define MSC_STAT_PRG_DONE               (1 << 13)
1510 #define MSC_STAT_DATA_TRAN_DONE         (1 << 12)
1511 #define MSC_STAT_END_CMD_RES            (1 << 11)
1512 #define MSC_STAT_DATA_FIFO_AFULL        (1 << 10)
1513 #define MSC_STAT_IS_READWAIT            (1 << 9)
1514 #define MSC_STAT_CLK_EN                 (1 << 8)
1515 #define MSC_STAT_DATA_FIFO_FULL         (1 << 7)
1516 #define MSC_STAT_DATA_FIFO_EMPTY        (1 << 6)
1517 #define MSC_STAT_CRC_RES_ERR            (1 << 5)
1518 #define MSC_STAT_CRC_READ_ERROR         (1 << 4)
1519 #define MSC_STAT_CRC_WRITE_ERROR_BIT    2
1520 #define MSC_STAT_CRC_WRITE_ERROR_MASK   (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1521 #define MSC_STAT_CRC_WRITE_ERROR_NO             (0 << MSC_STAT_CRC_WRITE_ERROR_BIT)     /* No error on transmission of data */
1522 #define MSC_STAT_CRC_WRITE_ERROR                (1 << MSC_STAT_CRC_WRITE_ERROR_BIT)     /* Card observed erroneous transmission of data */
1523 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS  (2 << MSC_STAT_CRC_WRITE_ERROR_BIT)     /* No CRC status is sent back */
1524 #define MSC_STAT_TIME_OUT_RES           (1 << 1)
1525 #define MSC_STAT_TIME_OUT_READ          (1 << 0)
1526
1527 /* MSC Bus Clock Control Register (MSC_CLKRT) */
1528
1529 #define MSC_CLKRT_CLK_RATE_BIT          0
1530 #define MSC_CLKRT_CLK_RATE_MASK         (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1531 #define MSC_CLKRT_CLK_RATE_DIV_1          (0x0 << MSC_CLKRT_CLK_RATE_BIT)       /* CLK_SRC */
1532 #define MSC_CLKRT_CLK_RATE_DIV_2          (0x1 << MSC_CLKRT_CLK_RATE_BIT)       /* 1/2 of CLK_SRC */
1533 #define MSC_CLKRT_CLK_RATE_DIV_4          (0x2 << MSC_CLKRT_CLK_RATE_BIT)       /* 1/4 of CLK_SRC */
1534 #define MSC_CLKRT_CLK_RATE_DIV_8          (0x3 << MSC_CLKRT_CLK_RATE_BIT)       /* 1/8 of CLK_SRC */
1535 #define MSC_CLKRT_CLK_RATE_DIV_16         (0x4 << MSC_CLKRT_CLK_RATE_BIT)       /* 1/16 of CLK_SRC */
1536 #define MSC_CLKRT_CLK_RATE_DIV_32         (0x5 << MSC_CLKRT_CLK_RATE_BIT)       /* 1/32 of CLK_SRC */
1537 #define MSC_CLKRT_CLK_RATE_DIV_64         (0x6 << MSC_CLKRT_CLK_RATE_BIT)       /* 1/64 of CLK_SRC */
1538 #define MSC_CLKRT_CLK_RATE_DIV_128        (0x7 << MSC_CLKRT_CLK_RATE_BIT)       /* 1/128 of CLK_SRC */
1539
1540 /* MSC Command Sequence Control Register (MSC_CMDAT) */
1541
1542 #define MSC_CMDAT_IO_ABORT              (1 << 11)
1543 #define MSC_CMDAT_BUS_WIDTH_BIT         9
1544 #define MSC_CMDAT_BUS_WIDTH_MASK        (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1545 #define MSC_CMDAT_BUS_WIDTH_1BIT          (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)      /* 1-bit data bus */
1546 #define MSC_CMDAT_BUS_WIDTH_4BIT          (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)      /* 4-bit data bus */
1547 #define CMDAT_BUS_WIDTH1          (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1548 #define CMDAT_BUS_WIDTH4          (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1549 #define MSC_CMDAT_DMA_EN                (1 << 8)
1550 #define MSC_CMDAT_INIT                  (1 << 7)
1551 #define MSC_CMDAT_BUSY                  (1 << 6)
1552 #define MSC_CMDAT_STREAM_BLOCK          (1 << 5)
1553 #define MSC_CMDAT_WRITE                 (1 << 4)
1554 #define MSC_CMDAT_READ                  (0 << 4)
1555 #define MSC_CMDAT_DATA_EN               (1 << 3)
1556 #define MSC_CMDAT_RESPONSE_BIT  0
1557 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1558 #define MSC_CMDAT_RESPONSE_NONE  (0x0 << MSC_CMDAT_RESPONSE_BIT)        /* No response */
1559 #define MSC_CMDAT_RESPONSE_R1     (0x1 << MSC_CMDAT_RESPONSE_BIT)       /* Format R1 and R1b */
1560 #define MSC_CMDAT_RESPONSE_R2     (0x2 << MSC_CMDAT_RESPONSE_BIT)       /* Format R2 */
1561 #define MSC_CMDAT_RESPONSE_R3     (0x3 << MSC_CMDAT_RESPONSE_BIT)       /* Format R3 */
1562 #define MSC_CMDAT_RESPONSE_R4     (0x4 << MSC_CMDAT_RESPONSE_BIT)       /* Format R4 */
1563 #define MSC_CMDAT_RESPONSE_R5     (0x5 << MSC_CMDAT_RESPONSE_BIT)       /* Format R5 */
1564 #define MSC_CMDAT_RESPONSE_R6     (0x6 << MSC_CMDAT_RESPONSE_BIT)       /* Format R6 */
1565
1566 #define CMDAT_DMA_EN    (1 << 8)
1567 #define CMDAT_INIT      (1 << 7)
1568 #define CMDAT_BUSY      (1 << 6)
1569 #define CMDAT_STREAM    (1 << 5)
1570 #define CMDAT_WRITE     (1 << 4)
1571 #define CMDAT_DATA_EN   (1 << 3)
1572
1573 /* MSC Interrupts Mask Register (MSC_IMASK) */
1574
1575 #define MSC_IMASK_SDIO                  (1 << 7)
1576 #define MSC_IMASK_TXFIFO_WR_REQ         (1 << 6)
1577 #define MSC_IMASK_RXFIFO_RD_REQ         (1 << 5)
1578 #define MSC_IMASK_END_CMD_RES           (1 << 2)
1579 #define MSC_IMASK_PRG_DONE              (1 << 1)
1580 #define MSC_IMASK_DATA_TRAN_DONE        (1 << 0)
1581
1582
1583 /* MSC Interrupts Status Register (MSC_IREG) */
1584
1585 #define MSC_IREG_SDIO                   (1 << 7)
1586 #define MSC_IREG_TXFIFO_WR_REQ          (1 << 6)
1587 #define MSC_IREG_RXFIFO_RD_REQ          (1 << 5)
1588 #define MSC_IREG_END_CMD_RES            (1 << 2)
1589 #define MSC_IREG_PRG_DONE               (1 << 1)
1590 #define MSC_IREG_DATA_TRAN_DONE         (1 << 0)
1591
1592
1593 /*************************************************************************
1594  * EMC (External Memory Controller)
1595  *************************************************************************/
1596 #define EMC_BCR         (EMC_BASE + 0x0)        /* BCR */
1597
1598 #define EMC_SMCR0       (EMC_BASE + 0x10)       /* Static Memory Control Register 0 */
1599 #define EMC_SMCR1       (EMC_BASE + 0x14)       /* Static Memory Control Register 1 */
1600 #define EMC_SMCR2       (EMC_BASE + 0x18)       /* Static Memory Control Register 2 */
1601 #define EMC_SMCR3       (EMC_BASE + 0x1c)       /* Static Memory Control Register 3 */
1602 #define EMC_SMCR4       (EMC_BASE + 0x20)       /* Static Memory Control Register 4 */
1603 #define EMC_SACR0       (EMC_BASE + 0x30)       /* Static Memory Bank 0 Addr Config Reg */
1604 #define EMC_SACR1       (EMC_BASE + 0x34)       /* Static Memory Bank 1 Addr Config Reg */
1605 #define EMC_SACR2       (EMC_BASE + 0x38)       /* Static Memory Bank 2 Addr Config Reg */
1606 #define EMC_SACR3       (EMC_BASE + 0x3c)       /* Static Memory Bank 3 Addr Config Reg */
1607 #define EMC_SACR4       (EMC_BASE + 0x40)       /* Static Memory Bank 4 Addr Config Reg */
1608
1609 #define EMC_NFCSR       (EMC_BASE + 0x050)      /* NAND Flash Control/Status Register */
1610 #define EMC_NFECR       (EMC_BASE + 0x100)      /* NAND Flash ECC Control Register */
1611 #define EMC_NFECC       (EMC_BASE + 0x104)      /* NAND Flash ECC Data Register */
1612 #define EMC_NFPAR0      (EMC_BASE + 0x108)      /* NAND Flash RS Parity 0 Register */
1613 #define EMC_NFPAR1      (EMC_BASE + 0x10c)      /* NAND Flash RS Parity 1 Register */
1614 #define EMC_NFPAR2      (EMC_BASE + 0x110)      /* NAND Flash RS Parity 2 Register */
1615 #define EMC_NFINTS      (EMC_BASE + 0x114)      /* NAND Flash Interrupt Status Register */
1616 #define EMC_NFINTE      (EMC_BASE + 0x118)      /* NAND Flash Interrupt Enable Register */
1617 #define EMC_NFERR0      (EMC_BASE + 0x11c)      /* NAND Flash RS Error Report 0 Register */
1618 #define EMC_NFERR1      (EMC_BASE + 0x120)      /* NAND Flash RS Error Report 1 Register */
1619 #define EMC_NFERR2      (EMC_BASE + 0x124)      /* NAND Flash RS Error Report 2 Register */
1620 #define EMC_NFERR3      (EMC_BASE + 0x128)      /* NAND Flash RS Error Report 3 Register */
1621
1622 #define EMC_DMCR        (EMC_BASE + 0x80)       /* DRAM Control Register */
1623 #define EMC_RTCSR       (EMC_BASE + 0x84)       /* Refresh Time Control/Status Register */
1624 #define EMC_RTCNT       (EMC_BASE + 0x88)       /* Refresh Timer Counter */
1625 #define EMC_RTCOR       (EMC_BASE + 0x8c)       /* Refresh Time Constant Register */
1626 #define EMC_DMAR0       (EMC_BASE + 0x90)       /* SDRAM Bank 0 Addr Config Register */
1627 #define EMC_SDMR0       (EMC_BASE + 0xa000)     /* Mode Register of SDRAM bank 0 */
1628
1629 #define REG_EMC_BCR     REG32(EMC_BCR)
1630
1631 #define REG_EMC_SMCR0   REG32(EMC_SMCR0)
1632 #define REG_EMC_SMCR1   REG32(EMC_SMCR1)
1633 #define REG_EMC_SMCR2   REG32(EMC_SMCR2)
1634 #define REG_EMC_SMCR3   REG32(EMC_SMCR3)
1635 #define REG_EMC_SMCR4   REG32(EMC_SMCR4)
1636 #define REG_EMC_SACR0   REG32(EMC_SACR0)
1637 #define REG_EMC_SACR1   REG32(EMC_SACR1)
1638 #define REG_EMC_SACR2   REG32(EMC_SACR2)
1639 #define REG_EMC_SACR3   REG32(EMC_SACR3)
1640 #define REG_EMC_SACR4   REG32(EMC_SACR4)
1641
1642 #define REG_EMC_NFCSR   REG32(EMC_NFCSR)
1643 #define REG_EMC_NFECR   REG32(EMC_NFECR)
1644 #define REG_EMC_NFECC   REG32(EMC_NFECC)
1645 #define REG_EMC_NFPAR0  REG32(EMC_NFPAR0)
1646 #define REG_EMC_NFPAR1  REG32(EMC_NFPAR1)
1647 #define REG_EMC_NFPAR2  REG32(EMC_NFPAR2)
1648 #define REG_EMC_NFINTS  REG32(EMC_NFINTS)
1649 #define REG_EMC_NFINTE  REG32(EMC_NFINTE)
1650 #define REG_EMC_NFERR0  REG32(EMC_NFERR0)
1651 #define REG_EMC_NFERR1  REG32(EMC_NFERR1)
1652 #define REG_EMC_NFERR2  REG32(EMC_NFERR2)
1653 #define REG_EMC_NFERR3  REG32(EMC_NFERR3)
1654
1655 #define REG_EMC_DMCR    REG32(EMC_DMCR)
1656 #define REG_EMC_RTCSR   REG16(EMC_RTCSR)
1657 #define REG_EMC_RTCNT   REG16(EMC_RTCNT)
1658 #define REG_EMC_RTCOR   REG16(EMC_RTCOR)
1659 #define REG_EMC_DMAR0   REG32(EMC_DMAR0)
1660
1661 /* Static Memory Control Register */
1662 #define EMC_SMCR_STRV_BIT       24
1663 #define EMC_SMCR_STRV_MASK      (0x0f << EMC_SMCR_STRV_BIT)
1664 #define EMC_SMCR_TAW_BIT        20
1665 #define EMC_SMCR_TAW_MASK       (0x0f << EMC_SMCR_TAW_BIT)
1666 #define EMC_SMCR_TBP_BIT        16
1667 #define EMC_SMCR_TBP_MASK       (0x0f << EMC_SMCR_TBP_BIT)
1668 #define EMC_SMCR_TAH_BIT        12
1669 #define EMC_SMCR_TAH_MASK       (0x07 << EMC_SMCR_TAH_BIT)
1670 #define EMC_SMCR_TAS_BIT        8
1671 #define EMC_SMCR_TAS_MASK       (0x07 << EMC_SMCR_TAS_BIT)
1672 #define EMC_SMCR_BW_BIT         6
1673 #define EMC_SMCR_BW_MASK        (0x03 << EMC_SMCR_BW_BIT)
1674 #define EMC_SMCR_BW_8BIT        (0 << EMC_SMCR_BW_BIT)
1675 #define EMC_SMCR_BW_16BIT       (1 << EMC_SMCR_BW_BIT)
1676 #define EMC_SMCR_BW_32BIT       (2 << EMC_SMCR_BW_BIT)
1677 #define EMC_SMCR_BCM            (1 << 3)
1678 #define EMC_SMCR_BL_BIT         1
1679 #define EMC_SMCR_BL_MASK        (0x03 << EMC_SMCR_BL_BIT)
1680 #define EMC_SMCR_BL_4           (0 << EMC_SMCR_BL_BIT)
1681 #define EMC_SMCR_BL_8           (1 << EMC_SMCR_BL_BIT)
1682 #define EMC_SMCR_BL_16  (2 << EMC_SMCR_BL_BIT)
1683 #define EMC_SMCR_BL_32  (3 << EMC_SMCR_BL_BIT)
1684 #define EMC_SMCR_SMT            (1 << 0)
1685
1686 /* Static Memory Bank Addr Config Reg */
1687 #define EMC_SACR_BASE_BIT       8
1688 #define EMC_SACR_BASE_MASK      (0xff << EMC_SACR_BASE_BIT)
1689 #define EMC_SACR_MASK_BIT       0
1690 #define EMC_SACR_MASK_MASK      (0xff << EMC_SACR_MASK_BIT)
1691
1692 /* NAND Flash Control/Status Register */
1693 #define EMC_NFCSR_NFCE4         (1 << 7)        /* NAND Flash Enable */
1694 #define EMC_NFCSR_NFE4          (1 << 6)        /* NAND Flash FCE# Assertion Enable */
1695 #define EMC_NFCSR_NFCE3         (1 << 5)
1696 #define EMC_NFCSR_NFE3          (1 << 4)
1697 #define EMC_NFCSR_NFCE2         (1 << 3)
1698 #define EMC_NFCSR_NFE2          (1 << 2)
1699 #define EMC_NFCSR_NFCE1         (1 << 1)
1700 #define EMC_NFCSR_NFE1          (1 << 0)
1701
1702 /* NAND Flash ECC Control Register */
1703 #define EMC_NFECR_PRDY          (1 << 4)        /* Parity Ready */
1704 #define EMC_NFECR_RS_DECODING   (0 << 3)        /* RS is in decoding phase */
1705 #define EMC_NFECR_RS_ENCODING   (1 << 3)        /* RS is in encoding phase */
1706 #define EMC_NFECR_HAMMING       (0 << 2)        /* Select HAMMING Correction Algorithm */
1707 #define EMC_NFECR_RS            (1 << 2)        /* Select RS Correction Algorithm */
1708 #define EMC_NFECR_ERST          (1 << 1)        /* ECC Reset */
1709 #define EMC_NFECR_ECCE          (1 << 0)        /* ECC Enable */
1710
1711 /* NAND Flash ECC Data Register */
1712 #define EMC_NFECC_ECC2_BIT      16
1713 #define EMC_NFECC_ECC2_MASK     (0xff << EMC_NFECC_ECC2_BIT)
1714 #define EMC_NFECC_ECC1_BIT      8
1715 #define EMC_NFECC_ECC1_MASK     (0xff << EMC_NFECC_ECC1_BIT)
1716 #define EMC_NFECC_ECC0_BIT      0
1717 #define EMC_NFECC_ECC0_MASK     (0xff << EMC_NFECC_ECC0_BIT)
1718
1719 /* NAND Flash Interrupt Status Register */
1720 #define EMC_NFINTS_ERRCNT_BIT   29      /* Error Count */
1721 #define EMC_NFINTS_ERRCNT_MASK  (0x7 << EMC_NFINTS_ERRCNT_BIT)
1722 #define EMC_NFINTS_PADF         (1 << 4)        /* Padding Finished */
1723 #define EMC_NFINTS_DECF         (1 << 3)        /* Decoding Finished */
1724 #define EMC_NFINTS_ENCF         (1 << 2)        /* Encoding Finished */
1725 #define EMC_NFINTS_UNCOR        (1 << 1)        /* Uncorrectable Error Occurred */
1726 #define EMC_NFINTS_ERR          (1 << 0)        /* Error Occurred */
1727
1728 /* NAND Flash Interrupt Enable Register */
1729 #define EMC_NFINTE_PADFE        (1 << 4)        /* Padding Finished Interrupt Enable */
1730 #define EMC_NFINTE_DECFE        (1 << 3)        /* Decoding Finished Interrupt Enable */
1731 #define EMC_NFINTE_ENCFE        (1 << 2)        /* Encoding Finished Interrupt Enable */
1732 #define EMC_NFINTE_UNCORE       (1 << 1)        /* Uncorrectable Error Occurred Intr Enable */
1733 #define EMC_NFINTE_ERRE         (1 << 0)        /* Error Occurred Interrupt */
1734
1735 /* NAND Flash RS Error Report Register */
1736 #define EMC_NFERR_INDEX_BIT     16      /* Error Symbol Index */
1737 #define EMC_NFERR_INDEX_MASK    (0x1ff << EMC_NFERR_INDEX_BIT)
1738 #define EMC_NFERR_MASK_BIT      0       /* Error Symbol Value */
1739 #define EMC_NFERR_MASK_MASK     (0x1ff << EMC_NFERR_MASK_BIT)
1740
1741
1742 /* DRAM Control Register */
1743 #define EMC_DMCR_BW_BIT         31
1744 #define EMC_DMCR_BW             (1 << EMC_DMCR_BW_BIT)
1745 #define EMC_DMCR_CA_BIT         26
1746 #define EMC_DMCR_CA_MASK        (0x07 << EMC_DMCR_CA_BIT)
1747 #define EMC_DMCR_CA_8           (0 << EMC_DMCR_CA_BIT)
1748 #define EMC_DMCR_CA_9           (1 << EMC_DMCR_CA_BIT)
1749 #define EMC_DMCR_CA_10  (2 << EMC_DMCR_CA_BIT)
1750 #define EMC_DMCR_CA_11  (3 << EMC_DMCR_CA_BIT)
1751 #define EMC_DMCR_CA_12  (4 << EMC_DMCR_CA_BIT)
1752 #define EMC_DMCR_RMODE          (1 << 25)
1753 #define EMC_DMCR_RFSH           (1 << 24)
1754 #define EMC_DMCR_MRSET          (1 << 23)
1755 #define EMC_DMCR_RA_BIT         20
1756 #define EMC_DMCR_RA_MASK        (0x03 << EMC_DMCR_RA_BIT)
1757 #define EMC_DMCR_RA_11  (0 << EMC_DMCR_RA_BIT)
1758 #define EMC_DMCR_RA_12  (1 << EMC_DMCR_RA_BIT)
1759 #define EMC_DMCR_RA_13  (2 << EMC_DMCR_RA_BIT)
1760 #define EMC_DMCR_BA_BIT         19
1761 #define EMC_DMCR_BA             (1 << EMC_DMCR_BA_BIT)
1762 #define EMC_DMCR_PDM            (1 << 18)
1763 #define EMC_DMCR_EPIN           (1 << 17)
1764 #define EMC_DMCR_TRAS_BIT       13
1765 #define EMC_DMCR_TRAS_MASK      (0x07 << EMC_DMCR_TRAS_BIT)
1766 #define EMC_DMCR_RCD_BIT        11
1767 #define EMC_DMCR_RCD_MASK       (0x03 << EMC_DMCR_RCD_BIT)
1768 #define EMC_DMCR_TPC_BIT        8
1769 #define EMC_DMCR_TPC_MASK       (0x07 << EMC_DMCR_TPC_BIT)
1770 #define EMC_DMCR_TRWL_BIT       5
1771 #define EMC_DMCR_TRWL_MASK      (0x03 << EMC_DMCR_TRWL_BIT)
1772 #define EMC_DMCR_TRC_BIT        2
1773 #define EMC_DMCR_TRC_MASK       (0x07 << EMC_DMCR_TRC_BIT)
1774 #define EMC_DMCR_TCL_BIT        0
1775 #define EMC_DMCR_TCL_MASK       (0x03 << EMC_DMCR_TCL_BIT)
1776
1777 /* Refresh Time Control/Status Register */
1778 #define EMC_RTCSR_CMF           (1 << 7)
1779 #define EMC_RTCSR_CKS_BIT       0
1780 #define EMC_RTCSR_CKS_MASK      (0x07 << EMC_RTCSR_CKS_BIT)
1781 #define EMC_RTCSR_CKS_DISABLE   (0 << EMC_RTCSR_CKS_BIT)
1782 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1783 #define EMC_RTCSR_CKS_16        (2 << EMC_RTCSR_CKS_BIT)
1784 #define EMC_RTCSR_CKS_64        (3 << EMC_RTCSR_CKS_BIT)
1785 #define EMC_RTCSR_CKS_256       (4 << EMC_RTCSR_CKS_BIT)
1786 #define EMC_RTCSR_CKS_1024      (5 << EMC_RTCSR_CKS_BIT)
1787 #define EMC_RTCSR_CKS_2048      (6 << EMC_RTCSR_CKS_BIT)
1788 #define EMC_RTCSR_CKS_4096      (7 << EMC_RTCSR_CKS_BIT)
1789
1790 /* SDRAM Bank Address Configuration Register */
1791 #define EMC_DMAR_BASE_BIT       8
1792 #define EMC_DMAR_BASE_MASK      (0xff << EMC_DMAR_BASE_BIT)
1793 #define EMC_DMAR_MASK_BIT       0
1794 #define EMC_DMAR_MASK_MASK      (0xff << EMC_DMAR_MASK_BIT)
1795
1796 /* Mode Register of SDRAM bank 0 */
1797 #define EMC_SDMR_BM             (1 << 9)        /* Write Burst Mode */
1798 #define EMC_SDMR_OM_BIT         7       /* Operating Mode */
1799 #define EMC_SDMR_OM_MASK        (3 << EMC_SDMR_OM_BIT)
1800 #define EMC_SDMR_OM_NORMAL      (0 << EMC_SDMR_OM_BIT)
1801 #define EMC_SDMR_CAS_BIT        4       /* CAS Latency */
1802 #define EMC_SDMR_CAS_MASK       (7 << EMC_SDMR_CAS_BIT)
1803 #define EMC_SDMR_CAS_1  (1 << EMC_SDMR_CAS_BIT)
1804 #define EMC_SDMR_CAS_2  (2 << EMC_SDMR_CAS_BIT)
1805 #define EMC_SDMR_CAS_3  (3 << EMC_SDMR_CAS_BIT)
1806 #define EMC_SDMR_BT_BIT         3       /* Burst Type */
1807 #define EMC_SDMR_BT_MASK        (1 << EMC_SDMR_BT_BIT)
1808 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT)  /* Sequential */
1809 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT)  /* Interleave */
1810 #define EMC_SDMR_BL_BIT         0       /* Burst Length */
1811 #define EMC_SDMR_BL_MASK        (7 << EMC_SDMR_BL_BIT)
1812 #define EMC_SDMR_BL_1           (0 << EMC_SDMR_BL_BIT)
1813 #define EMC_SDMR_BL_2           (1 << EMC_SDMR_BL_BIT)
1814 #define EMC_SDMR_BL_4           (2 << EMC_SDMR_BL_BIT)
1815 #define EMC_SDMR_BL_8           (3 << EMC_SDMR_BL_BIT)
1816
1817 #define EMC_SDMR_CAS2_16BIT \
1818   (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1819 #define EMC_SDMR_CAS2_32BIT \
1820   (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1821 #define EMC_SDMR_CAS3_16BIT \
1822   (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1823 #define EMC_SDMR_CAS3_32BIT \
1824   (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1825
1826
1827 /*************************************************************************
1828  * CIM
1829  *************************************************************************/
1830 #define CIM_CFG                 (CIM_BASE + 0x0000)
1831 #define CIM_CTRL                (CIM_BASE + 0x0004)
1832 #define CIM_STATE               (CIM_BASE + 0x0008)
1833 #define CIM_IID                 (CIM_BASE + 0x000C)
1834 #define CIM_RXFIFO              (CIM_BASE + 0x0010)
1835 #define CIM_DA                  (CIM_BASE + 0x0020)
1836 #define CIM_FA                  (CIM_BASE + 0x0024)
1837 #define CIM_FID                 (CIM_BASE + 0x0028)
1838 #define CIM_CMD                 (CIM_BASE + 0x002C)
1839
1840 #define REG_CIM_CFG             REG32(CIM_CFG)
1841 #define REG_CIM_CTRL            REG32(CIM_CTRL)
1842 #define REG_CIM_STATE           REG32(CIM_STATE)
1843 #define REG_CIM_IID             REG32(CIM_IID)
1844 #define REG_CIM_RXFIFO          REG32(CIM_RXFIFO)
1845 #define REG_CIM_DA              REG32(CIM_DA)
1846 #define REG_CIM_FA              REG32(CIM_FA)
1847 #define REG_CIM_FID             REG32(CIM_FID)
1848 #define REG_CIM_CMD             REG32(CIM_CMD)
1849
1850 /* CIM Configuration Register  (CIM_CFG) */
1851
1852 #define CIM_CFG_INV_DAT         (1 << 15)
1853 #define CIM_CFG_VSP             (1 << 14)
1854 #define CIM_CFG_HSP             (1 << 13)
1855 #define CIM_CFG_PCP             (1 << 12)
1856 #define CIM_CFG_DUMMY_ZERO      (1 << 9)
1857 #define CIM_CFG_EXT_VSYNC       (1 << 8)
1858 #define CIM_CFG_PACK_BIT        4
1859 #define CIM_CFG_PACK_MASK       (0x7 << CIM_CFG_PACK_BIT)
1860 #define CIM_CFG_PACK_0    (0 << CIM_CFG_PACK_BIT)
1861 #define CIM_CFG_PACK_1    (1 << CIM_CFG_PACK_BIT)
1862 #define CIM_CFG_PACK_2    (2 << CIM_CFG_PACK_BIT)
1863 #define CIM_CFG_PACK_3    (3 << CIM_CFG_PACK_BIT)
1864 #define CIM_CFG_PACK_4    (4 << CIM_CFG_PACK_BIT)
1865 #define CIM_CFG_PACK_5    (5 << CIM_CFG_PACK_BIT)
1866 #define CIM_CFG_PACK_6    (6 << CIM_CFG_PACK_BIT)
1867 #define CIM_CFG_PACK_7    (7 << CIM_CFG_PACK_BIT)
1868 #define CIM_CFG_DSM_BIT         0
1869 #define CIM_CFG_DSM_MASK        (0x3 << CIM_CFG_DSM_BIT)
1870 #define CIM_CFG_DSM_CPM   (0 << CIM_CFG_DSM_BIT)        /* CCIR656 Progressive Mode */
1871 #define CIM_CFG_DSM_CIM   (1 << CIM_CFG_DSM_BIT)        /* CCIR656 Interlace Mode */
1872 #define CIM_CFG_DSM_GCM   (2 << CIM_CFG_DSM_BIT)        /* Gated Clock Mode */
1873 #define CIM_CFG_DSM_NGCM          (3 << CIM_CFG_DSM_BIT)        /* Non-Gated Clock Mode */
1874
1875 /* CIM Control Register  (CIM_CTRL) */
1876
1877 #define CIM_CTRL_MCLKDIV_BIT    24
1878 #define CIM_CTRL_MCLKDIV_MASK   (0xff << CIM_CTRL_MCLKDIV_BIT)
1879 #define CIM_CTRL_FRC_BIT        16
1880 #define CIM_CTRL_FRC_MASK       (0xf << CIM_CTRL_FRC_BIT)
1881 #define CIM_CTRL_FRC_1    (0x0 << CIM_CTRL_FRC_BIT)     /* Sample every frame */
1882 #define CIM_CTRL_FRC_2    (0x1 << CIM_CTRL_FRC_BIT)     /* Sample 1/2 frame */
1883 #define CIM_CTRL_FRC_3    (0x2 << CIM_CTRL_FRC_BIT)     /* Sample 1/3 frame */
1884 #define CIM_CTRL_FRC_4    (0x3 << CIM_CTRL_FRC_BIT)     /* Sample 1/4 frame */
1885 #define CIM_CTRL_FRC_5    (0x4 << CIM_CTRL_FRC_BIT)     /* Sample 1/5 frame */
1886 #define CIM_CTRL_FRC_6    (0x5 << CIM_CTRL_FRC_BIT)     /* Sample 1/6 frame */
1887 #define CIM_CTRL_FRC_7    (0x6 << CIM_CTRL_FRC_BIT)     /* Sample 1/7 frame */
1888 #define CIM_CTRL_FRC_8    (0x7 << CIM_CTRL_FRC_BIT)     /* Sample 1/8 frame */
1889 #define CIM_CTRL_FRC_9    (0x8 << CIM_CTRL_FRC_BIT)     /* Sample 1/9 frame */
1890 #define CIM_CTRL_FRC_10   (0x9 << CIM_CTRL_FRC_BIT)     /* Sample 1/10 frame */
1891 #define CIM_CTRL_FRC_11   (0xA << CIM_CTRL_FRC_BIT)     /* Sample 1/11 frame */
1892 #define CIM_CTRL_FRC_12   (0xB << CIM_CTRL_FRC_BIT)     /* Sample 1/12 frame */
1893 #define CIM_CTRL_FRC_13   (0xC << CIM_CTRL_FRC_BIT)     /* Sample 1/13 frame */
1894 #define CIM_CTRL_FRC_14   (0xD << CIM_CTRL_FRC_BIT)     /* Sample 1/14 frame */
1895 #define CIM_CTRL_FRC_15   (0xE << CIM_CTRL_FRC_BIT)     /* Sample 1/15 frame */
1896 #define CIM_CTRL_FRC_16   (0xF << CIM_CTRL_FRC_BIT)     /* Sample 1/16 frame */
1897 #define CIM_CTRL_VDDM           (1 << 13)
1898 #define CIM_CTRL_DMA_SOFM       (1 << 12)
1899 #define CIM_CTRL_DMA_EOFM       (1 << 11)
1900 #define CIM_CTRL_DMA_STOPM      (1 << 10)
1901 #define CIM_CTRL_RXF_TRIGM      (1 << 9)
1902 #define CIM_CTRL_RXF_OFM        (1 << 8)
1903 #define CIM_CTRL_RXF_TRIG_BIT   4
1904 #define CIM_CTRL_RXF_TRIG_MASK  (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1905 #define CIM_CTRL_RXF_TRIG_4       (0 << CIM_CTRL_RXF_TRIG_BIT)  /* RXFIFO Trigger Value is 4 */
1906 #define CIM_CTRL_RXF_TRIG_8       (1 << CIM_CTRL_RXF_TRIG_BIT)  /* RXFIFO Trigger Value is 8 */
1907 #define CIM_CTRL_RXF_TRIG_12      (2 << CIM_CTRL_RXF_TRIG_BIT)  /* RXFIFO Trigger Value is 12 */
1908 #define CIM_CTRL_RXF_TRIG_16      (3 << CIM_CTRL_RXF_TRIG_BIT)  /* RXFIFO Trigger Value is 16 */
1909 #define CIM_CTRL_RXF_TRIG_20      (4 << CIM_CTRL_RXF_TRIG_BIT)  /* RXFIFO Trigger Value is 20 */
1910 #define CIM_CTRL_RXF_TRIG_24      (5 << CIM_CTRL_RXF_TRIG_BIT)  /* RXFIFO Trigger Value is 24 */
1911 #define CIM_CTRL_RXF_TRIG_28      (6 << CIM_CTRL_RXF_TRIG_BIT)  /* RXFIFO Trigger Value is 28 */
1912 #define CIM_CTRL_RXF_TRIG_32      (7 << CIM_CTRL_RXF_TRIG_BIT)  /* RXFIFO Trigger Value is 32 */
1913 #define CIM_CTRL_DMA_EN         (1 << 2)
1914 #define CIM_CTRL_RXF_RST        (1 << 1)
1915 #define CIM_CTRL_ENA            (1 << 0)
1916
1917 /* CIM State Register  (CIM_STATE) */
1918
1919 #define CIM_STATE_DMA_SOF       (1 << 6)
1920 #define CIM_STATE_DMA_EOF       (1 << 5)
1921 #define CIM_STATE_DMA_STOP      (1 << 4)
1922 #define CIM_STATE_RXF_OF        (1 << 3)
1923 #define CIM_STATE_RXF_TRIG      (1 << 2)
1924 #define CIM_STATE_RXF_EMPTY     (1 << 1)
1925 #define CIM_STATE_VDD           (1 << 0)
1926
1927 /* CIM DMA Command Register (CIM_CMD) */
1928
1929 #define CIM_CMD_SOFINT          (1 << 31)
1930 #define CIM_CMD_EOFINT          (1 << 30)
1931 #define CIM_CMD_STOP            (1 << 28)
1932 #define CIM_CMD_LEN_BIT         0
1933 #define CIM_CMD_LEN_MASK        (0xffffff << CIM_CMD_LEN_BIT)
1934
1935
1936 /*************************************************************************
1937  * SADC (Smart A/D Controller)
1938  *************************************************************************/
1939
1940 #define SADC_ENA        (SADC_BASE + 0x00)      /* ADC Enable Register */
1941 #define SADC_CFG        (SADC_BASE + 0x04)      /* ADC Configure Register */
1942 #define SADC_CTRL       (SADC_BASE + 0x08)      /* ADC Control Register */
1943 #define SADC_STATE      (SADC_BASE + 0x0C)      /* ADC Status Register */
1944 #define SADC_SAMETIME   (SADC_BASE + 0x10)      /* ADC Same Point Time Register */
1945 #define SADC_WAITTIME   (SADC_BASE + 0x14)      /* ADC Wait Time Register */
1946 #define SADC_TSDAT      (SADC_BASE + 0x18)      /* ADC Touch Screen Data Register */
1947 #define SADC_BATDAT     (SADC_BASE + 0x1C)      /* ADC PBAT Data Register */
1948 #define SADC_SADDAT     (SADC_BASE + 0x20)      /* ADC SADCIN Data Register */
1949
1950 #define REG_SADC_ENA            REG8(SADC_ENA)
1951 #define REG_SADC_CFG            REG32(SADC_CFG)
1952 #define REG_SADC_CTRL           REG8(SADC_CTRL)
1953 #define REG_SADC_STATE          REG8(SADC_STATE)
1954 #define REG_SADC_SAMETIME       REG16(SADC_SAMETIME)
1955 #define REG_SADC_WAITTIME       REG16(SADC_WAITTIME)
1956 #define REG_SADC_TSDAT          REG32(SADC_TSDAT)
1957 #define REG_SADC_BATDAT         REG16(SADC_BATDAT)
1958 #define REG_SADC_SADDAT         REG16(SADC_SADDAT)
1959
1960 /* ADC Enable Register */
1961 #define SADC_ENA_ADEN           (1 << 7)        /* Touch Screen Enable */
1962 #define SADC_ENA_TSEN           (1 << 2)        /* Touch Screen Enable */
1963 #define SADC_ENA_PBATEN         (1 << 1)        /* PBAT Enable */
1964 #define SADC_ENA_SADCINEN       (1 << 0)        /* SADCIN Enable */
1965
1966 /* ADC Configure Register */
1967 #define SADC_CFG_CLKOUT_NUM_BIT 16
1968 #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
1969 #define SADC_CFG_TS_DMA         (1 << 15)       /* Touch Screen DMA Enable */
1970 #define SADC_CFG_XYZ_BIT        13      /* XYZ selection */
1971 #define SADC_CFG_XYZ_MASK       (0x3 << SADC_CFG_XYZ_BIT)
1972 #define SADC_CFG_XY             (0 << SADC_CFG_XYZ_BIT)
1973 #define SADC_CFG_XYZ            (1 << SADC_CFG_XYZ_BIT)
1974 #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
1975 #define SADC_CFG_SNUM_BIT       10      /* Sample Number */
1976 #define SADC_CFG_SNUM_MASK      (0x7 << SADC_CFG_SNUM_BIT)
1977 #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
1978 #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
1979 #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
1980 #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
1981 #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
1982 #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
1983 #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
1984 #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
1985 #define SADC_CFG_CLKDIV_BIT     5       /* AD Converter frequency clock divider */
1986 #define SADC_CFG_CLKDIV_MASK    (0x1f << SADC_CFG_CLKDIV_BIT)
1987 #define SADC_CFG_PBAT_HIGH      (0 << 4)        /* PBAT >= 2.5V */
1988 #define SADC_CFG_PBAT_LOW       (1 << 4)        /* PBAT < 2.5V */
1989 #define SADC_CFG_CMD_BIT        0       /* ADC Command */
1990 #define SADC_CFG_CMD_MASK       (0xf << SADC_CFG_CMD_BIT)
1991 #define SADC_CFG_CMD_X_SE       (0x0 << SADC_CFG_CMD_BIT)       /* X Single-End */
1992 #define SADC_CFG_CMD_Y_SE       (0x1 << SADC_CFG_CMD_BIT)       /* Y Single-End */
1993 #define SADC_CFG_CMD_X_DIFF     (0x2 << SADC_CFG_CMD_BIT)       /* X Differential */
1994 #define SADC_CFG_CMD_Y_DIFF     (0x3 << SADC_CFG_CMD_BIT)       /* Y Differential */
1995 #define SADC_CFG_CMD_Z1_DIFF    (0x4 << SADC_CFG_CMD_BIT)       /* Z1 Differential */
1996 #define SADC_CFG_CMD_Z2_DIFF    (0x5 << SADC_CFG_CMD_BIT)       /* Z2 Differential */
1997 #define SADC_CFG_CMD_Z3_DIFF    (0x6 << SADC_CFG_CMD_BIT)       /* Z3 Differential */
1998 #define SADC_CFG_CMD_Z4_DIFF    (0x7 << SADC_CFG_CMD_BIT)       /* Z4 Differential */
1999 #define SADC_CFG_CMD_TP_SE      (0x8 << SADC_CFG_CMD_BIT)       /* Touch Pressure */
2000 #define SADC_CFG_CMD_PBATH_SE   (0x9 << SADC_CFG_CMD_BIT)       /* PBAT >= 2.5V */
2001 #define SADC_CFG_CMD_PBATL_SE   (0xa << SADC_CFG_CMD_BIT)       /* PBAT < 2.5V */
2002 #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT)        /* Measure SADCIN */
2003 #define SADC_CFG_CMD_INT_PEN    (0xc << SADC_CFG_CMD_BIT)       /* INT_PEN Enable */
2004
2005 /* ADC Control Register */
2006 #define SADC_CTRL_PENDM         (1 << 4)        /* Pen Down Interrupt Mask */
2007 #define SADC_CTRL_PENUM         (1 << 3)        /* Pen Up Interrupt Mask */
2008 #define SADC_CTRL_TSRDYM        (1 << 2)        /* Touch Screen Data Ready Interrupt Mask */
2009 #define SADC_CTRL_PBATRDYM      (1 << 1)        /* PBAT Data Ready Interrupt Mask */
2010 #define SADC_CTRL_SRDYM         (1 << 0)        /* SADCIN Data Ready Interrupt Mask */
2011
2012 /* ADC Status Register */
2013 #define SADC_STATE_TSBUSY       (1 << 7)        /* TS A/D is working */
2014 #define SADC_STATE_PBATBUSY     (1 << 6)        /* PBAT A/D is working */
2015 #define SADC_STATE_SBUSY        (1 << 5)        /* SADCIN A/D is working */
2016 #define SADC_STATE_PEND         (1 << 4)        /* Pen Down Interrupt Flag */
2017 #define SADC_STATE_PENU         (1 << 3)        /* Pen Up Interrupt Flag */
2018 #define SADC_STATE_TSRDY        (1 << 2)        /* Touch Screen Data Ready Interrupt Flag */
2019 #define SADC_STATE_PBATRDY      (1 << 1)        /* PBAT Data Ready Interrupt Flag */
2020 #define SADC_STATE_SRDY         (1 << 0)        /* SADCIN Data Ready Interrupt Flag */
2021
2022 /* ADC Touch Screen Data Register */
2023 #define SADC_TSDAT_DATA0_BIT    0
2024 #define SADC_TSDAT_DATA0_MASK   (0xfff << SADC_TSDAT_DATA0_BIT)
2025 #define SADC_TSDAT_TYPE0        (1 << 15)
2026 #define SADC_TSDAT_DATA1_BIT    16
2027 #define SADC_TSDAT_DATA1_MASK   (0xfff << SADC_TSDAT_DATA1_BIT)
2028 #define SADC_TSDAT_TYPE1        (1 << 31)
2029
2030
2031 /*************************************************************************
2032  * SLCD (Smart LCD Controller)
2033  *************************************************************************/
2034
2035 #define SLCD_CFG        (SLCD_BASE + 0xA0)      /* SLCD Configure Register */
2036 #define SLCD_CTRL       (SLCD_BASE + 0xA4)      /* SLCD Control Register */
2037 #define SLCD_STATE      (SLCD_BASE + 0xA8)      /* SLCD Status Register */
2038 #define SLCD_DATA       (SLCD_BASE + 0xAC)      /* SLCD Data Register */
2039 #define SLCD_FIFO       (SLCD_BASE + 0xB0)      /* SLCD FIFO Register */
2040
2041 #define REG_SLCD_CFG    REG32(SLCD_CFG)
2042 #define REG_SLCD_CTRL   REG8(SLCD_CTRL)
2043 #define REG_SLCD_STATE  REG8(SLCD_STATE)
2044 #define REG_SLCD_DATA   REG32(SLCD_DATA)
2045 #define REG_SLCD_FIFO   REG32(SLCD_FIFO)
2046
2047 /* SLCD Configure Register */
2048 #define SLCD_CFG_BURST_BIT      14
2049 #define SLCD_CFG_BURST_MASK     (0x3 << SLCD_CFG_BURST_BIT)
2050 #define SLCD_CFG_BURST_4_WORD   (0 << SLCD_CFG_BURST_BIT)
2051 #define SLCD_CFG_BURST_8_WORD   (1 << SLCD_CFG_BURST_BIT)
2052 #define SLCD_CFG_DWIDTH_BIT     10
2053 #define SLCD_CFG_DWIDTH_MASK    (0x7 << SLCD_CFG_DWIDTH_BIT)
2054 #define SLCD_CFG_DWIDTH_18      (0 << SLCD_CFG_DWIDTH_BIT)
2055 #define SLCD_CFG_DWIDTH_16      (1 << SLCD_CFG_DWIDTH_BIT)
2056 #define SLCD_CFG_DWIDTH_8_x3    (2 << SLCD_CFG_DWIDTH_BIT)
2057 #define SLCD_CFG_DWIDTH_8_x2    (3 << SLCD_CFG_DWIDTH_BIT)
2058 #define SLCD_CFG_DWIDTH_9_x2    (4 << SLCD_CFG_DWIDTH_BIT)
2059 #define SLCD_CFG_CWIDTH_16BIT   (0 << 8)
2060 #define SLCD_CFG_CWIDTH_8BIT    (1 << 8)
2061 #define SLCD_CFG_CS_ACTIVE_LOW  (0 << 4)
2062 #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2063 #define SLCD_CFG_RS_CMD_LOW     (0 << 3)
2064 #define SLCD_CFG_RS_CMD_HIGH    (1 << 3)
2065 #define SLCD_CFG_CLK_ACTIVE_FALLING     (0 << 1)
2066 #define SLCD_CFG_CLK_ACTIVE_RISING      (1 << 1)
2067 #define SLCD_CFG_TYPE_PARALLEL  (0 << 0)
2068 #define SLCD_CFG_TYPE_SERIAL    (1 << 0)
2069
2070 /* SLCD Control Register */
2071 #define SLCD_CTRL_DMA_EN        (1 << 0)
2072
2073 /* SLCD Status Register */
2074 #define SLCD_STATE_BUSY         (1 << 0)
2075
2076 /* SLCD Data Register */
2077 #define SLCD_DATA_RS_DATA       (0 << 31)
2078 #define SLCD_DATA_RS_COMMAND    (1 << 31)
2079
2080 /* SLCD FIFO Register */
2081 #define SLCD_FIFO_RS_DATA       (0 << 31)
2082 #define SLCD_FIFO_RS_COMMAND    (1 << 31)
2083
2084
2085 /*************************************************************************
2086  * LCD (LCD Controller)
2087  *************************************************************************/
2088 #define LCD_CFG         (LCD_BASE + 0x00)       /* LCD Configure Register */
2089 #define LCD_VSYNC       (LCD_BASE + 0x04)       /* Vertical Synchronize Register */
2090 #define LCD_HSYNC       (LCD_BASE + 0x08)       /* Horizontal Synchronize Register */
2091 #define LCD_VAT         (LCD_BASE + 0x0c)       /* Virtual Area Setting Register */
2092 #define LCD_DAH         (LCD_BASE + 0x10)       /* Display Area Horizontal Start/End Point */
2093 #define LCD_DAV         (LCD_BASE + 0x14)       /* Display Area Vertical Start/End Point */
2094 #define LCD_PS          (LCD_BASE + 0x18)       /* PS Signal Setting */
2095 #define LCD_CLS         (LCD_BASE + 0x1c)       /* CLS Signal Setting */
2096 #define LCD_SPL         (LCD_BASE + 0x20)       /* SPL Signal Setting */
2097 #define LCD_REV         (LCD_BASE + 0x24)       /* REV Signal Setting */
2098 #define LCD_CTRL        (LCD_BASE + 0x30)       /* LCD Control Register */
2099 #define LCD_STATE       (LCD_BASE + 0x34)       /* LCD Status Register */
2100 #define LCD_IID         (LCD_BASE + 0x38)       /* Interrupt ID Register */
2101 #define LCD_DA0         (LCD_BASE + 0x40)       /* Descriptor Address Register 0 */
2102 #define LCD_SA0         (LCD_BASE + 0x44)       /* Source Address Register 0 */
2103 #define LCD_FID0        (LCD_BASE + 0x48)       /* Frame ID Register 0 */
2104 #define LCD_CMD0        (LCD_BASE + 0x4c)       /* DMA Command Register 0 */
2105 #define LCD_DA1         (LCD_BASE + 0x50)       /* Descriptor Address Register 1 */
2106 #define LCD_SA1         (LCD_BASE + 0x54)       /* Source Address Register 1 */
2107 #define LCD_FID1        (LCD_BASE + 0x58)       /* Frame ID Register 1 */
2108 #define LCD_CMD1        (LCD_BASE + 0x5c)       /* DMA Command Register 1 */
2109
2110 #define REG_LCD_CFG     REG32(LCD_CFG)
2111 #define REG_LCD_VSYNC   REG32(LCD_VSYNC)
2112 #define REG_LCD_HSYNC   REG32(LCD_HSYNC)
2113 #define REG_LCD_VAT     REG32(LCD_VAT)
2114 #define REG_LCD_DAH     REG32(LCD_DAH)
2115 #define REG_LCD_DAV     REG32(LCD_DAV)
2116 #define REG_LCD_PS      REG32(LCD_PS)
2117 #define REG_LCD_CLS     REG32(LCD_CLS)
2118 #define REG_LCD_SPL     REG32(LCD_SPL)
2119 #define REG_LCD_REV     REG32(LCD_REV)
2120 #define REG_LCD_CTRL    REG32(LCD_CTRL)
2121 #define REG_LCD_STATE   REG32(LCD_STATE)
2122 #define REG_LCD_IID     REG32(LCD_IID)
2123 #define REG_LCD_DA0     REG32(LCD_DA0)
2124 #define REG_LCD_SA0     REG32(LCD_SA0)
2125 #define REG_LCD_FID0    REG32(LCD_FID0)
2126 #define REG_LCD_CMD0    REG32(LCD_CMD0)
2127 #define REG_LCD_DA1     REG32(LCD_DA1)
2128 #define REG_LCD_SA1     REG32(LCD_SA1)
2129 #define REG_LCD_FID1    REG32(LCD_FID1)
2130 #define REG_LCD_CMD1    REG32(LCD_CMD1)
2131
2132 /* LCD Configure Register */
2133 #define LCD_CFG_LCDPIN_BIT      31      /* LCD pins selection */
2134 #define LCD_CFG_LCDPIN_MASK     (0x1 << LCD_CFG_LCDPIN_BIT)
2135 #define LCD_CFG_LCDPIN_LCD      (0x0 << LCD_CFG_LCDPIN_BIT)
2136 #define LCD_CFG_LCDPIN_SLCD     (0x1 << LCD_CFG_LCDPIN_BIT)
2137 #define LCD_CFG_PSM             (1 << 23)       /* PS signal mode */
2138 #define LCD_CFG_CLSM            (1 << 22)       /* CLS signal mode */
2139 #define LCD_CFG_SPLM            (1 << 21)       /* SPL signal mode */
2140 #define LCD_CFG_REVM            (1 << 20)       /* REV signal mode */
2141 #define LCD_CFG_HSYNM           (1 << 19)       /* HSYNC signal mode */
2142 #define LCD_CFG_PCLKM           (1 << 18)       /* PCLK signal mode */
2143 #define LCD_CFG_INVDAT          (1 << 17)       /* Inverse output data */
2144 #define LCD_CFG_SYNDIR_IN       (1 << 16)       /* VSYNC&HSYNC direction */
2145 #define LCD_CFG_PSP             (1 << 15)       /* PS pin reset state */
2146 #define LCD_CFG_CLSP            (1 << 14)       /* CLS pin reset state */
2147 #define LCD_CFG_SPLP            (1 << 13)       /* SPL pin reset state */
2148 #define LCD_CFG_REVP            (1 << 12)       /* REV pin reset state */
2149 #define LCD_CFG_HSP             (1 << 11)       /* HSYNC pority:0-active high,1-active low */
2150 #define LCD_CFG_PCP             (1 << 10)       /* PCLK pority:0-rising,1-falling */
2151 #define LCD_CFG_DEP             (1 << 9)        /* DE pority:0-active high,1-active low */
2152 #define LCD_CFG_VSP             (1 << 8)        /* VSYNC pority:0-rising,1-falling */
2153 #define LCD_CFG_PDW_BIT         4       /* STN pins utilization */
2154 #define LCD_CFG_PDW_MASK        (0x3 << LCD_DEV_PDW_BIT)
2155 #define LCD_CFG_PDW_1           (0 << LCD_CFG_PDW_BIT)  /* LCD_D[0] */
2156 #define LCD_CFG_PDW_2           (1 << LCD_CFG_PDW_BIT)  /* LCD_D[0:1] */
2157 #define LCD_CFG_PDW_4           (2 << LCD_CFG_PDW_BIT)  /* LCD_D[0:3]/LCD_D[8:11] */
2158 #define LCD_CFG_PDW_8           (3 << LCD_CFG_PDW_BIT)  /* LCD_D[0:7]/LCD_D[8:15] */
2159 #define LCD_CFG_MODE_BIT        0       /* Display Device Mode Select */
2160 #define LCD_CFG_MODE_MASK       (0x0f << LCD_CFG_MODE_BIT)
2161 #define LCD_CFG_MODE_GENERIC_TFT        (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2162 #define LCD_CFG_MODE_SPECIAL_TFT_1      (1 << LCD_CFG_MODE_BIT)
2163 #define LCD_CFG_MODE_SPECIAL_TFT_2      (2 << LCD_CFG_MODE_BIT)
2164 #define LCD_CFG_MODE_SPECIAL_TFT_3      (3 << LCD_CFG_MODE_BIT)
2165 #define LCD_CFG_MODE_NONINTER_CCIR656   (4 << LCD_CFG_MODE_BIT)
2166 #define LCD_CFG_MODE_INTER_CCIR656      (5 << LCD_CFG_MODE_BIT)
2167 #define LCD_CFG_MODE_SINGLE_CSTN        (8 << LCD_CFG_MODE_BIT)
2168 #define LCD_CFG_MODE_SINGLE_MSTN        (9 << LCD_CFG_MODE_BIT)
2169 #define LCD_CFG_MODE_DUAL_CSTN  (10 << LCD_CFG_MODE_BIT)
2170 #define LCD_CFG_MODE_DUAL_MSTN  (11 << LCD_CFG_MODE_BIT)
2171 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2172 #define LCD_CFG_MODE_GENERIC_18BIT_TFT  (13 << LCD_CFG_MODE_BIT)
2173   /* JZ47XX defines */
2174 #define LCD_CFG_MODE_SHARP_HR           (1 << LCD_CFG_MODE_BIT)
2175 #define LCD_CFG_MODE_CASIO_TFT  (2 << LCD_CFG_MODE_BIT)
2176 #define LCD_CFG_MODE_SAMSUNG_ALPHA      (3 << LCD_CFG_MODE_BIT)
2177
2178
2179
2180 /* Vertical Synchronize Register */
2181 #define LCD_VSYNC_VPS_BIT       16      /* VSYNC pulse start in line clock, fixed to 0 */
2182 #define LCD_VSYNC_VPS_MASK      (0xffff << LCD_VSYNC_VPS_BIT)
2183 #define LCD_VSYNC_VPE_BIT       0       /* VSYNC pulse end in line clock */
2184 #define LCD_VSYNC_VPE_MASK      (0xffff << LCD_VSYNC_VPS_BIT)
2185
2186 /* Horizontal Synchronize Register */
2187 #define LCD_HSYNC_HPS_BIT       16      /* HSYNC pulse start position in dot clock */
2188 #define LCD_HSYNC_HPS_MASK      (0xffff << LCD_HSYNC_HPS_BIT)
2189 #define LCD_HSYNC_HPE_BIT       0       /* HSYNC pulse end position in dot clock */
2190 #define LCD_HSYNC_HPE_MASK      (0xffff << LCD_HSYNC_HPE_BIT)
2191
2192 /* Virtual Area Setting Register */
2193 #define LCD_VAT_HT_BIT          16      /* Horizontal Total size in dot clock */
2194 #define LCD_VAT_HT_MASK         (0xffff << LCD_VAT_HT_BIT)
2195 #define LCD_VAT_VT_BIT          0       /* Vertical Total size in dot clock */
2196 #define LCD_VAT_VT_MASK         (0xffff << LCD_VAT_VT_BIT)
2197
2198 /* Display Area Horizontal Start/End Point Register */
2199 #define LCD_DAH_HDS_BIT         16      /* Horizontal display area start in dot clock */
2200 #define LCD_DAH_HDS_MASK        (0xffff << LCD_DAH_HDS_BIT)
2201 #define LCD_DAH_HDE_BIT         0       /* Horizontal display area end in dot clock */
2202 #define LCD_DAH_HDE_MASK        (0xffff << LCD_DAH_HDE_BIT)
2203
2204 /* Display Area Vertical Start/End Point Register */
2205 #define LCD_DAV_VDS_BIT         16      /* Vertical display area start in line clock */
2206 #define LCD_DAV_VDS_MASK        (0xffff << LCD_DAV_VDS_BIT)
2207 #define LCD_DAV_VDE_BIT         0       /* Vertical display area end in line clock */
2208 #define LCD_DAV_VDE_MASK        (0xffff << LCD_DAV_VDE_BIT)
2209
2210 /* PS Signal Setting */
2211 #define LCD_PS_PSS_BIT          16      /* PS signal start position in dot clock */
2212 #define LCD_PS_PSS_MASK         (0xffff << LCD_PS_PSS_BIT)
2213 #define LCD_PS_PSE_BIT          0       /* PS signal end position in dot clock */
2214 #define LCD_PS_PSE_MASK         (0xffff << LCD_PS_PSE_BIT)
2215
2216 /* CLS Signal Setting */
2217 #define LCD_CLS_CLSS_BIT        16      /* CLS signal start position in dot clock */
2218 #define LCD_CLS_CLSS_MASK       (0xffff << LCD_CLS_CLSS_BIT)
2219 #define LCD_CLS_CLSE_BIT        0       /* CLS signal end position in dot clock */
2220 #define LCD_CLS_CLSE_MASK       (0xffff << LCD_CLS_CLSE_BIT)
2221
2222 /* SPL Signal Setting */
2223 #define LCD_SPL_SPLS_BIT        16      /* SPL signal start position in dot clock */
2224 #define LCD_SPL_SPLS_MASK       (0xffff << LCD_SPL_SPLS_BIT)
2225 #define LCD_SPL_SPLE_BIT        0       /* SPL signal end position in dot clock */
2226 #define LCD_SPL_SPLE_MASK       (0xffff << LCD_SPL_SPLE_BIT)
2227
2228 /* REV Signal Setting */
2229 #define LCD_REV_REVS_BIT        16      /* REV signal start position in dot clock */
2230 #define LCD_REV_REVS_MASK       (0xffff << LCD_REV_REVS_BIT)
2231
2232 /* LCD Control Register */
2233 #define LCD_CTRL_BST_BIT        28      /* Burst Length Selection */
2234 #define LCD_CTRL_BST_MASK       (0x03 << LCD_CTRL_BST_BIT)
2235 #define LCD_CTRL_BST_4  (0 << LCD_CTRL_BST_BIT) /* 4-word */
2236 #define LCD_CTRL_BST_8  (1 << LCD_CTRL_BST_BIT) /* 8-word */
2237 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2238 #define LCD_CTRL_RGB565         (0 << 27)       /* RGB565 mode */
2239 #define LCD_CTRL_RGB555         (1 << 27)       /* RGB555 mode */
2240 #define LCD_CTRL_OFUP           (1 << 26)       /* Output FIFO underrun protection enable */
2241 #define LCD_CTRL_FRC_BIT        24      /* STN FRC Algorithm Selection */
2242 #define LCD_CTRL_FRC_MASK       (0x03 << LCD_CTRL_FRC_BIT)
2243 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2244 #define LCD_CTRL_FRC_4  (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2245 #define LCD_CTRL_FRC_2  (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2246 #define LCD_CTRL_PDD_BIT        16      /* Load Palette Delay Counter */
2247 #define LCD_CTRL_PDD_MASK       (0xff << LCD_CTRL_PDD_BIT)
2248 #define LCD_CTRL_EOFM           (1 << 13)       /* EOF interrupt mask */
2249 #define LCD_CTRL_SOFM           (1 << 12)       /* SOF interrupt mask */
2250 #define LCD_CTRL_OFUM           (1 << 11)       /* Output FIFO underrun interrupt mask */
2251 #define LCD_CTRL_IFUM0          (1 << 10)       /* Input FIFO 0 underrun interrupt mask */
2252 #define LCD_CTRL_IFUM1          (1 << 9)        /* Input FIFO 1 underrun interrupt mask */
2253 #define LCD_CTRL_LDDM           (1 << 8)        /* LCD disable done interrupt mask */
2254 #define LCD_CTRL_QDM            (1 << 7)        /* LCD quick disable done interrupt mask */
2255 #define LCD_CTRL_BEDN           (1 << 6)        /* Endian selection */
2256 #define LCD_CTRL_PEDN           (1 << 5)        /* Endian in byte:0-msb first, 1-lsb first */
2257 #define LCD_CTRL_DIS            (1 << 4)        /* Disable indicate bit */
2258 #define LCD_CTRL_ENA            (1 << 3)        /* LCD enable bit */
2259 #define LCD_CTRL_BPP_BIT        0       /* Bits Per Pixel */
2260 #define LCD_CTRL_BPP_MASK       (0x07 << LCD_CTRL_BPP_BIT)
2261 #define LCD_CTRL_BPP_1  (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2262 #define LCD_CTRL_BPP_2  (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2263 #define LCD_CTRL_BPP_4  (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2264 #define LCD_CTRL_BPP_8  (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2265 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2266 #define LCD_CTRL_BPP_18_24      (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2267
2268 /* LCD Status Register */
2269 #define LCD_STATE_QD            (1 << 7)        /* Quick Disable Done */
2270 #define LCD_STATE_EOF           (1 << 5)        /* EOF Flag */
2271 #define LCD_STATE_SOF           (1 << 4)        /* SOF Flag */
2272 #define LCD_STATE_OFU           (1 << 3)        /* Output FIFO Underrun */
2273 #define LCD_STATE_IFU0          (1 << 2)        /* Input FIFO 0 Underrun */
2274 #define LCD_STATE_IFU1          (1 << 1)        /* Input FIFO 1 Underrun */
2275 #define LCD_STATE_LDD           (1 << 0)        /* LCD Disabled */
2276
2277 /* DMA Command Register */
2278 #define LCD_CMD_SOFINT          (1 << 31)
2279 #define LCD_CMD_EOFINT          (1 << 30)
2280 #define LCD_CMD_PAL             (1 << 28)
2281 #define LCD_CMD_LEN_BIT         0
2282 #define LCD_CMD_LEN_MASK        (0xffffff << LCD_CMD_LEN_BIT)
2283
2284
2285 /*************************************************************************
2286  * USB Device
2287  *************************************************************************/
2288 #define USB_BASE  UDC_BASE
2289
2290 #define USB_REG_FADDR           (USB_BASE + 0x00)       /* Function Address 8-bit */
2291 #define USB_REG_POWER           (USB_BASE + 0x01)       /* Power Managemetn 8-bit */
2292 #define USB_REG_INTRIN          (USB_BASE + 0x02)       /* Interrupt IN 16-bit */
2293 #define USB_REG_INTROUT         (USB_BASE + 0x04)       /* Interrupt OUT 16-bit */
2294 #define USB_REG_INTRINE         (USB_BASE + 0x06)       /* Intr IN enable 16-bit */
2295 #define USB_REG_INTROUTE        (USB_BASE + 0x08)       /* Intr OUT enable 16-bit */
2296 #define USB_REG_INTRUSB         (USB_BASE + 0x0a)       /* Interrupt USB 8-bit */
2297 #define USB_REG_INTRUSBE        (USB_BASE + 0x0b)       /* Interrupt USB Enable 8-bit */
2298 #define USB_REG_FRAME           (USB_BASE + 0x0c)       /* Frame number 16-bit */
2299 #define USB_REG_INDEX           (USB_BASE + 0x0e)       /* Index register 8-bit */
2300 #define USB_REG_TESTMODE        (USB_BASE + 0x0f)       /* USB test mode 8-bit */
2301
2302 #define USB_REG_CSR0            (USB_BASE + 0x12)       /* EP0 CSR 8-bit */
2303 #define USB_REG_INMAXP          (USB_BASE + 0x10)       /* EP1-2 IN Max Pkt Size 16-bit */
2304 #define USB_REG_INCSR           (USB_BASE + 0x12)       /* EP1-2 IN CSR LSB 8/16bit */
2305 #define USB_REG_INCSRH          (USB_BASE + 0x13)       /* EP1-2 IN CSR MSB 8-bit */
2306 #define USB_REG_OUTMAXP         (USB_BASE + 0x14)       /* EP1 OUT Max Pkt Size 16-bit */
2307 #define USB_REG_OUTCSR          (USB_BASE + 0x16)       /* EP1 OUT CSR LSB 8/16bit */
2308 #define USB_REG_OUTCSRH         (USB_BASE + 0x17)       /* EP1 OUT CSR MSB 8-bit */
2309 #define USB_REG_OUTCOUNT        (USB_BASE + 0x18)       /* bytes in EP0/1 OUT FIFO 16-bit */
2310
2311 #define USB_FIFO_EP0            (USB_BASE + 0x20)
2312 #define USB_FIFO_EP1            (USB_BASE + 0x24)
2313 #define USB_FIFO_EP2            (USB_BASE + 0x28)
2314
2315 #define USB_REG_EPINFO          (USB_BASE + 0x78)       /* Endpoint information */
2316 #define USB_REG_RAMINFO         (USB_BASE + 0x79)       /* RAM information */
2317
2318 #define USB_REG_INTR            (USB_BASE + 0x200)      /* DMA pending interrupts */
2319 #define USB_REG_CNTL1           (USB_BASE + 0x204)      /* DMA channel 1 control */
2320 #define USB_REG_ADDR1           (USB_BASE + 0x208)      /* DMA channel 1 AHB memory addr */
2321 #define USB_REG_COUNT1          (USB_BASE + 0x20c)      /* DMA channel 1 byte count */
2322 #define USB_REG_CNTL2           (USB_BASE + 0x214)      /* DMA channel 2 control */
2323 #define USB_REG_ADDR2           (USB_BASE + 0x218)      /* DMA channel 2 AHB memory addr */
2324 #define USB_REG_COUNT2          (USB_BASE + 0x21c)      /* DMA channel 2 byte count */
2325
2326
2327 /* Power register bit masks */
2328 #define USB_POWER_SUSPENDM      0x01
2329 #define USB_POWER_RESUME        0x04
2330 #define USB_POWER_HSMODE        0x10
2331 #define USB_POWER_HSENAB        0x20
2332 #define USB_POWER_SOFTCONN      0x40
2333
2334 /* Interrupt register bit masks */
2335 #define USB_INTR_SUSPEND        0x01
2336 #define USB_INTR_RESUME         0x02
2337 #define USB_INTR_RESET          0x04
2338
2339 #define USB_INTR_EP0            0x0001
2340 #define USB_INTR_INEP1          0x0002
2341 #define USB_INTR_INEP2          0x0004
2342 #define USB_INTR_OUTEP1         0x0002
2343
2344 /* CSR0 bit masks */
2345 #define USB_CSR0_OUTPKTRDY      0x01
2346 #define USB_CSR0_INPKTRDY       0x02
2347 #define USB_CSR0_SENTSTALL      0x04
2348 #define USB_CSR0_DATAEND        0x08
2349 #define USB_CSR0_SETUPEND       0x10
2350 #define USB_CSR0_SENDSTALL      0x20
2351 #define USB_CSR0_SVDOUTPKTRDY   0x40
2352 #define USB_CSR0_SVDSETUPEND    0x80
2353
2354 /* Endpoint CSR register bits */
2355 #define USB_INCSRH_AUTOSET      0x80
2356 #define USB_INCSRH_ISO          0x40
2357 #define USB_INCSRH_MODE         0x20
2358 #define USB_INCSRH_DMAREQENAB   0x10
2359 #define USB_INCSRH_DMAREQMODE   0x04
2360 #define USB_INCSR_CDT           0x40
2361 #define USB_INCSR_SENTSTALL     0x20
2362 #define USB_INCSR_SENDSTALL     0x10
2363 #define USB_INCSR_FF            0x08
2364 #define USB_INCSR_UNDERRUN      0x04
2365 #define USB_INCSR_FFNOTEMPT     0x02
2366 #define USB_INCSR_INPKTRDY      0x01
2367 #define USB_OUTCSRH_AUTOCLR     0x80
2368 #define USB_OUTCSRH_ISO         0x40
2369 #define USB_OUTCSRH_DMAREQENAB  0x20
2370 #define USB_OUTCSRH_DNYT        0x10
2371 #define USB_OUTCSRH_DMAREQMODE  0x08
2372 #define USB_OUTCSR_CDT          0x80
2373 #define USB_OUTCSR_SENTSTALL    0x40
2374 #define USB_OUTCSR_SENDSTALL    0x20
2375 #define USB_OUTCSR_FF           0x10
2376 #define USB_OUTCSR_DATAERR      0x08
2377 #define USB_OUTCSR_OVERRUN      0x04
2378 #define USB_OUTCSR_FFFULL       0x02
2379 #define USB_OUTCSR_OUTPKTRDY    0x01
2380
2381 /* Testmode register bits */
2382 #define USB_TEST_SE0NAK         0x01
2383 #define USB_TEST_J              0x02
2384 #define USB_TEST_K              0x04
2385 #define USB_TEST_PACKET         0x08
2386
2387 /* DMA control bits */
2388 #define USB_CNTL_ENA            0x01
2389 #define USB_CNTL_DIR_IN         0x02
2390 #define USB_CNTL_MODE_1         0x04
2391 #define USB_CNTL_INTR_EN        0x08
2392 #define USB_CNTL_EP(n)          ((n) << 4)
2393 #define USB_CNTL_BURST_0        (0 << 9)
2394 #define USB_CNTL_BURST_4        (1 << 9)
2395 #define USB_CNTL_BURST_8        (2 << 9)
2396 #define USB_CNTL_BURST_16       (3 << 9)
2397
2398
2399 //----------------------------------------------------------------------
2400 //
2401 // Module Operation Definitions
2402 //
2403 //----------------------------------------------------------------------
2404 #ifndef __ASSEMBLY__
2405
2406 /***************************************************************************
2407  * GPIO
2408  ***************************************************************************/
2409
2410 //------------------------------------------------------
2411 // GPIO Pins Description
2412 //
2413 // PORT 0:
2414 //
2415 // PIN/BIT N            FUNC0           FUNC1
2416 //      0               D0              -
2417 //      1               D1              -
2418 //      2               D2              -
2419 //      3               D3              -
2420 //      4               D4              -
2421 //      5               D5              -
2422 //      6               D6              -
2423 //      7               D7              -
2424 //      8               D8              -
2425 //      9               D9              -
2426 //      10              D10             -
2427 //      11              D11             -
2428 //      12              D12             -
2429 //      13              D13             -
2430 //      14              D14             -
2431 //      15              D15             -
2432 //      16              D16             -
2433 //      17              D17             -
2434 //      18              D18             -
2435 //      19              D19             -
2436 //      20              D20             -
2437 //      21              D21             -
2438 //      22              D22             -
2439 //      23              D23             -
2440 //      24              D24             -
2441 //      25              D25             -
2442 //      26              D26             -
2443 //      27              D27             -
2444 //      28              D28             -
2445 //      29              D29             -
2446 //      30              D30             -
2447 //      31              D31             -
2448 //
2449 //------------------------------------------------------
2450 // PORT 1:
2451 //
2452 // PIN/BIT N            FUNC0           FUNC1
2453 //      0               A0              -
2454 //      1               A1              -
2455 //      2               A2              -
2456 //      3               A3              -
2457 //      4               A4              -
2458 //      5               A5              -
2459 //      6               A6              -
2460 //      7               A7              -
2461 //      8               A8              -
2462 //      9               A9              -
2463 //      10              A10             -
2464 //      11              A11             -
2465 //      12              A12             -
2466 //      13              A13             -
2467 //      14              A14             -
2468 //      15              A15/CL          -
2469 //      16              A16/AL          -
2470 //      17              LCD_CLS         A21
2471 //      18              LCD_SPL         A22
2472 //      19              DCS#            -
2473 //      20              RAS#            -
2474 //      21              CAS#            -
2475 //      22              RDWE#/BUFD#     -
2476 //      23              CKE             -
2477 //      24              CKO             -
2478 //      25              CS1#            -
2479 //      26              CS2#            -
2480 //      27              CS3#            -
2481 //      28              CS4#            -
2482 //      29              RD#             -
2483 //      30              WR#             -
2484 //      31              WE0#            -
2485 //
2486 // Note: PIN15&16 are CL&AL when connecting to NAND flash.
2487 //------------------------------------------------------
2488 // PORT 2:
2489 //
2490 // PIN/BIT N            FUNC0           FUNC1
2491 //      0               LCD_D0          -
2492 //      1               LCD_D1          -
2493 //      2               LCD_D2          -
2494 //      3               LCD_D3          -
2495 //      4               LCD_D4          -
2496 //      5               LCD_D5          -
2497 //      6               LCD_D6          -
2498 //      7               LCD_D7          -
2499 //      8               LCD_D8          -
2500 //      9               LCD_D9          -
2501 //      10              LCD_D10         -
2502 //      11              LCD_D11         -
2503 //      12              LCD_D12         -
2504 //      13              LCD_D13         -
2505 //      14              LCD_D14         -
2506 //      15              LCD_D15         -
2507 //      16              LCD_D16         -
2508 //      17              LCD_D17         -
2509 //      18              LCD_PCLK        -
2510 //      19              LCD_HSYNC       -
2511 //      20              LCD_VSYNC       -
2512 //      21              LCD_DE          -
2513 //      22              LCD_PS          A19
2514 //      23              LCD_REV         A20
2515 //      24              WE1#            -
2516 //      25              WE2#            -
2517 //      26              WE3#            -
2518 //      27              WAIT#           -
2519 //      28              FRE#            -
2520 //      29              FWE#            -
2521 //      30(NOTE:FRB#)   -               -
2522 //      31              -               -
2523 //
2524 // NOTE(1): PIN30 is used for FRB# when connecting to NAND flash.
2525 //------------------------------------------------------
2526 // PORT 3:
2527 //
2528 // PIN/BIT N            FUNC0           FUNC1
2529 //      0               CIM_D0          -
2530 //      1               CIM_D1          -
2531 //      2               CIM_D2          -
2532 //      3               CIM_D3          -
2533 //      4               CIM_D4          -
2534 //      5               CIM_D5          -
2535 //      6               CIM_D6          -
2536 //      7               CIM_D7          -
2537 //      8               MSC_CMD         -
2538 //      9               MSC_CLK         -
2539 //      10              MSC_D0          -
2540 //      11              MSC_D1          -
2541 //      12              MSC_D2          -
2542 //      13              MSC_D3          -
2543 //      14              CIM_MCLK        -
2544 //      15              CIM_PCLK        -
2545 //      16              CIM_VSYNC       -
2546 //      17              CIM_HSYNC       -
2547 //      18              SSI_CLK         SCLK_RSTN
2548 //      19              SSI_CE0#        BIT_CLK(AIC)
2549 //      20              SSI_DT          SDATA_OUT(AIC)
2550 //      21              SSI_DR          SDATA_IN(AIC)
2551 //      22              SSI_CE1#&GPC    SYNC(AIC)
2552 //      23              PWM0            I2C_SDA
2553 //      24              PWM1            I2C_SCK
2554 //      25              PWM2            UART0_TxD
2555 //      26              PWM3            UART0_RxD
2556 //      27              PWM4            A17
2557 //      28              PWM5            A18
2558 //      29              -               -
2559 //      30              PWM6            UART0_CTS/UART1_RxD
2560 //      31              PWM7            UART0_RTS/UART1_TxD
2561 //
2562 //////////////////////////////////////////////////////////
2563
2564 /*
2565  * p is the port number (0,1,2,3)
2566  * o is the pin offset (0-31) inside the port
2567  * n is the absolute number of a pin (0-127), regardless of the port
2568  */
2569
2570 //-------------------------------------------
2571 // Function Pins Mode
2572
2573 #define __gpio_as_func0(n)                      \
2574 do {                                            \
2575         unsigned int p, o;                      \
2576         p = (n) / 32;                           \
2577         o = (n) % 32;                           \
2578         REG_GPIO_PXFUNS(p) = (1 << o);          \
2579         REG_GPIO_PXSELC(p) = (1 << o);          \
2580 } while (0)
2581
2582 #define __gpio_as_func1(n)                      \
2583 do {                                            \
2584         unsigned int p, o;                      \
2585         p = (n) / 32;                           \
2586         o = (n) % 32;                           \
2587         REG_GPIO_PXFUNS(p) = (1 << o);          \
2588         REG_GPIO_PXSELS(p) = (1 << o);          \
2589 } while (0)
2590
2591 /*
2592  * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2593  * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2594  */
2595 #define __gpio_as_sdram_32bit()                 \
2596 do {                                            \
2597         REG_GPIO_PXFUNS(0) = 0xffffffff;        \
2598         REG_GPIO_PXSELC(0) = 0xffffffff;        \
2599         REG_GPIO_PXFUNS(1) = 0x81f9ffff;        \
2600         REG_GPIO_PXSELC(1) = 0x81f9ffff;        \
2601         REG_GPIO_PXFUNS(2) = 0x07000000;        \
2602         REG_GPIO_PXSELC(2) = 0x07000000;        \
2603 } while (0)
2604
2605 /*
2606  * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2607  * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2608  */
2609 #define __gpio_as_sdram_16bit()                 \
2610 do {                                            \
2611         REG_GPIO_PXFUNS(0) = 0x5442bfaa;        \
2612         REG_GPIO_PXSELC(0) = 0x5442bfaa;        \
2613         REG_GPIO_PXPES(0) = 0x5442bfaa;         \
2614         REG_GPIO_PXFUNS(1) = 0x81f9ffff;        \
2615         REG_GPIO_PXSELC(1) = 0x81f9ffff;        \
2616         REG_GPIO_PXPES(1) = 0x81f9ffff;         \
2617         REG_GPIO_PXFUNS(2) = 0x01000000;        \
2618         REG_GPIO_PXSELC(2) = 0x01000000;        \
2619         REG_GPIO_PXPES(2) = 0x01000000;         \
2620 } while (0)
2621
2622 /*
2623  * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
2624  */
2625 #define __gpio_as_nand()                        \
2626 do {                                            \
2627         REG_GPIO_PXFUNS(1) = 0x02018000;        \
2628         REG_GPIO_PXSELC(1) = 0x02018000;        \
2629         REG_GPIO_PXFUNS(2) = 0x30000000;        \
2630         REG_GPIO_PXSELC(2) = 0x30000000;        \
2631         REG_GPIO_PXFUNC(2) = 0x40000000;        \
2632         REG_GPIO_PXSELC(2) = 0x40000000;        \
2633         REG_GPIO_PXDIRC(2) = 0x40000000;                \
2634         REG_GPIO_PXFUNS(1) = 0x00400000;        \
2635 } while (0)
2636
2637 /*
2638  * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
2639  */
2640 #define __gpio_as_nor_8bit()                    \
2641 do {                                            \
2642         REG_GPIO_PXFUNS(0) = 0x000000ff;        \
2643         REG_GPIO_PXSELC(0) = 0x000000ff;        \
2644         REG_GPIO_PXPES(0) = 0x000000ff;         \
2645         REG_GPIO_PXFUNS(1) = 0x7041ffff;        \
2646         REG_GPIO_PXSELC(1) = 0x7041ffff;        \
2647         REG_GPIO_PXPES(1) = 0x7041ffff;         \
2648         REG_GPIO_PXFUNS(1) = 0x00060000;        \
2649         REG_GPIO_PXSELS(1) = 0x00060000;        \
2650         REG_GPIO_PXPES(1) = 0x00060000;         \
2651         REG_GPIO_PXFUNS(2) = 0x08000000;        \
2652         REG_GPIO_PXSELC(2) = 0x08000000;        \
2653         REG_GPIO_PXPES(2) = 0x08000000;         \
2654         REG_GPIO_PXFUNS(2) = 0x00c00000;        \
2655         REG_GPIO_PXSELS(2) = 0x00c00000;        \
2656         REG_GPIO_PXPES(2) = 0x00c00000;         \
2657         REG_GPIO_PXFUNS(3) = 0x18000000;        \
2658         REG_GPIO_PXSELS(3) = 0x18000000;        \
2659         REG_GPIO_PXPES(3) = 0x18000000;         \
2660 } while (0)
2661
2662 /*
2663  * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
2664  */
2665 #define __gpio_as_nor_16bit()                   \
2666 do {                                            \
2667         REG_GPIO_PXFUNS(0) = 0x0000ffff;        \
2668         REG_GPIO_PXSELC(0) = 0x0000ffff;        \
2669         REG_GPIO_PXPES(0) = 0x0000ffff;         \
2670         REG_GPIO_PXFUNS(1) = 0x7041ffff;        \
2671         REG_GPIO_PXSELC(1) = 0x7041ffff;        \
2672         REG_GPIO_PXPES(1) = 0x7041ffff;         \
2673         REG_GPIO_PXFUNS(1) = 0x00060000;        \
2674         REG_GPIO_PXSELS(1) = 0x00060000;        \
2675         REG_GPIO_PXPES(1) = 0x00060000;         \
2676         REG_GPIO_PXFUNS(2) = 0x08000000;        \
2677         REG_GPIO_PXSELC(2) = 0x08000000;        \
2678         REG_GPIO_PXPES(2) = 0x08000000;         \
2679         REG_GPIO_PXFUNS(2) = 0x00c00000;        \
2680         REG_GPIO_PXSELS(2) = 0x00c00000;        \
2681         REG_GPIO_PXPES(2) = 0x00c00000;         \
2682         REG_GPIO_PXFUNS(3) = 0x18000000;        \
2683         REG_GPIO_PXSELS(3) = 0x18000000;        \
2684         REG_GPIO_PXPES(3) = 0x18000000;         \
2685 } while (0)
2686
2687 /*
2688  * UART0_TxD, UART_RxD0
2689  */
2690 #define __gpio_as_uart0()                       \
2691 do {                                            \
2692         REG_GPIO_PXFUNS(3) = 0x06000000;        \
2693         REG_GPIO_PXSELS(3) = 0x06000000;        \
2694 } while (0)
2695
2696 /*
2697  * UART1_TxD, UART1_RxD1
2698  */
2699 #define __gpio_as_uart1()                       \
2700 do {                                            \
2701         REG_GPIO_PXFUNS(3) = 0xc0000000;        \
2702         REG_GPIO_PXSELS(3) = 0xc0000000;        \
2703         REG_GPIO_PXPES(3) = 0xc0000000;         \
2704 } while (0)
2705
2706 /*
2707  * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2708  */
2709 #define __gpio_as_lcd_16bit()                   \
2710 do {                                            \
2711         REG_GPIO_PXFUNS(2) = 0x003cffff;        \
2712         REG_GPIO_PXSELC(2) = 0x003cffff;        \
2713         REG_GPIO_PXPES(2) = 0x003cffff;         \
2714 } while (0)
2715
2716 /*
2717  * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2718  */
2719 #define __gpio_as_lcd_18bit()                   \
2720 do {                                            \
2721         REG_GPIO_PXFUNS(2) = 0x003fffff;        \
2722         REG_GPIO_PXSELC(2) = 0x003fffff;        \
2723         REG_GPIO_PXPES(2) = 0x003fffff;         \
2724 } while (0)
2725
2726 /*
2727  * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
2728  */
2729 #define __gpio_as_cim()                         \
2730 do {                                            \
2731         REG_GPIO_PXFUNS(3) = 0x0003c0ff;        \
2732         REG_GPIO_PXSELC(3) = 0x0003c0ff;        \
2733         REG_GPIO_PXPES(3) = 0x0003c0ff;         \
2734 } while (0)
2735
2736 /*
2737  * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET
2738  */
2739 #define __gpio_as_aic()                         \
2740 do {                                            \
2741         REG_GPIO_PXFUNS(3) = 0x007c0000;        \
2742         REG_GPIO_PXSELS(3) = 0x007c0000;        \
2743         REG_GPIO_PXPES(3) = 0x007c0000;         \
2744 } while (0)
2745
2746 /*
2747  * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
2748  */
2749 #define __gpio_as_msc()                         \
2750 do {                                            \
2751         REG_GPIO_PXFUNS(3) = 0x00003f00;        \
2752         REG_GPIO_PXSELC(3) = 0x00003f00;        \
2753         REG_GPIO_PXPES(3) = 0x00003f00;         \
2754 } while (0)
2755
2756 /*
2757  * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR
2758  */
2759 #define __gpio_as_ssi()                         \
2760 do {                                            \
2761         REG_GPIO_PXFUNS(3) = 0x003c0000;        \
2762         REG_GPIO_PXSELC(3) = 0x003c0000;        \
2763         REG_GPIO_PXPES(3) = 0x003c0000;         \
2764 } while (0)
2765
2766 /*
2767  * I2C_SCK, I2C_SDA
2768  */
2769 #define __gpio_as_i2c()                         \
2770 do {                                            \
2771         REG_GPIO_PXFUNS(3) = 0x01800000;        \
2772         REG_GPIO_PXSELS(3) = 0x01800000;        \
2773         REG_GPIO_PXPES(3) = 0x01800000;         \
2774 } while (0)
2775
2776 /*
2777  * PWM0
2778  */
2779 #define __gpio_as_pwm0()                        \
2780 do {                                            \
2781         REG_GPIO_PXFUNS(3) = 0x00800000;        \
2782         REG_GPIO_PXSELC(3) = 0x00800000;        \
2783         REG_GPIO_PXPES(3) = 0x00800000;         \
2784 } while (0)
2785
2786 /*
2787  * PWM1
2788  */
2789 #define __gpio_as_pwm1()                        \
2790 do {                                            \
2791         REG_GPIO_PXFUNS(3) = 0x01000000;        \
2792         REG_GPIO_PXSELC(3) = 0x01000000;        \
2793         REG_GPIO_PXPES(3) = 0x01000000;         \
2794 } while (0)
2795
2796 /*
2797  * PWM2
2798  */
2799 #define __gpio_as_pwm2()                        \
2800 do {                                            \
2801         REG_GPIO_PXFUNS(3) = 0x02000000;        \
2802         REG_GPIO_PXSELC(3) = 0x02000000;        \
2803         REG_GPIO_PXPES(3) = 0x02000000;         \
2804 } while (0)
2805
2806 /*
2807  * PWM3
2808  */
2809 #define __gpio_as_pwm3()                        \
2810 do {                                            \
2811         REG_GPIO_PXFUNS(3) = 0x04000000;        \
2812         REG_GPIO_PXSELC(3) = 0x04000000;        \
2813         REG_GPIO_PXPES(3) = 0x04000000;         \
2814 } while (0)
2815
2816 /*
2817  * PWM4
2818  */
2819 #define __gpio_as_pwm4()                        \
2820 do {                                            \
2821         REG_GPIO_PXFUNS(3) = 0x08000000;        \
2822         REG_GPIO_PXSELC(3) = 0x08000000;        \
2823         REG_GPIO_PXPES(3) = 0x08000000;         \
2824 } while (0)
2825
2826 /*
2827  * PWM5
2828  */
2829 #define __gpio_as_pwm5()                        \
2830 do {                                            \
2831         REG_GPIO_PXFUNS(3) = 0x10000000;        \
2832         REG_GPIO_PXSELC(3) = 0x10000000;        \
2833         REG_GPIO_PXPES(3) = 0x10000000;         \
2834 } while (0)
2835
2836 /*
2837  * PWM6
2838  */
2839 #define __gpio_as_pwm6()                        \
2840 do {                                            \
2841         REG_GPIO_PXFUNS(3) = 0x40000000;        \
2842         REG_GPIO_PXSELC(3) = 0x40000000;        \
2843         REG_GPIO_PXPES(3) = 0x40000000;         \
2844 } while (0)
2845
2846 /*
2847  * PWM7
2848  */
2849 #define __gpio_as_pwm7()                        \
2850 do {                                            \
2851         REG_GPIO_PXFUNS(3) = 0x80000000;        \
2852         REG_GPIO_PXSELC(3) = 0x80000000;        \
2853         REG_GPIO_PXPES(3) = 0x80000000;         \
2854 } while (0)
2855
2856 /*
2857  * n = 0 ~ 7
2858  */
2859 #define __gpio_as_pwm(n)        __gpio_as_pwm##n()
2860
2861 //-------------------------------------------
2862 // GPIO or Interrupt Mode
2863
2864 #define __gpio_get_port(p)      (REG_GPIO_PXPIN(p))
2865
2866 #define __gpio_port_as_output(p, o)             \
2867 do {                                            \
2868     REG_GPIO_PXFUNC(p) = (1 << (o));            \
2869     REG_GPIO_PXSELC(p) = (1 << (o));            \
2870     REG_GPIO_PXDIRS(p) = (1 << (o));            \
2871 } while (0)
2872
2873 #define __gpio_port_as_input(p, o)              \
2874 do {                                            \
2875     REG_GPIO_PXFUNC(p) = (1 << (o));            \
2876     REG_GPIO_PXSELC(p) = (1 << (o));            \
2877     REG_GPIO_PXDIRC(p) = (1 << (o));            \
2878 } while (0)
2879
2880 #define __gpio_as_output(n)                     \
2881 do {                                            \
2882         unsigned int p, o;                      \
2883         p = (n) / 32;                           \
2884         o = (n) % 32;                           \
2885         __gpio_port_as_output(p, o);            \
2886 } while (0)
2887
2888 #define __gpio_as_input(n)                      \
2889 do {                                            \
2890         unsigned int p, o;                      \
2891         p = (n) / 32;                           \
2892         o = (n) % 32;                           \
2893         __gpio_port_as_input(p, o);             \
2894 } while (0)
2895
2896 #define __gpio_set_pin(n)                       \
2897 do {                                            \
2898         unsigned int p, o;                      \
2899         p = (n) / 32;                           \
2900         o = (n) % 32;                           \
2901         REG_GPIO_PXDATS(p) = (1 << o);          \
2902 } while (0)
2903
2904 #define __gpio_clear_pin(n)                     \
2905 do {                                            \
2906         unsigned int p, o;                      \
2907         p = (n) / 32;                           \
2908         o = (n) % 32;                           \
2909         REG_GPIO_PXDATC(p) = (1 << o);          \
2910 } while (0)
2911
2912 #define __gpio_get_pin(n)                       \
2913 ({                                              \
2914         unsigned int p, o, v;                   \
2915         p = (n) / 32;                           \
2916         o = (n) % 32;                           \
2917         if (__gpio_get_port(p) & (1 << o))      \
2918                 v = 1;                          \
2919         else                                    \
2920                 v = 0;                          \
2921         v;                                      \
2922 })
2923
2924 #define __gpio_as_irq_high_level(n)             \
2925 do {                                            \
2926         unsigned int p, o;                      \
2927         p = (n) / 32;                           \
2928         o = (n) % 32;                           \
2929         REG_GPIO_PXIMS(p) = (1 << o);           \
2930         REG_GPIO_PXTRGC(p) = (1 << o);          \
2931         REG_GPIO_PXFUNC(p) = (1 << o);          \
2932         REG_GPIO_PXSELS(p) = (1 << o);          \
2933         REG_GPIO_PXDIRS(p) = (1 << o);          \
2934         REG_GPIO_PXFLGC(p) = (1 << o);          \
2935         REG_GPIO_PXIMC(p) = (1 << o);           \
2936 } while (0)
2937
2938 #define __gpio_as_irq_low_level(n)              \
2939 do {                                            \
2940         unsigned int p, o;                      \
2941         p = (n) / 32;                           \
2942         o = (n) % 32;                           \
2943         REG_GPIO_PXIMS(p) = (1 << o);           \
2944         REG_GPIO_PXTRGC(p) = (1 << o);          \
2945         REG_GPIO_PXFUNC(p) = (1 << o);          \
2946         REG_GPIO_PXSELS(p) = (1 << o);          \
2947         REG_GPIO_PXDIRC(p) = (1 << o);          \
2948         REG_GPIO_PXFLGC(p) = (1 << o);          \
2949         REG_GPIO_PXIMC(p) = (1 << o);           \
2950 } while (0)
2951
2952 #define __gpio_as_irq_rise_edge(n)              \
2953 do {                                            \
2954         unsigned int p, o;                      \
2955         p = (n) / 32;                           \
2956         o = (n) % 32;                           \
2957         REG_GPIO_PXIMS(p) = (1 << o);           \
2958         REG_GPIO_PXTRGS(p) = (1 << o);          \
2959         REG_GPIO_PXFUNC(p) = (1 << o);          \
2960         REG_GPIO_PXSELS(p) = (1 << o);          \
2961         REG_GPIO_PXDIRS(p) = (1 << o);          \
2962         REG_GPIO_PXFLGC(p) = (1 << o);          \
2963         REG_GPIO_PXIMC(p) = (1 << o);           \
2964 } while (0)
2965
2966 #define __gpio_as_irq_fall_edge(n)              \
2967 do {                                            \
2968         unsigned int p, o;                      \
2969         p = (n) / 32;                           \
2970         o = (n) % 32;                           \
2971         REG_GPIO_PXIMS(p) = (1 << o);           \
2972         REG_GPIO_PXTRGS(p) = (1 << o);          \
2973         REG_GPIO_PXFUNC(p) = (1 << o);          \
2974         REG_GPIO_PXSELS(p) = (1 << o);          \
2975         REG_GPIO_PXDIRC(p) = (1 << o);          \
2976         REG_GPIO_PXFLGC(p) = (1 << o);          \
2977         REG_GPIO_PXIMC(p) = (1 << o);           \
2978 } while (0)
2979
2980 #define __gpio_mask_irq(n)                      \
2981 do {                                            \
2982         unsigned int p, o;                      \
2983         p = (n) / 32;                           \
2984         o = (n) % 32;                           \
2985         REG_GPIO_PXIMS(p) = (1 << o);           \
2986 } while (0)
2987
2988 #define __gpio_unmask_irq(n)                    \
2989 do {                                            \
2990         unsigned int p, o;                      \
2991         p = (n) / 32;                           \
2992         o = (n) % 32;                           \
2993         REG_GPIO_PXIMC(p) = (1 << o);           \
2994 } while (0)
2995
2996 #define __gpio_ack_irq(n)                       \
2997 do {                                            \
2998         unsigned int p, o;                      \
2999         p = (n) / 32;                           \
3000         o = (n) % 32;                           \
3001         REG_GPIO_PXFLGC(p) = (1 << o);          \
3002 } while (0)
3003
3004 #define __gpio_get_irq()                        \
3005 ({                                              \
3006         unsigned int p, i, tmp, v = 0;          \
3007         for (p = 3; p >= 0; p--) {              \
3008                 tmp = REG_GPIO_PXFLG(p);        \
3009                 for (i = 0; i < 32; i++)        \
3010                         if (tmp & (1 << i))     \
3011                                 v = (32*p + i); \
3012         }                                       \
3013         v;                                      \
3014 })
3015
3016 #define __gpio_group_irq(n)                     \
3017 ({                                              \
3018         register int tmp, i;                    \
3019         tmp = REG_GPIO_PXFLG((n));              \
3020         for (i=31;i>=0;i--)                     \
3021                 if (tmp & (1 << i))             \
3022                         break;                  \
3023         i;                                      \
3024 })
3025
3026 #define __gpio_enable_pull(n)                   \
3027 do {                                            \
3028         unsigned int p, o;                      \
3029         p = (n) / 32;                           \
3030         o = (n) % 32;                           \
3031         REG_GPIO_PXPEC(p) = (1 << o);           \
3032 } while (0)
3033
3034 #define __gpio_disable_pull(n)                  \
3035 do {                                            \
3036         unsigned int p, o;                      \
3037         p = (n) / 32;                           \
3038         o = (n) % 32;                           \
3039         REG_GPIO_PXPES(p) = (1 << o);           \
3040 } while (0)
3041
3042
3043 /***************************************************************************
3044  * CPM
3045  ***************************************************************************/
3046 #define __cpm_get_pllm() \
3047         ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
3048 #define __cpm_get_plln() \
3049         ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
3050 #define __cpm_get_pllod() \
3051         ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
3052
3053 #define __cpm_get_cdiv() \
3054         ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
3055 #define __cpm_get_hdiv() \
3056         ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
3057 #define __cpm_get_pdiv() \
3058         ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
3059 #define __cpm_get_mdiv() \
3060         ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
3061 #define __cpm_get_ldiv() \
3062         ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
3063 #define __cpm_get_udiv() \
3064         ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
3065 #define __cpm_get_i2sdiv() \
3066         ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
3067 #define __cpm_get_pixdiv() \
3068         ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
3069 #define __cpm_get_mscdiv() \
3070         ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
3071
3072 #define __cpm_set_cdiv(v) \
3073         (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
3074 #define __cpm_set_hdiv(v) \
3075         (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
3076 #define __cpm_set_pdiv(v) \
3077         (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
3078 #define __cpm_set_mdiv(v) \
3079         (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
3080 #define __cpm_set_ldiv(v) \
3081         (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
3082 #define __cpm_set_udiv(v) \
3083         (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
3084 #define __cpm_set_i2sdiv(v) \
3085         (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
3086 #define __cpm_set_pixdiv(v) \
3087         (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
3088 #define __cpm_set_mscdiv(v) \
3089         (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
3090
3091 #define __cpm_select_i2sclk_exclk()     (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
3092 #define __cpm_select_i2sclk_pll()       (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
3093 #define __cpm_enable_cko()              (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
3094 #define __cpm_select_usbclk_exclk()     (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
3095 #define __cpm_select_usbclk_pll()       (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
3096 #define __cpm_enable_pll_change()       (REG_CPM_CPCCR |= CPM_CPCCR_CE)
3097 #define __cpm_pllout_direct()           (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
3098 #define __cpm_pllout_div2()             (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
3099
3100 #define __cpm_pll_is_on()               (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
3101 #define __cpm_pll_bypass()              (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
3102 #define __cpm_pll_enable()              (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
3103
3104 #define __cpm_get_cclk_doze_duty() \
3105         ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
3106 #define __cpm_set_cclk_doze_duty(v) \
3107         (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
3108
3109 #define __cpm_doze_mode()               (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
3110 #define __cpm_idle_mode() \
3111         (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
3112 #define __cpm_sleep_mode() \
3113         (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
3114
3115 #define __cpm_stop_all()        (REG_CPM_CLKGR = 0x7fff)
3116 #define __cpm_stop_uart1()      (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
3117 #define __cpm_stop_uhc()        (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
3118 #define __cpm_stop_ipu()        (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
3119 #define __cpm_stop_dmac()       (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
3120 #define __cpm_stop_udc()        (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
3121 #define __cpm_stop_lcd()        (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
3122 #define __cpm_stop_cim()        (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
3123 #define __cpm_stop_sadc()       (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
3124 #define __cpm_stop_msc()        (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
3125 #define __cpm_stop_aic1()       (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
3126 #define __cpm_stop_aic2()       (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
3127 #define __cpm_stop_ssi()        (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
3128 #define __cpm_stop_i2c()        (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
3129 #define __cpm_stop_rtc()        (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
3130 #define __cpm_stop_tcu()        (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
3131 #define __cpm_stop_uart0()      (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
3132
3133 #define __cpm_start_all()       (REG_CPM_CLKGR = 0x0)
3134 #define __cpm_start_uart1()     (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
3135 #define __cpm_start_uhc()       (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
3136 #define __cpm_start_ipu()       (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
3137 #define __cpm_start_dmac()      (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
3138 #define __cpm_start_udc()       (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
3139 #define __cpm_start_lcd()       (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
3140 #define __cpm_start_cim()       (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
3141 #define __cpm_start_sadc()      (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
3142 #define __cpm_start_msc()       (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
3143 #define __cpm_start_aic1()      (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
3144 #define __cpm_start_aic2()      (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
3145 #define __cpm_start_ssi()       (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
3146 #define __cpm_start_i2c()       (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
3147 #define __cpm_start_rtc()       (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
3148 #define __cpm_start_tcu()       (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
3149 #define __cpm_start_uart0()     (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
3150
3151 #define __cpm_get_o1st() \
3152         ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
3153 #define __cpm_set_o1st(v) \
3154         (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
3155 #define __cpm_suspend_usbphy()          (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
3156 #define __cpm_enable_osc_in_sleep()     (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
3157
3158
3159 #ifdef CFG_EXTAL
3160 #define JZ_EXTAL                CFG_EXTAL
3161 #else
3162 #define JZ_EXTAL                3686400
3163 #endif
3164 #define JZ_EXTAL2               32768   /* RTC clock */
3165
3166 /* PLL output frequency */
3167 static __inline__ unsigned int __cpm_get_pllout(void)
3168 {
3169     unsigned long m, n, no, pllout;
3170     unsigned long cppcr = REG_CPM_CPPCR;
3171     unsigned long od[4] = { 1, 2, 2, 4 };
3172     if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP))
3173     {
3174         m = __cpm_get_pllm() + 2;
3175         n = __cpm_get_plln() + 2;
3176         no = od[__cpm_get_pllod()];
3177         pllout = ((JZ_EXTAL) / (n * no)) * m;
3178     }
3179     else
3180         pllout = JZ_EXTAL;
3181     return pllout;
3182 }
3183
3184 /* PLL output frequency for MSC/I2S/LCD/USB */
3185 static __inline__ unsigned int __cpm_get_pllout2(void)
3186 {
3187     if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
3188         return __cpm_get_pllout();
3189     else
3190         return __cpm_get_pllout() / 2;
3191 }
3192
3193 /* CPU core clock */
3194 static __inline__ unsigned int __cpm_get_cclk(void)
3195 {
3196     int div[] = { 1, 2, 3, 4, 6, 8, 12, 16, 24, 32 };
3197
3198     return __cpm_get_pllout() / div[__cpm_get_cdiv()];
3199 }
3200
3201 /* AHB system bus clock */
3202 static __inline__ unsigned int __cpm_get_hclk(void)
3203 {
3204     int div[] = { 1, 2, 3, 4, 6, 8, 12, 16, 24, 32 };
3205
3206     return __cpm_get_pllout() / div[__cpm_get_hdiv()];
3207 }
3208
3209 /* Memory bus clock */
3210 static __inline__ unsigned int __cpm_get_mclk(void)
3211 {
3212     int div[] = { 1, 2, 3, 4, 6, 8, 12, 16, 24, 32 };
3213
3214     return __cpm_get_pllout() / div[__cpm_get_mdiv()];
3215 }
3216
3217 /* APB peripheral bus clock */
3218 static __inline__ unsigned int __cpm_get_pclk(void)
3219 {
3220     int div[] = { 1, 2, 3, 4, 6, 8, 12, 16, 24, 32 };
3221
3222     return __cpm_get_pllout() / div[__cpm_get_pdiv()];
3223 }
3224
3225 /* LCDC module clock */
3226 static __inline__ unsigned int __cpm_get_lcdclk(void)
3227 {
3228     return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
3229 }
3230
3231 /* LCD pixel clock */
3232 static __inline__ unsigned int __cpm_get_pixclk(void)
3233 {
3234     return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
3235 }
3236
3237 /* I2S clock */
3238 static __inline__ unsigned int __cpm_get_i2sclk(void)
3239 {
3240     if (REG_CPM_CPCCR & CPM_CPCCR_I2CS)
3241     {
3242         return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
3243     }
3244     else
3245     {
3246         return JZ_EXTAL;
3247     }
3248 }
3249
3250 /* USB clock */
3251 static __inline__ unsigned int __cpm_get_usbclk(void)
3252 {
3253     if (REG_CPM_CPCCR & CPM_CPCCR_UCS)
3254     {
3255         return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
3256     }
3257     else
3258     {
3259         return JZ_EXTAL;
3260     }
3261 }
3262
3263 /* MSC clock */
3264 static __inline__ unsigned int __cpm_get_mscclk(void)
3265 {
3266     return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
3267 }
3268
3269 /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
3270 static __inline__ unsigned int __cpm_get_extalclk(void)
3271 {
3272     return JZ_EXTAL;
3273 }
3274
3275 /* RTC clock for CPM,INTC,RTC,TCU,WDT */
3276 static __inline__ unsigned int __cpm_get_rtcclk(void)
3277 {
3278     return JZ_EXTAL2;
3279 }
3280
3281 /*
3282  * Output 24MHz for SD and 16MHz for MMC.
3283  */
3284 static inline void __cpm_select_msc_clk(int sd)
3285 {
3286     unsigned int pllout2 = __cpm_get_pllout2();
3287     unsigned int div = 0;
3288
3289     if (sd)
3290     {
3291         div = pllout2 / 24000000;
3292     }
3293     else
3294     {
3295         div = pllout2 / 16000000;
3296     }
3297
3298     REG_CPM_MSCCDR = div - 1;
3299 }
3300
3301 /***************************************************************************
3302  * TCU
3303  ***************************************************************************/
3304 // where 'n' is the TCU channel
3305 #define __tcu_select_extalclk(n) \
3306         (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
3307 #define __tcu_select_rtcclk(n) \
3308         (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
3309 #define __tcu_select_pclk(n) \
3310         (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
3311
3312 #define __tcu_select_clk_div1(n) \
3313         (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
3314 #define __tcu_select_clk_div4(n) \
3315         (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
3316 #define __tcu_select_clk_div16(n) \
3317         (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
3318 #define __tcu_select_clk_div64(n) \
3319         (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
3320 #define __tcu_select_clk_div256(n) \
3321         (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
3322 #define __tcu_select_clk_div1024(n) \
3323         (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
3324
3325 #define __tcu_enable_pwm_output(n)      ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
3326 #define __tcu_disable_pwm_output(n)     ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
3327
3328 #define __tcu_init_pwm_output_high(n)   ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
3329 #define __tcu_init_pwm_output_low(n)    ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
3330
3331 #define __tcu_set_pwm_output_shutdown_graceful(n)       ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
3332 #define __tcu_set_pwm_output_shutdown_abrupt(n)         ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
3333
3334 #define __tcu_start_counter(n)          ( REG_TCU_TESR |= (1 << (n)) )
3335 #define __tcu_stop_counter(n)           ( REG_TCU_TECR |= (1 << (n)) )
3336
3337 #define __tcu_half_match_flag(n)        ( REG_TCU_TFR & (1 << ((n) + 16)) )
3338 #define __tcu_full_match_flag(n)        ( REG_TCU_TFR & (1 << (n)) )
3339 #define __tcu_set_half_match_flag(n)    ( REG_TCU_TFSR = (1 << ((n) + 16)) )
3340 #define __tcu_set_full_match_flag(n)    ( REG_TCU_TFSR = (1 << (n)) )
3341 #define __tcu_clear_half_match_flag(n)  ( REG_TCU_TFCR = (1 << ((n) + 16)) )
3342 #define __tcu_clear_full_match_flag(n)  ( REG_TCU_TFCR = (1 << (n)) )
3343 #define __tcu_mask_half_match_irq(n)    ( REG_TCU_TMSR = (1 << ((n) + 16)) )
3344 #define __tcu_mask_full_match_irq(n)    ( REG_TCU_TMSR = (1 << (n)) )
3345 #define __tcu_unmask_half_match_irq(n)  ( REG_TCU_TMCR = (1 << ((n) + 16)) )
3346 #define __tcu_unmask_full_match_irq(n)  ( REG_TCU_TMCR = (1 << (n)) )
3347
3348 #define __tcu_wdt_clock_stopped()       ( REG_TCU_TSR & TCU_TSSR_WDTSC )
3349 #define __tcu_timer_clock_stopped(n)    ( REG_TCU_TSR & (1 << (n)) )
3350
3351 #define __tcu_start_wdt_clock()         ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
3352 #define __tcu_start_timer_clock(n)      ( REG_TCU_TSCR = (1 << (n)) )
3353
3354 #define __tcu_stop_wdt_clock()          ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
3355 #define __tcu_stop_timer_clock(n)       ( REG_TCU_TSSR = (1 << (n)) )
3356
3357 #define __tcu_get_count(n)              ( REG_TCU_TCNT((n)) )
3358 #define __tcu_set_count(n,v)            ( REG_TCU_TCNT((n)) = (v) )
3359 #define __tcu_set_full_data(n,v)        ( REG_TCU_TDFR((n)) = (v) )
3360 #define __tcu_set_half_data(n,v)        ( REG_TCU_TDHR((n)) = (v) )
3361
3362
3363 /***************************************************************************
3364  * WDT
3365  ***************************************************************************/
3366 #define __wdt_start()                   ( REG_WDT_TCER |= WDT_TCER_TCEN )
3367 #define __wdt_stop()                    ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
3368 #define __wdt_set_count(v)              ( REG_WDT_TCNT = (v) )
3369 #define __wdt_set_data(v)               ( REG_WDT_TDR = (v) )
3370
3371 #define __wdt_select_extalclk() \
3372         (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
3373 #define __wdt_select_rtcclk() \
3374         (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
3375 #define __wdt_select_pclk() \
3376         (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
3377
3378 #define __wdt_select_clk_div1() \
3379         (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
3380 #define __wdt_select_clk_div4() \
3381         (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
3382 #define __wdt_select_clk_div16() \
3383         (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
3384 #define __wdt_select_clk_div64() \
3385         (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
3386 #define __wdt_select_clk_div256() \
3387         (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
3388 #define __wdt_select_clk_div1024() \
3389         (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
3390
3391
3392 /***************************************************************************
3393  * UART
3394  ***************************************************************************/
3395
3396 #define __uart_enable()                 ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
3397 #define __uart_disable()                ( REG8(UART0_FCR) = ~UARTFCR_UUE )
3398
3399 #define __uart_enable_transmit_irq()    ( REG8(UART0_IER) |= UARTIER_TIE )
3400 #define __uart_disable_transmit_irq()   ( REG8(UART0_IER) &= ~UARTIER_TIE )
3401
3402 #define __uart_enable_receive_irq() \
3403   ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
3404 #define __uart_disable_receive_irq() \
3405   ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
3406
3407 #define __uart_enable_loopback()        ( REG8(UART0_MCR) |= UARTMCR_LOOP )
3408 #define __uart_disable_loopback()       ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
3409
3410 #define __uart_set_8n1()                ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
3411
3412 #define __uart_set_baud(devclk, baud)                           \
3413   do {                                                          \
3414         REG8(UART0_LCR) |= UARTLCR_DLAB;                        \
3415         REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff;         \
3416         REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff;  \
3417         REG8(UART0_LCR) &= ~UARTLCR_DLAB;                       \
3418   } while (0)
3419
3420 #define __uart_parity_error()           ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
3421 #define __uart_clear_errors() \
3422   ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
3423
3424 #define __uart_transmit_fifo_empty()    ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
3425 #define __uart_transmit_end()           ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
3426 #define __uart_transmit_char(ch)        ( REG8(UART0_TDR) = (ch) )
3427 #define __uart_receive_fifo_full()      ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3428 #define __uart_receive_ready()          ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3429 #define __uart_receive_char()           REG8(UART0_RDR)
3430 #define __uart_disable_irda()           ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
3431 #define __uart_enable_irda() \
3432   /* Tx high pulse as 0, Rx low pulse as 0 */ \
3433   ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
3434
3435
3436 /***************************************************************************
3437  * DMAC
3438  ***************************************************************************/
3439
3440 /* n is the DMA channel (0 - 5) */
3441
3442 #define __dmac_enable_module() \
3443   ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR )
3444 #define __dmac_disable_module() \
3445   ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE )
3446
3447 /* p=0,1,2,3 */
3448 #define __dmac_set_priority(p)                          \
3449 do {                                                    \
3450         REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK;          \
3451         REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT);   \
3452 } while (0)
3453
3454 #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT )
3455 #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR )
3456
3457 #define __dmac_enable_descriptor(n) \
3458   ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
3459 #define __dmac_disable_descriptor(n) \
3460   ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
3461
3462 #define __dmac_enable_channel(n) \
3463   ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
3464 #define __dmac_disable_channel(n) \
3465   ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
3466 #define __dmac_channel_enabled(n) \
3467   ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
3468
3469 #define __dmac_channel_enable_irq(n) \
3470   ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
3471 #define __dmac_channel_disable_irq(n) \
3472   ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
3473
3474 #define __dmac_channel_transmit_halt_detected(n) \
3475   (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
3476 #define __dmac_channel_transmit_end_detected(n) \
3477   (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
3478 #define __dmac_channel_address_error_detected(n) \
3479   (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
3480 #define __dmac_channel_count_terminated_detected(n) \
3481   (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
3482 #define __dmac_channel_descriptor_invalid_detected(n) \
3483   (  REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
3484
3485 #define __dmac_channel_clear_transmit_halt(n) \
3486   (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
3487 #define __dmac_channel_clear_transmit_end(n) \
3488   (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
3489 #define __dmac_channel_clear_address_error(n) \
3490   (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
3491 #define __dmac_channel_clear_count_terminated(n) \
3492   (  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
3493 #define __dmac_channel_clear_descriptor_invalid(n) \
3494   (  REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
3495
3496 #define __dmac_channel_set_single_mode(n) \
3497   (  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM )
3498 #define __dmac_channel_set_block_mode(n) \
3499   (  REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM )
3500
3501 #define __dmac_channel_set_transfer_unit_32bit(n)       \
3502 do {                                                    \
3503         REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;       \
3504         REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT;       \
3505 } while (0)
3506
3507 #define __dmac_channel_set_transfer_unit_16bit(n)       \
3508 do {                                                    \
3509         REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;       \
3510         REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT;       \
3511 } while (0)
3512
3513 #define __dmac_channel_set_transfer_unit_8bit(n)        \
3514 do {                                                    \
3515         REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;       \
3516         REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT;        \
3517 } while (0)
3518
3519 #define __dmac_channel_set_transfer_unit_16byte(n)      \
3520 do {                                                    \
3521         REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;       \
3522         REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE;      \
3523 } while (0)
3524
3525 #define __dmac_channel_set_transfer_unit_32byte(n)      \
3526 do {                                                    \
3527         REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK;       \
3528         REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE;      \
3529 } while (0)
3530
3531 /* w=8,16,32 */
3532 #define __dmac_channel_set_dest_port_width(n,w)         \
3533 do {                                                    \
3534         REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK;     \
3535         REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w;       \
3536 } while (0)
3537
3538 /* w=8,16,32 */
3539 #define __dmac_channel_set_src_port_width(n,w)          \
3540 do {                                                    \
3541         REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK;     \
3542         REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w;       \
3543 } while (0)
3544
3545 /* v=0-15 */
3546 #define __dmac_channel_set_rdil(n,v)                            \
3547 do {                                                            \
3548         REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK;             \
3549         REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT);       \
3550 } while (0)
3551
3552 #define __dmac_channel_dest_addr_fixed(n) \
3553   (  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
3554 #define __dmac_channel_dest_addr_increment(n) \
3555   (  REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
3556
3557 #define __dmac_channel_src_addr_fixed(n) \
3558   (  REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
3559 #define __dmac_channel_src_addr_increment(n) \
3560   (  REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
3561
3562 #define __dmac_channel_set_doorbell(n) \
3563   (  REG_DMAC_DMADBSR = (1 << (n)) )
3564
3565 #define __dmac_channel_irq_detected(n)  ( REG_DMAC_DMAIPR & (1 << (n)) )
3566 #define __dmac_channel_ack_irq(n)       ( REG_DMAC_DMAIPR &= ~(1 << (n)) )
3567
3568 static __inline__ int __dmac_get_irq(void)
3569 {
3570     int i;
3571     for (i = 0; i < MAX_DMA_NUM; i++)
3572         if (__dmac_channel_irq_detected(i))
3573             return i;
3574     return -1;
3575 }
3576
3577
3578 /***************************************************************************
3579  * AIC (AC'97 & I2S Controller)
3580  ***************************************************************************/
3581
3582 #define __aic_enable()          ( REG_AIC_FR |= AIC_FR_ENB )
3583 #define __aic_disable()         ( REG_AIC_FR &= ~AIC_FR_ENB )
3584
3585 #define __aic_select_ac97()     ( REG_AIC_FR &= ~AIC_FR_AUSEL )
3586 #define __aic_select_i2s()      ( REG_AIC_FR |= AIC_FR_AUSEL )
3587
3588 #define __i2s_as_master()       ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
3589 #define __i2s_as_slave()        ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
3590 #define __aic_reset_status()          ( REG_AIC_FR & AIC_FR_RST )
3591
3592 #define __aic_reset()                                   \
3593 do {                                                    \
3594         REG_AIC_FR |= AIC_FR_RST;                       \
3595 } while(0)
3596
3597
3598 #define __aic_set_transmit_trigger(n)                   \
3599 do {                                                    \
3600         REG_AIC_FR &= ~AIC_FR_TFTH_MASK;                \
3601         REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT);         \
3602 } while(0)
3603
3604 #define __aic_set_receive_trigger(n)                    \
3605 do {                                                    \
3606         REG_AIC_FR &= ~AIC_FR_RFTH_MASK;                \
3607         REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT);         \
3608 } while(0)
3609
3610 #define __aic_enable_record()   ( REG_AIC_CR |= AIC_CR_EREC )
3611 #define __aic_disable_record()  ( REG_AIC_CR &= ~AIC_CR_EREC )
3612 #define __aic_enable_replay()   ( REG_AIC_CR |= AIC_CR_ERPL )
3613 #define __aic_disable_replay()  ( REG_AIC_CR &= ~AIC_CR_ERPL )
3614 #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
3615 #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
3616
3617 #define __aic_flush_fifo()      ( REG_AIC_CR |= AIC_CR_FLUSH )
3618 #define __aic_unflush_fifo()    ( REG_AIC_CR &= ~AIC_CR_FLUSH )
3619
3620 #define __aic_enable_transmit_intr() \
3621   ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
3622 #define __aic_disable_transmit_intr() \
3623   ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
3624 #define __aic_enable_receive_intr() \
3625   ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
3626 #define __aic_disable_receive_intr() \
3627   ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
3628
3629 #define __aic_enable_transmit_dma()  ( REG_AIC_CR |= AIC_CR_TDMS )
3630 #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
3631 #define __aic_enable_receive_dma()   ( REG_AIC_CR |= AIC_CR_RDMS )
3632 #define __aic_disable_receive_dma()  ( REG_AIC_CR &= ~AIC_CR_RDMS )
3633
3634 #define __aic_enable_mono2stereo()   ( REG_AIC_CR |= AIC_CR_M2S )
3635 #define __aic_disable_mono2stereo()  ( REG_AIC_CR &= ~AIC_CR_M2S )
3636 #define __aic_enable_byteswap()      ( REG_AIC_CR |= AIC_CR_ENDSW )
3637 #define __aic_disable_byteswap()     ( REG_AIC_CR &= ~AIC_CR_ENDSW )
3638 #define __aic_enable_unsignadj()     ( REG_AIC_CR |= AIC_CR_AVSTSU )
3639 #define __aic_disable_unsignadj()    ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
3640
3641 #define AC97_PCM_XS_L_FRONT     AIC_ACCR1_XS_SLOT3
3642 #define AC97_PCM_XS_R_FRONT     AIC_ACCR1_XS_SLOT4
3643 #define AC97_PCM_XS_CENTER      AIC_ACCR1_XS_SLOT6
3644 #define AC97_PCM_XS_L_SURR      AIC_ACCR1_XS_SLOT7
3645 #define AC97_PCM_XS_R_SURR      AIC_ACCR1_XS_SLOT8
3646 #define AC97_PCM_XS_LFE         AIC_ACCR1_XS_SLOT9
3647
3648 #define AC97_PCM_RS_L_FRONT     AIC_ACCR1_RS_SLOT3
3649 #define AC97_PCM_RS_R_FRONT     AIC_ACCR1_RS_SLOT4
3650 #define AC97_PCM_RS_CENTER      AIC_ACCR1_RS_SLOT6
3651 #define AC97_PCM_RS_L_SURR      AIC_ACCR1_RS_SLOT7
3652 #define AC97_PCM_RS_R_SURR      AIC_ACCR1_RS_SLOT8
3653 #define AC97_PCM_RS_LFE         AIC_ACCR1_RS_SLOT9
3654
3655 #define __ac97_set_xs_none()    ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
3656 #define __ac97_set_xs_mono()                                            \
3657 do {                                                                    \
3658         REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;                            \
3659         REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT;                           \
3660 } while(0)
3661 #define __ac97_set_xs_stereo()                                          \
3662 do {                                                                    \
3663         REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;                            \
3664         REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT;     \
3665 } while(0)
3666
3667 /* In fact, only stereo is support now. */
3668 #define __ac97_set_rs_none()    ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
3669 #define __ac97_set_rs_mono()                                            \
3670 do {                                                                    \
3671         REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;                            \
3672         REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT;                           \
3673 } while(0)
3674 #define __ac97_set_rs_stereo()                                          \
3675 do {                                                                    \
3676         REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;                            \
3677         REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT;     \
3678 } while(0)
3679
3680 #define __ac97_warm_reset_codec()               \
3681  do {                                           \
3682         REG_AIC_ACCR2 |= AIC_ACCR2_SA;          \
3683         REG_AIC_ACCR2 |= AIC_ACCR2_SS;          \
3684         udelay(2);                              \
3685         REG_AIC_ACCR2 &= ~AIC_ACCR2_SS;         \
3686         REG_AIC_ACCR2 &= ~AIC_ACCR2_SA;         \
3687  } while (0)
3688
3689 #define __ac97_cold_reset_codec()               \
3690  do {                                           \
3691         REG_AIC_ACCR2 |=  AIC_ACCR2_SR;         \
3692         udelay(2);                              \
3693         REG_AIC_ACCR2 &= ~AIC_ACCR2_SR;         \
3694  } while (0)
3695
3696 /* n=8,16,18,20 */
3697 #define __ac97_set_iass(n) \
3698  ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
3699 #define __ac97_set_oass(n) \
3700  ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
3701
3702 #define __i2s_select_i2s()            ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
3703 #define __i2s_select_msbjustified()   ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
3704
3705 /* n=8,16,18,20,24 */
3706 /*#define __i2s_set_sample_size(n) \
3707  ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
3708
3709 #define __i2s_set_oss_sample_size(n) \
3710  ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
3711 #define __i2s_set_iss_sample_size(n) \
3712  ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
3713
3714 #define __i2s_stop_bitclk()   ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
3715 #define __i2s_start_bitclk()  ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
3716
3717 #define __aic_transmit_request()  ( REG_AIC_SR & AIC_SR_TFS )
3718 #define __aic_receive_request()   ( REG_AIC_SR & AIC_SR_RFS )
3719 #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
3720 #define __aic_receive_overrun()   ( REG_AIC_SR & AIC_SR_ROR )
3721
3722 #define __aic_clear_errors()      ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
3723
3724 #define __aic_get_transmit_resident() \
3725   ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
3726 #define __aic_get_receive_count() \
3727   ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
3728
3729 #define __ac97_command_transmitted()     ( REG_AIC_ACSR & AIC_ACSR_CADT )
3730 #define __ac97_status_received()         ( REG_AIC_ACSR & AIC_ACSR_SADR )
3731 #define __ac97_status_receive_timeout()  ( REG_AIC_ACSR & AIC_ACSR_RSTO )
3732 #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
3733 #define __ac97_codec_is_ready()          ( REG_AIC_ACSR & AIC_ACSR_CRDY )
3734 #define __ac97_slot_error_detected()     ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
3735 #define __ac97_clear_slot_error()        ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
3736
3737 #define __i2s_is_busy()         ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
3738
3739 #define CODEC_READ_CMD          (1 << 19)
3740 #define CODEC_WRITE_CMD         (0 << 19)
3741 #define CODEC_REG_INDEX_BIT     12
3742 #define CODEC_REG_INDEX_MASK    (0x7f << CODEC_REG_INDEX_BIT)   /* 18:12 */
3743 #define CODEC_REG_DATA_BIT      4
3744 #define CODEC_REG_DATA_MASK     (0x0ffff << 4)  /* 19:4 */
3745
3746 #define __ac97_out_rcmd_addr(reg)                                       \
3747 do {                                                                    \
3748     REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT);    \
3749 } while (0)
3750
3751 #define __ac97_out_wcmd_addr(reg)                                       \
3752 do {                                                                    \
3753     REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT);   \
3754 } while (0)
3755
3756 #define __ac97_out_data(value)                                          \
3757 do {                                                                    \
3758     REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT);                    \
3759 } while (0)
3760
3761 #define __ac97_in_data() \
3762  ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
3763
3764 #define __ac97_in_status_addr() \
3765  ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
3766
3767 #define __i2s_set_sample_rate(i2sclk, sync) \
3768   ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
3769
3770 #define __aic_write_tfifo(v)  ( REG_AIC_DR = (v) )
3771 #define __aic_read_rfifo()    ( REG_AIC_DR )
3772
3773 #define __aic_internal_codec()  ( REG_AIC_FR |= AIC_FR_ICDC )
3774 #define __aic_external_codec()  ( REG_AIC_FR &= ~AIC_FR_ICDC )
3775
3776 //
3777 // Define next ops for AC97 compatible
3778 //
3779
3780 #define AC97_ACSR       AIC_ACSR
3781
3782 #define __ac97_enable()         __aic_enable(); __aic_select_ac97()
3783 #define __ac97_disable()        __aic_disable()
3784 #define __ac97_reset()          __aic_reset()
3785
3786 #define __ac97_set_transmit_trigger(n)  __aic_set_transmit_trigger(n)
3787 #define __ac97_set_receive_trigger(n)   __aic_set_receive_trigger(n)
3788
3789 #define __ac97_enable_record()          __aic_enable_record()
3790 #define __ac97_disable_record()         __aic_disable_record()
3791 #define __ac97_enable_replay()          __aic_enable_replay()
3792 #define __ac97_disable_replay()         __aic_disable_replay()
3793 #define __ac97_enable_loopback()        __aic_enable_loopback()
3794 #define __ac97_disable_loopback()       __aic_disable_loopback()
3795
3796 #define __ac97_enable_transmit_dma()    __aic_enable_transmit_dma()
3797 #define __ac97_disable_transmit_dma()   __aic_disable_transmit_dma()
3798 #define __ac97_enable_receive_dma()     __aic_enable_receive_dma()
3799 #define __ac97_disable_receive_dma()    __aic_disable_receive_dma()
3800
3801 #define __ac97_transmit_request()       __aic_transmit_request()
3802 #define __ac97_receive_request()        __aic_receive_request()
3803 #define __ac97_transmit_underrun()      __aic_transmit_underrun()
3804 #define __ac97_receive_overrun()        __aic_receive_overrun()
3805
3806 #define __ac97_clear_errors()           __aic_clear_errors()
3807
3808 #define __ac97_get_transmit_resident()  __aic_get_transmit_resident()
3809 #define __ac97_get_receive_count()      __aic_get_receive_count()
3810
3811 #define __ac97_enable_transmit_intr()   __aic_enable_transmit_intr()
3812 #define __ac97_disable_transmit_intr()  __aic_disable_transmit_intr()
3813 #define __ac97_enable_receive_intr()    __aic_enable_receive_intr()
3814 #define __ac97_disable_receive_intr()   __aic_disable_receive_intr()
3815
3816 #define __ac97_write_tfifo(v)           __aic_write_tfifo(v)
3817 #define __ac97_read_rfifo()             __aic_read_rfifo()
3818
3819 //
3820 // Define next ops for I2S compatible
3821 //
3822
3823 #define I2S_ACSR        AIC_I2SSR
3824
3825 #define __i2s_enable()           __aic_enable(); __aic_select_i2s()
3826 #define __i2s_disable()         __aic_disable()
3827 #define __i2s_reset()           __aic_reset()
3828
3829 #define __i2s_set_transmit_trigger(n)   __aic_set_transmit_trigger(n)
3830 #define __i2s_set_receive_trigger(n)    __aic_set_receive_trigger(n)
3831
3832 #define __i2s_enable_record()           __aic_enable_record()
3833 #define __i2s_disable_record()          __aic_disable_record()
3834 #define __i2s_enable_replay()           __aic_enable_replay()
3835 #define __i2s_disable_replay()          __aic_disable_replay()
3836 #define __i2s_enable_loopback()         __aic_enable_loopback()
3837 #define __i2s_disable_loopback()        __aic_disable_loopback()
3838
3839 #define __i2s_enable_transmit_dma()     __aic_enable_transmit_dma()
3840 #define __i2s_disable_transmit_dma()    __aic_disable_transmit_dma()
3841 #define __i2s_enable_receive_dma()      __aic_enable_receive_dma()
3842 #define __i2s_disable_receive_dma()     __aic_disable_receive_dma()
3843
3844 #define __i2s_transmit_request()        __aic_transmit_request()
3845 #define __i2s_receive_request()         __aic_receive_request()
3846 #define __i2s_transmit_underrun()       __aic_transmit_underrun()
3847 #define __i2s_receive_overrun()         __aic_receive_overrun()
3848
3849 #define __i2s_clear_errors()            __aic_clear_errors()
3850
3851 #define __i2s_get_transmit_resident()   __aic_get_transmit_resident()
3852 #define __i2s_get_receive_count()       __aic_get_receive_count()
3853
3854 #define __i2s_enable_transmit_intr()    __aic_enable_transmit_intr()
3855 #define __i2s_disable_transmit_intr()   __aic_disable_transmit_intr()
3856 #define __i2s_enable_receive_intr()     __aic_enable_receive_intr()
3857 #define __i2s_disable_receive_intr()    __aic_disable_receive_intr()
3858
3859 #define __i2s_write_tfifo(v)            __aic_write_tfifo(v)
3860 #define __i2s_read_rfifo()              __aic_read_rfifo()
3861
3862 #define __i2s_reset_codec()                     \
3863  do {                                           \
3864  } while (0)
3865
3866
3867 /***************************************************************************
3868  * ICDC
3869  ***************************************************************************/
3870 #define __i2s_internal_codec()         __aic_internal_codec()
3871 #define __i2s_external_codec()         __aic_external_codec()
3872
3873 /***************************************************************************
3874  * INTC
3875  ***************************************************************************/
3876 #define __intc_unmask_irq(n)    ( REG_INTC_IMCR = (1 << (n)) )
3877 #define __intc_mask_irq(n)      ( REG_INTC_IMSR = (1 << (n)) )
3878 #define __intc_ack_irq(n)       ( REG_INTC_IPR = (1 << (n)) )
3879
3880
3881 /***************************************************************************
3882  * I2C
3883  ***************************************************************************/
3884
3885 #define __i2c_enable()          ( REG_I2C_CR |= I2C_CR_I2CE )
3886 #define __i2c_disable()         ( REG_I2C_CR &= ~I2C_CR_I2CE )
3887
3888 #define __i2c_send_start()      ( REG_I2C_CR |= I2C_CR_STA )
3889 #define __i2c_send_stop()       ( REG_I2C_CR |= I2C_CR_STO )
3890 #define __i2c_send_ack()        ( REG_I2C_CR &= ~I2C_CR_AC )
3891 #define __i2c_send_nack()       ( REG_I2C_CR |= I2C_CR_AC )
3892
3893 #define __i2c_set_drf()         ( REG_I2C_SR |= I2C_SR_DRF )
3894 #define __i2c_clear_drf()       ( REG_I2C_SR &= ~I2C_SR_DRF )
3895 #define __i2c_check_drf()       ( REG_I2C_SR & I2C_SR_DRF )
3896
3897 #define __i2c_received_ack()    ( !(REG_I2C_SR & I2C_SR_ACKF) )
3898 #define __i2c_is_busy()         ( REG_I2C_SR & I2C_SR_BUSY )
3899 #define __i2c_transmit_ended()  ( REG_I2C_SR & I2C_SR_TEND )
3900
3901 #define __i2c_set_clk(dev_clk, i2c_clk) \
3902   ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
3903
3904 #define __i2c_read()            ( REG_I2C_DR )
3905 #define __i2c_write(val)        ( REG_I2C_DR = (val) )
3906
3907
3908 /***************************************************************************
3909  * MSC
3910  ***************************************************************************/
3911
3912 #define __msc_start_op() \
3913   ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
3914
3915 #define __msc_set_resto(to)     ( REG_MSC_RESTO = to )
3916 #define __msc_set_rdto(to)      ( REG_MSC_RDTO = to )
3917 #define __msc_set_cmd(cmd)      ( REG_MSC_CMD = cmd )
3918 #define __msc_set_arg(arg)      ( REG_MSC_ARG = arg )
3919 #define __msc_set_nob(nob)      ( REG_MSC_NOB = nob )
3920 #define __msc_get_nob()         ( REG_MSC_NOB )
3921 #define __msc_set_blklen(len)   ( REG_MSC_BLKLEN = len )
3922 #define __msc_set_cmdat(cmdat)  ( REG_MSC_CMDAT = cmdat )
3923 #define __msc_set_cmdat_ioabort()       ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
3924 #define __msc_clear_cmdat_ioabort()     ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
3925
3926 #define __msc_set_cmdat_bus_width1()                    \
3927 do {                                                    \
3928         REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK;     \
3929         REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT;      \
3930 } while(0)
3931
3932 #define __msc_set_cmdat_bus_width4()                    \
3933 do {                                                    \
3934         REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK;     \
3935         REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT;      \
3936 } while(0)
3937
3938 #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
3939 #define __msc_set_cmdat_init()  ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
3940 #define __msc_set_cmdat_busy()  ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
3941 #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
3942 #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
3943 #define __msc_set_cmdat_read()  ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
3944 #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
3945 #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
3946
3947 /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
3948 #define __msc_set_cmdat_res_format(r)                           \
3949 do {                                                            \
3950         REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK;       \
3951         REG_MSC_CMDAT |= (r);                                   \
3952 } while(0)
3953
3954 #define __msc_clear_cmdat() \
3955   REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
3956   MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
3957   MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
3958
3959 #define __msc_get_imask()               ( REG_MSC_IMASK )
3960 #define __msc_mask_all_intrs()          ( REG_MSC_IMASK = 0xff )
3961 #define __msc_unmask_all_intrs()        ( REG_MSC_IMASK = 0x00 )
3962 #define __msc_mask_rd()                 ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
3963 #define __msc_unmask_rd()               ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
3964 #define __msc_mask_wr()                 ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
3965 #define __msc_unmask_wr()               ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
3966 #define __msc_mask_endcmdres()          ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
3967 #define __msc_unmask_endcmdres()        ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
3968 #define __msc_mask_datatrandone()       ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
3969 #define __msc_unmask_datatrandone()     ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
3970 #define __msc_mask_prgdone()            ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
3971 #define __msc_unmask_prgdone()          ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
3972
3973 /* n=0,1,2,3,4,5,6,7 */
3974 #define __msc_set_clkrt(n)      \
3975 do {                            \
3976         REG_MSC_CLKRT = n;      \
3977 } while(0)
3978
3979 #define __msc_get_ireg()                ( REG_MSC_IREG )
3980 #define __msc_ireg_rd()                 ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
3981 #define __msc_ireg_wr()                 ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
3982 #define __msc_ireg_end_cmd_res()        ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
3983 #define __msc_ireg_data_tran_done()     ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
3984 #define __msc_ireg_prg_done()           ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
3985 #define __msc_ireg_clear_end_cmd_res()  ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
3986 #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
3987 #define __msc_ireg_clear_prg_done()     ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
3988
3989 #define __msc_get_stat()                ( REG_MSC_STAT )
3990 #define __msc_stat_not_end_cmd_res()    ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
3991 #define __msc_stat_crc_err() \
3992   ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
3993 #define __msc_stat_res_crc_err()        ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
3994 #define __msc_stat_rd_crc_err()         ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
3995 #define __msc_stat_wr_crc_err()         ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
3996 #define __msc_stat_resto_err()          ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
3997 #define __msc_stat_rdto_err()           ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
3998
3999 #define __msc_rd_resfifo()              ( REG_MSC_RES )
4000 #define __msc_rd_rxfifo()               ( REG_MSC_RXFIFO )
4001 #define __msc_wr_txfifo(v)              ( REG_MSC_TXFIFO = v )
4002
4003 #define __msc_reset()                                           \
4004 do {                                                            \
4005         REG_MSC_STRPCL = MSC_STRPCL_RESET;                      \
4006         while (REG_MSC_STAT & MSC_STAT_IS_RESETTING);           \
4007 } while (0)
4008
4009 #define __msc_start_clk()                                       \
4010 do {                                                            \
4011         REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START;        \
4012 } while (0)
4013
4014 #define __msc_stop_clk()                                        \
4015 do {                                                            \
4016         REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
4017 } while (0)
4018
4019 #define MMC_CLK 19169200
4020 #define SD_CLK  24576000
4021
4022 /* msc_clk should little than pclk and little than clk retrieve from card */
4023 #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv)         \
4024 do {                                                            \
4025         unsigned int rate, pclk, i;                             \
4026         pclk = dev_clk;                                         \
4027         rate = type?SD_CLK:MMC_CLK;                             \
4028         if (msc_clk && msc_clk < pclk)                          \
4029                 pclk = msc_clk;                                 \
4030         i = 0;                                                  \
4031         while (pclk < rate)                                     \
4032         {                                                       \
4033                 i ++;                                           \
4034                 rate >>= 1;                                     \
4035         }                                                       \
4036         lv = i;                                                 \
4037 } while(0)
4038
4039 /* divide rate to little than or equal to 400kHz */
4040 #define __msc_calc_slow_clk_divisor(type, lv)                   \
4041 do {                                                            \
4042         unsigned int rate, i;                                   \
4043         rate = (type?SD_CLK:MMC_CLK)/1000/400;                  \
4044         i = 0;                                                  \
4045         while (rate > 0)                                        \
4046         {                                                       \
4047                 rate >>= 1;                                     \
4048                 i ++;                                           \
4049         }                                                       \
4050         lv = i;                                                 \
4051 } while(0)
4052
4053
4054 /***************************************************************************
4055  * SSI
4056  ***************************************************************************/
4057
4058 #define __ssi_enable()    ( REG_SSI_CR0 |= SSI_CR0_SSIE )
4059 #define __ssi_disable()   ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
4060 #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
4061
4062 #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
4063
4064 #define __ssi_select_ce2()              \
4065 do {                                    \
4066         REG_SSI_CR0 |= SSI_CR0_FSEL;    \
4067         REG_SSI_CR1 &= ~SSI_CR1_MULTS;  \
4068 } while (0)
4069
4070 #define __ssi_select_gpc()              \
4071 do {                                    \
4072         REG_SSI_CR0 &= ~SSI_CR0_FSEL;   \
4073         REG_SSI_CR1 |= SSI_CR1_MULTS;   \
4074 } while (0)
4075
4076 #define __ssi_enable_tx_intr()  \
4077   ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
4078
4079 #define __ssi_disable_tx_intr() \
4080   ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
4081
4082 #define __ssi_enable_rx_intr()  \
4083   ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE )
4084
4085 #define __ssi_disable_rx_intr() \
4086   ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
4087
4088 #define __ssi_enable_loopback()  ( REG_SSI_CR0 |= SSI_CR0_LOOP )
4089 #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP )
4090
4091 #define __ssi_enable_receive()   ( REG_SSI_CR0 &= ~SSI_CR0_DISREV )
4092 #define __ssi_disable_receive()  ( REG_SSI_CR0 |= SSI_CR0_DISREV )
4093
4094 #define __ssi_finish_receive()  \
4095   ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
4096
4097 #define __ssi_disable_recvfinish() \
4098   ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
4099
4100 #define __ssi_flush_txfifo()   ( REG_SSI_CR0 |= SSI_CR0_TFLUSH )
4101 #define __ssi_flush_rxfifo()   ( REG_SSI_CR0 |= SSI_CR0_RFLUSH )
4102
4103 #define __ssi_flush_fifo() \
4104   ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
4105
4106 #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN )
4107
4108 #define __ssi_spi_format()                                      \
4109 do {                                                            \
4110         REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK;                      \
4111         REG_SSI_CR1 |= SSI_CR1_FMAT_SPI;                        \
4112         REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
4113         REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1);     \
4114 } while (0)
4115
4116 /* TI's SSP format, must clear SSI_CR1.UNFIN */
4117 #define __ssi_ssp_format()                                      \
4118 do {                                                            \
4119         REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN);    \
4120         REG_SSI_CR1 |= SSI_CR1_FMAT_SSP;                        \
4121 } while (0)
4122
4123 /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
4124 #define __ssi_microwire_format()                                \
4125 do {                                                            \
4126         REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK;                      \
4127         REG_SSI_CR1 |= SSI_CR1_FMAT_MW1;                        \
4128         REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
4129         REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3);     \
4130         REG_SSI_CR0 &= ~SSI_CR0_RFINE;                          \
4131 } while (0)
4132
4133 /* CE# level (FRMHL), CE# in interval time (ITFRM),
4134    clock phase and polarity (PHA POL),
4135    interval time (SSIITR), interval characters/frame (SSIICR) */
4136
4137  /* frmhl,endian,mcom,flen,pha,pol MASK */
4138 #define SSICR1_MISC_MASK                                        \
4139         ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
4140         | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL )       \
4141
4142 #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol)      \
4143 do {                                                            \
4144         REG_SSI_CR1 &= ~SSICR1_MISC_MASK;                       \
4145         REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) |     \
4146                  (((mcom) - 1) << 12) | (((flen) - 2) << 4) |   \
4147                  ((pha) << 1) | (pol);                          \
4148 } while(0)
4149
4150 /* Transfer with MSB or LSB first */
4151 #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST )
4152 #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST )
4153
4154 #define __ssi_set_frame_length(n) \
4155     REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4)
4156
4157 /* n = 1 - 16 */
4158 #define __ssi_set_microwire_command_length(n) \
4159     ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) )
4160
4161 /* Set the clock phase for SPI */
4162 #define __ssi_set_spi_clock_phase(n) \
4163     ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) )
4164
4165 /* Set the clock polarity for SPI */
4166 #define __ssi_set_spi_clock_polarity(n) \
4167     ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) )
4168
4169 /* n = ix8 */
4170 #define __ssi_set_tx_trigger(n)                 \
4171 do {                                            \
4172         REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK;      \
4173         REG_SSI_CR1 |= SSI_CR1_TTRG_##n;        \
4174 } while (0)
4175
4176 /* n = ix8 */
4177 #define __ssi_set_rx_trigger(n)                 \
4178 do {                                            \
4179         REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK;      \
4180         REG_SSI_CR1 |= SSI_CR1_RTRG_##n;        \
4181 } while (0)
4182
4183 #define __ssi_get_txfifo_count() \
4184     ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
4185
4186 #define __ssi_get_rxfifo_count() \
4187     ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
4188
4189 #define __ssi_clear_errors() \
4190     ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
4191
4192 #define __ssi_transfer_end()    ( REG_SSI_SR & SSI_SR_END )
4193 #define __ssi_is_busy()         ( REG_SSI_SR & SSI_SR_BUSY )
4194
4195 #define __ssi_txfifo_full()     ( REG_SSI_SR & SSI_SR_TFF )
4196 #define __ssi_rxfifo_empty()    ( REG_SSI_SR & SSI_SR_RFE )
4197 #define __ssi_rxfifo_noempty()  ( REG_SSI_SR & SSI_SR_RFHF )
4198
4199 #define __ssi_set_clk(dev_clk, ssi_clk) \
4200   ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 )
4201
4202 #define __ssi_receive_data()    REG_SSI_DR
4203 #define __ssi_transmit_data(v)  ( REG_SSI_DR = (v) )
4204
4205
4206 /***************************************************************************
4207  * CIM
4208  ***************************************************************************/
4209
4210 #define __cim_enable()  ( REG_CIM_CTRL |= CIM_CTRL_ENA )
4211 #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
4212
4213 #define __cim_input_data_inverse()      ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
4214 #define __cim_input_data_normal()       ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
4215
4216 #define __cim_vsync_active_low()        ( REG_CIM_CFG |= CIM_CFG_VSP )
4217 #define __cim_vsync_active_high()       ( REG_CIM_CFG &= ~CIM_CFG_VSP )
4218
4219 #define __cim_hsync_active_low()        ( REG_CIM_CFG |= CIM_CFG_HSP )
4220 #define __cim_hsync_active_high()       ( REG_CIM_CFG &= ~CIM_CFG_HSP )
4221
4222 #define __cim_sample_data_at_pclk_falling_edge() \
4223   ( REG_CIM_CFG |= CIM_CFG_PCP )
4224 #define __cim_sample_data_at_pclk_rising_edge() \
4225   ( REG_CIM_CFG &= ~CIM_CFG_PCP )
4226
4227 #define __cim_enable_dummy_zero()       ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
4228 #define __cim_disable_dummy_zero()      ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
4229
4230 #define __cim_select_external_vsync()   ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
4231 #define __cim_select_internal_vsync()   ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
4232
4233 /* n=0-7 */
4234 #define __cim_set_data_packing_mode(n)          \
4235 do {                                            \
4236     REG_CIM_CFG &= ~CIM_CFG_PACK_MASK;          \
4237     REG_CIM_CFG |= (CIM_CFG_PACK_##n);          \
4238 } while (0)
4239
4240 #define __cim_enable_ccir656_progressive_mode() \
4241 do {                                            \
4242     REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;           \
4243     REG_CIM_CFG |= CIM_CFG_DSM_CPM;             \
4244 } while (0)
4245
4246 #define __cim_enable_ccir656_interlace_mode()   \
4247 do {                                            \
4248     REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;           \
4249     REG_CIM_CFG |= CIM_CFG_DSM_CIM;             \
4250 } while (0)
4251
4252 #define __cim_enable_gated_clock_mode()         \
4253 do {                                            \
4254     REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;           \
4255     REG_CIM_CFG |= CIM_CFG_DSM_GCM;             \
4256 } while (0)
4257
4258 #define __cim_enable_nongated_clock_mode()      \
4259 do {                                            \
4260     REG_CIM_CFG &= ~CIM_CFG_DSM_MASK;           \
4261     REG_CIM_CFG |= CIM_CFG_DSM_NGCM;            \
4262 } while (0)
4263
4264 /* sclk:system bus clock
4265  * mclk: CIM master clock
4266  */
4267 #define __cim_set_master_clk(sclk, mclk)                        \
4268 do {                                                            \
4269     REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK;                     \
4270     REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT);      \
4271 } while (0)
4272
4273 #define __cim_enable_sof_intr() \
4274   ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
4275 #define __cim_disable_sof_intr() \
4276   ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
4277
4278 #define __cim_enable_eof_intr() \
4279   ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
4280 #define __cim_disable_eof_intr() \
4281   ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
4282
4283 #define __cim_enable_stop_intr() \
4284   ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
4285 #define __cim_disable_stop_intr() \
4286   ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
4287
4288 #define __cim_enable_trig_intr() \
4289   ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
4290 #define __cim_disable_trig_intr() \
4291   ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
4292
4293 #define __cim_enable_rxfifo_overflow_intr() \
4294   ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
4295 #define __cim_disable_rxfifo_overflow_intr() \
4296   ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
4297
4298 /* n=1-16 */
4299 #define __cim_set_frame_rate(n)                 \
4300 do {                                            \
4301     REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK;         \
4302     REG_CIM_CTRL |= CIM_CTRL_FRC_##n;           \
4303 } while (0)
4304
4305 #define __cim_enable_dma()   ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
4306 #define __cim_disable_dma()  ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
4307
4308 #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
4309 #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
4310
4311 /* n=4,8,12,16,20,24,28,32 */
4312 #define __cim_set_rxfifo_trigger(n)             \
4313 do {                                            \
4314     REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK;    \
4315     REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n;      \
4316 } while (0)
4317
4318 #define __cim_clear_state()          ( REG_CIM_STATE = 0 )
4319
4320 #define __cim_disable_done()         ( REG_CIM_STATE & CIM_STATE_VDD )
4321 #define __cim_rxfifo_empty()         ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
4322 #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
4323 #define __cim_rxfifo_overflow()      ( REG_CIM_STATE & CIM_STATE_RXF_OF )
4324 #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
4325 #define __cim_dma_stop()             ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
4326 #define __cim_dma_eof()              ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
4327 #define __cim_dma_sof()              ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
4328
4329 #define __cim_get_iid()              ( REG_CIM_IID )
4330 #define __cim_get_image_data()       ( REG_CIM_RXFIFO )
4331 #define __cim_get_dam_cmd()          ( REG_CIM_CMD )
4332
4333 #define __cim_set_da(a)              ( REG_CIM_DA = (a) )
4334
4335 /***************************************************************************
4336  * LCD
4337  ***************************************************************************/
4338 #define __lcd_as_smart_lcd()            ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
4339 #define __lcd_as_general_lcd()          ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
4340
4341 #define __lcd_set_dis()                 ( REG_LCD_CTRL |= LCD_CTRL_DIS )
4342 #define __lcd_clr_dis()                 ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
4343
4344 #define __lcd_set_ena()                 ( REG_LCD_CTRL |= LCD_CTRL_ENA )
4345 #define __lcd_clr_ena()                 ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
4346
4347 /* n=1,2,4,8,16 */
4348 #define __lcd_set_bpp(n) \
4349   ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
4350
4351 /* n=4,8,16 */
4352 #define __lcd_set_burst_length(n)               \
4353 do {                                            \
4354         REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK;     \
4355         REG_LCD_CTRL |= LCD_CTRL_BST_n##;       \
4356 } while (0)
4357
4358 #define __lcd_select_rgb565()           ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
4359 #define __lcd_select_rgb555()           ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
4360
4361 #define __lcd_set_ofup()                ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
4362 #define __lcd_clr_ofup()                ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
4363
4364 /* n=2,4,16 */
4365 #define __lcd_set_stn_frc(n)                    \
4366 do {                                            \
4367         REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK;     \
4368         REG_LCD_CTRL |= LCD_CTRL_FRC_n##;       \
4369 } while (0)
4370
4371
4372 #define __lcd_pixel_endian_little()     ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
4373 #define __lcd_pixel_endian_big()        ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
4374
4375 #define __lcd_reverse_byte_endian()     ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
4376 #define __lcd_normal_byte_endian()      ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
4377
4378 #define __lcd_enable_eof_intr()         ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
4379 #define __lcd_disable_eof_intr()        ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
4380
4381 #define __lcd_enable_sof_intr()         ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
4382 #define __lcd_disable_sof_intr()        ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
4383
4384 #define __lcd_enable_ofu_intr()         ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
4385 #define __lcd_disable_ofu_intr()        ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
4386
4387 #define __lcd_enable_ifu0_intr()        ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
4388 #define __lcd_disable_ifu0_intr()       ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
4389
4390 #define __lcd_enable_ifu1_intr()        ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
4391 #define __lcd_disable_ifu1_intr()       ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
4392
4393 #define __lcd_enable_ldd_intr()         ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
4394 #define __lcd_disable_ldd_intr()        ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
4395
4396 #define __lcd_enable_qd_intr()          ( REG_LCD_CTRL |= LCD_CTRL_QDM )
4397 #define __lcd_disable_qd_intr()         ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
4398
4399
4400 /* LCD status register indication */
4401
4402 #define __lcd_quick_disable_done()      ( REG_LCD_STATE & LCD_STATE_QD )
4403 #define __lcd_disable_done()            ( REG_LCD_STATE & LCD_STATE_LDD )
4404 #define __lcd_infifo0_underrun()        ( REG_LCD_STATE & LCD_STATE_IFU0 )
4405 #define __lcd_infifo1_underrun()        ( REG_LCD_STATE & LCD_STATE_IFU1 )
4406 #define __lcd_outfifo_underrun()        ( REG_LCD_STATE & LCD_STATE_OFU )
4407 #define __lcd_start_of_frame()          ( REG_LCD_STATE & LCD_STATE_SOF )
4408 #define __lcd_end_of_frame()            ( REG_LCD_STATE & LCD_STATE_EOF )
4409
4410 #define __lcd_clr_outfifounderrun()     ( REG_LCD_STATE &= ~LCD_STATE_OFU )
4411 #define __lcd_clr_sof()                 ( REG_LCD_STATE &= ~LCD_STATE_SOF )
4412 #define __lcd_clr_eof()                 ( REG_LCD_STATE &= ~LCD_STATE_EOF )
4413
4414 #define __lcd_panel_white()             ( REG_LCD_CFG |= LCD_CFG_WHITE )
4415 #define __lcd_panel_black()             ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
4416
4417 /* n=1,2,4,8 for single mono-STN
4418  * n=4,8 for dual mono-STN
4419  */
4420 #define __lcd_set_panel_datawidth(n)            \
4421 do {                                            \
4422         REG_LCD_CFG &= ~LCD_CFG_PDW_MASK;       \
4423         REG_LCD_CFG |= LCD_CFG_PDW_n##;         \
4424 } while (0)
4425
4426 /* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
4427 #define __lcd_set_panel_mode(m)                 \
4428 do {                                            \
4429         REG_LCD_CFG &= ~LCD_CFG_MODE_MASK;      \
4430         REG_LCD_CFG |= (m);                     \
4431 } while(0)
4432
4433 /* n = 0-255 */
4434 #define __lcd_disable_ac_bias()         ( REG_LCD_IO = 0xff )
4435 #define __lcd_set_ac_bias(n)                    \
4436 do {                                            \
4437         REG_LCD_IO &= ~LCD_IO_ACB_MASK;         \
4438         REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT);  \
4439 } while(0)
4440
4441 #define __lcd_io_set_dir()              ( REG_LCD_IO |= LCD_IO_DIR )
4442 #define __lcd_io_clr_dir()              ( REG_LCD_IO &= ~LCD_IO_DIR )
4443
4444 #define __lcd_io_set_dep()              ( REG_LCD_IO |= LCD_IO_DEP )
4445 #define __lcd_io_clr_dep()              ( REG_LCD_IO &= ~LCD_IO_DEP )
4446
4447 #define __lcd_io_set_vsp()              ( REG_LCD_IO |= LCD_IO_VSP )
4448 #define __lcd_io_clr_vsp()              ( REG_LCD_IO &= ~LCD_IO_VSP )
4449
4450 #define __lcd_io_set_hsp()              ( REG_LCD_IO |= LCD_IO_HSP )
4451 #define __lcd_io_clr_hsp()              ( REG_LCD_IO &= ~LCD_IO_HSP )
4452
4453 #define __lcd_io_set_pcp()              ( REG_LCD_IO |= LCD_IO_PCP )
4454 #define __lcd_io_clr_pcp()              ( REG_LCD_IO &= ~LCD_IO_PCP )
4455
4456 #define __lcd_vsync_get_vps() \
4457   ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
4458
4459 #define __lcd_vsync_get_vpe() \
4460   ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
4461 #define __lcd_vsync_set_vpe(n)                          \
4462 do {                                                    \
4463         REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK;           \
4464         REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT;      \
4465 } while (0)
4466
4467 #define __lcd_hsync_get_hps() \
4468   ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
4469 #define __lcd_hsync_set_hps(n)                          \
4470 do {                                                    \
4471         REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK;           \
4472         REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT;      \
4473 } while (0)
4474
4475 #define __lcd_hsync_get_hpe() \
4476   ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
4477 #define __lcd_hsync_set_hpe(n)                          \
4478 do {                                                    \
4479         REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK;           \
4480         REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT;      \
4481 } while (0)
4482
4483 #define __lcd_vat_get_ht() \
4484   ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
4485 #define __lcd_vat_set_ht(n)                             \
4486 do {                                                    \
4487         REG_LCD_VAT &= ~LCD_VAT_HT_MASK;                \
4488         REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT;           \
4489 } while (0)
4490
4491 #define __lcd_vat_get_vt() \
4492   ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
4493 #define __lcd_vat_set_vt(n)                             \
4494 do {                                                    \
4495         REG_LCD_VAT &= ~LCD_VAT_VT_MASK;                \
4496         REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT;           \
4497 } while (0)
4498
4499 #define __lcd_dah_get_hds() \
4500   ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
4501 #define __lcd_dah_set_hds(n)                            \
4502 do {                                                    \
4503         REG_LCD_DAH &= ~LCD_DAH_HDS_MASK;               \
4504         REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT;          \
4505 } while (0)
4506
4507 #define __lcd_dah_get_hde() \
4508   ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
4509 #define __lcd_dah_set_hde(n)                            \
4510 do {                                                    \
4511         REG_LCD_DAH &= ~LCD_DAH_HDE_MASK;               \
4512         REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT;          \
4513 } while (0)
4514
4515 #define __lcd_dav_get_vds() \
4516   ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
4517 #define __lcd_dav_set_vds(n)                            \
4518 do {                                                    \
4519         REG_LCD_DAV &= ~LCD_DAV_VDS_MASK;               \
4520         REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT;          \
4521 } while (0)
4522
4523 #define __lcd_dav_get_vde() \
4524   ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
4525 #define __lcd_dav_set_vde(n)                            \
4526 do {                                                    \
4527         REG_LCD_DAV &= ~LCD_DAV_VDE_MASK;               \
4528         REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT;          \
4529 } while (0)
4530
4531 #define __lcd_cmd0_set_sofint()         ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
4532 #define __lcd_cmd0_clr_sofint()         ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
4533 #define __lcd_cmd1_set_sofint()         ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
4534 #define __lcd_cmd1_clr_sofint()         ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
4535
4536 #define __lcd_cmd0_set_eofint()         ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
4537 #define __lcd_cmd0_clr_eofint()         ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
4538 #define __lcd_cmd1_set_eofint()         ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
4539 #define __lcd_cmd1_clr_eofint()         ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
4540
4541 #define __lcd_cmd0_set_pal()            ( REG_LCD_CMD0 |= LCD_CMD_PAL )
4542 #define __lcd_cmd0_clr_pal()            ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
4543
4544 #define __lcd_cmd0_get_len() \
4545   ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
4546 #define __lcd_cmd1_get_len() \
4547   ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
4548
4549 /***************************************************************************
4550  * RTC ops
4551  ***************************************************************************/
4552
4553 #define __rtc_write_ready()  ( REG_RTC_RCR & RTC_RCR_WRDY )
4554 #define __rtc_enabled()      \
4555 do{                          \
4556       while(!__rtc_write_ready());  \
4557       REG_RTC_RCR |= RTC_RCR_RTCE ; \
4558 }while(0)                           \
4559
4560 #define __rtc_disabled()         \
4561 do{                          \
4562       while(!__rtc_write_ready());  \
4563       REG_RTC_RCR &= ~RTC_RCR_RTCE; \
4564 }while(0)
4565 #define __rtc_enable_alarm()       \
4566 do{                          \
4567       while(!__rtc_write_ready());  \
4568       REG_RTC_RCR |= RTC_RCR_AE; \
4569 }while(0)
4570
4571 #define __rtc_disable_alarm()    \
4572 do{                          \
4573       while(!__rtc_write_ready());  \
4574       REG_RTC_RCR &= ~RTC_RCR_AE; \
4575 }while(0)
4576
4577 #define __rtc_enable_alarm_irq()  \
4578 do{                          \
4579       while(!__rtc_write_ready());  \
4580       REG_RTC_RCR |= RTC_RCR_AIE; \
4581 }while(0)
4582
4583 #define __rtc_disable_alarm_irq() \
4584 do{                          \
4585       while(!__rtc_write_ready());  \
4586       REG_RTC_RCR &= ~RTC_RCR_AIE; \
4587 }while(0)
4588 #define __rtc_enable_Hz_irq()      \
4589 do{                          \
4590       while(!__rtc_write_ready());  \
4591       REG_RTC_RCR |= RTC_RCR_HZIE;  \
4592 }while(0)
4593
4594 #define __rtc_disable_Hz_irq()     \
4595 do{                          \
4596       while(!__rtc_write_ready());  \
4597       REG_RTC_RCR &= ~RTC_RCR_HZIE; \
4598 }while(0)
4599 #define __rtc_get_1Hz_flag()     \
4600 do{                                 \
4601       while(!__rtc_write_ready());  \
4602       ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \
4603 }while(0)
4604 #define __rtc_clear_1Hz_flag()      \
4605 do{                                 \
4606       while(!__rtc_write_ready());  \
4607       REG_RTC_RCR &= ~RTC_RCR_HZ;   \
4608 }while(0)
4609 #define __rtc_get_alarm_flag()       \
4610 do{                                  \
4611        while(!__rtc_write_ready());  \
4612       ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \
4613 while(0)
4614 #define __rtc_clear_alarm_flag()    \
4615 do{                                 \
4616       while(!__rtc_write_ready());  \
4617       REG_RTC_RCR &= ~RTC_RCR_AF;   \
4618 }while(0)
4619 #define  __rtc_get_second()        \
4620 do{                                \
4621        while(!__rtc_write_ready());\
4622            REG_RTC_RSR;                \
4623 }while(0)
4624
4625 #define __rtc_set_second(v)         \
4626 do{                                 \
4627       while(!__rtc_write_ready());  \
4628       REG_RTC_RSR = v;              \
4629 }while(0)
4630
4631 #define  __rtc_get_alarm_second()  \
4632 do{                                \
4633       while(!__rtc_write_ready()); \
4634           REG_RTC_RSAR;                \
4635 }while(0)
4636
4637
4638 #define __rtc_set_alarm_second(v)   \
4639 do{                                 \
4640       while(!__rtc_write_ready());  \
4641       REG_RTC_RSAR = v;             \
4642 }while(0)
4643
4644 #define __rtc_RGR_is_locked()       \
4645 do{                                 \
4646       while(!__rtc_write_ready());  \
4647       REG_RTC_RGR >> RTC_RGR_LOCK;  \
4648 }while(0)
4649 #define __rtc_lock_RGR()            \
4650 do{                                 \
4651       while(!__rtc_write_ready());  \
4652       REG_RTC_RGR |= RTC_RGR_LOCK;  \
4653 }while(0)
4654
4655 #define __rtc_unlock_RGR()       \
4656 do{                                 \
4657       while(!__rtc_write_ready());  \
4658       REG_RTC_RGR &= ~RTC_RGR_LOCK; \
4659 }while(0)
4660
4661 #define __rtc_get_adjc_val()       \
4662 do{                                \
4663       while(!__rtc_write_ready());  \
4664       ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \
4665 }while(0)
4666 #define __rtc_set_adjc_val(v)      \
4667 do{                                 \
4668       while(!__rtc_write_ready());  \
4669       ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \
4670 }while(0)
4671
4672 #define __rtc_get_nc1Hz_val()       \
4673       while(!__rtc_write_ready());  \
4674       ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
4675
4676 #define __rtc_set_nc1Hz_val(v)      \
4677 do{                                 \
4678       while(!__rtc_write_ready());  \
4679       ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \
4680 }while(0)
4681 #define __rtc_power_down()          \
4682 do{                                 \
4683       while(!__rtc_write_ready());  \
4684       REG_RTC_HCR |= RTC_HCR_PD;    \
4685 }while(0)
4686
4687 #define __rtc_get_hwfcr_val()       \
4688 do{                                 \
4689       while(!__rtc_write_ready());  \
4690       REG_RTC_HWFCR & RTC_HWFCR_MASK;  \
4691 }while(0)
4692 #define __rtc_set_hwfcr_val(v)      \
4693 do{                                 \
4694       while(!__rtc_write_ready());  \
4695       REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK;  \
4696 }while(0)
4697
4698 #define __rtc_get_hrcr_val()      \
4699 do{                               \
4700       while(!__rtc_write_ready());  \
4701       ( REG_RTC_HRCR & RTC_HRCR_MASK ); \
4702 }while(0)
4703 #define __rtc_set_hrcr_val(v)        \
4704 do{                                 \
4705       while(!__rtc_write_ready());  \
4706       ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK );  \
4707 }while(0)
4708
4709 #define __rtc_enable_alarm_wakeup()      \
4710 do{                                 \
4711       while(!__rtc_write_ready());  \
4712       ( REG_RTC_HWCR |= RTC_HWCR_EALM );  \
4713 }while(0)
4714
4715 #define __rtc_disable_alarm_wakeup()     \
4716 do{                                 \
4717       while(!__rtc_write_ready());  \
4718       ( REG_RTC_HWCR &= ~RTC_HWCR_EALM );  \
4719 }while(0)
4720
4721 #define __rtc_status_hib_reset_occur()    \
4722 do{                                       \
4723       while(!__rtc_write_ready());        \
4724     ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \
4725 }while(0)
4726 #define __rtc_status_ppr_reset_occur()     \
4727 do{                                        \
4728       while(!__rtc_write_ready());        \
4729    ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \
4730 }while(0)
4731 #define __rtc_status_wakeup_pin_waken_up() \
4732 do{                                        \
4733       while(!__rtc_write_ready());        \
4734    ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \
4735 }while(0)
4736 #define __rtc_status_alarm_waken_up()      \
4737 do{                                       \
4738       while(!__rtc_write_ready());        \
4739   ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \
4740 }while(0)
4741 #define __rtc_clear_hib_stat_all()  \
4742 do{                                 \
4743       while(!__rtc_write_ready());  \
4744       ( REG_RTC_HWRSR = 0 );        \
4745 }while(0)
4746
4747 #define __rtc_get_scratch_pattern() \
4748       while(!__rtc_write_ready());  \
4749                   (REG_RTC_HSPR)
4750 #define __rtc_set_scratch_pattern(n)            \
4751 do{                                 \
4752       while(!__rtc_write_ready());  \
4753       (REG_RTC_HSPR = n );        \
4754 }while(0)
4755
4756
4757 #endif                          /* !__ASSEMBLY__ */
4758
4759 #endif                          /* __JZ4740_H__ */