| commit | d6af2388f7085b134d289b034a9cbe21a2d5f819 | |
| author | H.J. Lu <hjl.tools@gmail.com> | |
| Fri, 27 May 2016 22:16:22 +0000 (27 15:16 -0700) | ||
| committer | H.J. Lu <hjl.tools@gmail.com> | |
| Fri, 27 May 2016 22:16:51 +0000 (27 15:16 -0700) | ||
| tree | 247fee5893bf0ed398c80500d3fa919580cac5db | treesnapshot (tar.gz zip) |
| parent | f6ef0657e493e1f84dfb5b0b1966cf34e371ae27 | commitdiff |
Count number of logical processors sharing L2 cache
For Intel processors, when there are both L2 and L3 caches, SMT level
type should be ued to count number of available logical processors
sharing L2 cache. If there is only L2 cache, core level type should
be used to count number of available logical processors sharing L2
cache. Number of available logical processors sharing L2 cache should
be used for non-inclusive L2 and L3 caches.
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Count number of
available logical processors with SMT level type sharing L2
cache for Intel processors.
For Intel processors, when there are both L2 and L3 caches, SMT level
type should be ued to count number of available logical processors
sharing L2 cache. If there is only L2 cache, core level type should
be used to count number of available logical processors sharing L2
cache. Number of available logical processors sharing L2 cache should
be used for non-inclusive L2 and L3 caches.
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Count number of
available logical processors with SMT level type sharing L2
cache for Intel processors.
| ChangeLog | diffblobblamehistory | |
| sysdeps/x86/cacheinfo.c | diffblobblamehistory |