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commit	487972aea52004f604c2878c8c9d3e77670f2c32
author	Adhemerval Zanella <azanella@linux.vnet.ibm.com>
	Thu, 27 Feb 2014 15:43:51 +0000 (27 09:43 -0600)
committer	Adhemerval Zanella <azanella@linux.vnet.ibm.com>
	Thu, 27 Feb 2014 18:58:32 +0000 (27 12:58 -0600)
tree	1f8a570e52975d04c513523e7d7b454a29015993	tree \| snapshot (tar.gz zip)
parent	7d92b78723848ae616709eb8f0191ea067025b18	commit \| diff

PowerPC: Optimized isnan/isnanf for POWER8

This patch add a optimized isnan/isnanf implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.

ChangeLog		diff \| blob \| blame \| history
sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h		diff \| blob \| blame \| history
sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile		diff \| blob \| blame \| history
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isnan-power8.S	[new file with mode: 0644]	blob
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isnan.c		diff \| blob \| blame \| history
sysdeps/powerpc/powerpc64/fpu/multiarch/s_isnanf.c		diff \| blob \| blame \| history
sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S	[copied from sysdeps/powerpc/powerpc64/fpu/multiarch/s_isnan.c with 57% similarity]	diff \| blob \| blame \| history
sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S	[new file with mode: 0644]	blob

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