| commit | 38caf7a1cc92e6a546ea655701c8237ee727d0d3 | |
| author | Zong Li <zong.li@sifive.com> | |
| Wed, 9 Nov 2022 14:40:59 +0000 (9 11:40 -0300) | ||
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | |
| Wed, 9 Nov 2022 14:40:59 +0000 (9 11:40 -0300) | ||
| tree | 0119619baed0e9e26e682effadca7a553116c7ef | treesnapshot (tar.gz zip) |
| parent | 1a8335a408430517001a0660f5c7787223ce85e4 | commitdiff |
riscv: Get level 3 cache's information
RISC-V architecture extends the cache information for level 3 cache
in AUX vector in Linux v.6.1-rc1. This patch supports sysconf to get
the level 3 cache information.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
RISC-V architecture extends the cache information for level 3 cache
in AUX vector in Linux v.6.1-rc1. This patch supports sysconf to get
the level 3 cache information.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
| sysdeps/unix/sysv/linux/riscv/sysconf.c | diffblobblamehistory |