PowerPC: llrint/llrintf POWER8 optimization
commit1ad8950a3ea4056ed343d681b5146f4b4aa27e10
authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Tue, 18 Feb 2014 14:29:29 +0000 (18 09:29 -0500)
committerAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Thu, 27 Feb 2014 18:58:33 +0000 (27 12:58 -0600)
tree4dff22d7793de4244498f8c384dea196eb47a5a1
parentcac626d60a863e48ab75417064984769e58c5719
PowerPC: llrint/llrintf POWER8 optimization

This patch add a optimized llrint/llrintf implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.
ChangeLog
sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile
sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint-power8.S [new file with mode: 0644]
sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c
sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S [copied from sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c with 55% similarity]