sys/powerpc/ps3/ps3-hvcall.h

   1 /*
   2  * Playstation 3 LV1 hypercall interface
   3  *
   4  * $FreeBSD$
   5  */
   6
   7 #include <sys/types.h>
   8
   9 enum lpar_id {
  10         PS3_LPAR_ID_CURRENT     = 0x00,
  11         PS3_LPAR_ID_PME         = 0x01,
  12 };
  13
  14 /* Return codes from hypercalls */
  15 #define LV1_SUCCESS                     0
  16 #define LV1_RESOURCE_SHORTAGE           -2
  17 #define LV1_NO_PRIVILEGE                -3
  18 #define LV1_DENIED_BY_POLICY            -4
  19 #define LV1_ACCESS_VIOLATION            -5
  20 #define LV1_NO_ENTRY                    -6
  21 #define LV1_DUPLICATE_ENTRY             -7
  22 #define LV1_TYPE_MISMATCH               -8
  23 #define LV1_BUSY                        -9
  24 #define LV1_EMPTY                       -10
  25 #define LV1_WRONG_STATE                 -11
  26 #define LV1_NO_MATCH                    -13
  27 #define LV1_ALREADY_CONNECTED           -14
  28 #define LV1_UNSUPPORTED_PARAMETER_VALUE -15
  29 #define LV1_CONDITION_NOT_SATISFIED     -16
  30 #define LV1_ILLEGAL_PARAMETER_VALUE     -17
  31 #define LV1_BAD_OPTION                  -18
  32 #define LV1_IMPLEMENTATION_LIMITATION   -19
  33 #define LV1_NOT_IMPLEMENTED             -20
  34 #define LV1_INVALID_CLASS_ID            -21
  35 #define LV1_CONSTRAINT_NOT_SATISFIED    -22
  36 #define LV1_ALIGNMENT_ERROR             -23
  37 #define LV1_HARDWARE_ERROR              -24
  38 #define LV1_INVALID_DATA_FORMAT         -25
  39 #define LV1_INVALID_OPERATION           -26
  40 #define LV1_INTERNAL_ERROR              -32768
  41
  42 static inline uint64_t
  43 lv1_repository_string(const char *str)
  44 {
  45         uint64_t ret = 0;
  46         strncpy((char *)&ret, str, sizeof(ret));
  47         return (ret);
  48 }
  49
  50 int lv1_allocate_memory(uint64_t size, uint64_t log_page_size, uint64_t zero, uint64_t flags, uint64_t *base_addr, uint64_t *muid);
  51 int lv1_write_htab_entry(uint64_t vas_id, uint64_t slot, uint64_t pte_hi, uint64_t pte_lo);
  52 int lv1_construct_virtual_address_space(uint64_t log_pteg_count, uint64_t n_sizes, uint64_t page_sizes, uint64_t *vas_id, uint64_t *hv_pteg_count);
  53 int lv1_get_virtual_address_space_id_of_ppe(uint64_t ppe_id, uint64_t *vas_id);
  54 int lv1_query_logical_partition_address_region_info(uint64_t lpar_id, uint64_t *base_addr, uint64_t *size, uint64_t *access_right, uint64_t *max_page_size, uint64_t *flags);
  55 int lv1_select_virtual_address_space(uint64_t vas_id);
  56 int lv1_pause(uint64_t mode);
  57 int lv1_destruct_virtual_address_space(uint64_t vas_id);
  58 int lv1_configure_irq_state_bitmap(uint64_t ppe_id, uint64_t cpu_id, uint64_t bitmap_addr);
  59 int lv1_connect_irq_plug_ext(uint64_t ppe_id, uint64_t cpu_id, uint64_t virq, uint64_t outlet, uint64_t zero);
  60 int lv1_release_memory(uint64_t base_addr);
  61 int lv1_put_iopte(uint64_t ioas_id, uint64_t ioif_addr, uint64_t lpar_addr, uint64_t io_id, uint64_t flags);
  62 int lv1_disconnect_irq_plug_ext(uint64_t ppe_id, uint64_t cpu_id, uint64_t virq);
  63 int lv1_construct_event_receive_port(uint64_t *outlet);
  64 int lv1_destruct_event_receive_port(uint64_t outlet);
  65 int lv1_send_event_locally(uint64_t outlet);
  66 int lv1_end_of_interrupt(uint64_t irq);
  67 int lv1_connect_irq_plug(uint64_t virq, uint64_t irq);
  68 int lv1_disconnect_irq_plus(uint64_t virq);
  69 int lv1_end_of_interrupt_ext(uint64_t ppe_id, uint64_t cpu_id, uint64_t virq);
  70 int lv1_did_update_interrupt_mask(uint64_t ppe_id, uint64_t cpu_id);
  71 int lv1_shutdown_logical_partition(uint64_t cmd);
  72 int lv1_destruct_logical_spe(uint64_t spe_id);
  73 int lv1_construct_logical_spe(uint64_t pshift1, uint64_t pshift2, uint64_t pshift3, uint64_t pshift4, uint64_t pshift5, uint64_t vas_id, uint64_t spe_type, uint64_t *priv2_addr, uint64_t *problem_phys, uint64_t *local_store_phys, uint64_t *unused, uint64_t *shadow_addr, uint64_t *spe_id);
  74 int lv1_set_spe_interrupt_mask(uint64_t spe_id, uint64_t class, uint64_t mask);
  75 int lv1_disable_logical_spe(uint64_t spe_id, uint64_t zero);
  76 int lv1_clear_spe_interrupt_status(uint64_t spe_id, uint64_t class, uint64_t stat, uint64_t zero);
  77 int lv1_get_spe_interrupt_status(uint64_t spe_id, uint64_t class, uint64_t *stat);
  78 int lv1_get_logical_ppe_id(uint64_t *ppe_id);
  79 int lv1_get_logical_partition_id(uint64_t *lpar_id);
  80 int lv1_get_spe_irq_outlet(uint64_t spe_id, uint64_t class, uint64_t *outlet);
  81 int lv1_set_spe_privilege_state_area_1_register(uint64_t spe_id, uint64_t offset, uint64_t value);
  82 int lv1_get_repository_node_value(uint64_t lpar_id, uint64_t n1, uint64_t n2, uint64_t n3, uint64_t n4, uint64_t *v1, uint64_t *v2);
  83 int lv1_read_htab_entries(uint64_t vas_id, uint64_t slot, uint64_t *hi1, uint64_t *hi2, uint64_t *hi3, uint64_t *hi4, uint64_t *rcbits);
  84 int lv1_set_dabr(uint64_t dabr, uint64_t flags);
  85 int lv1_allocate_io_segment(uint64_t ioas_id, uint64_t seg_size, uint64_t io_pagesize, uint64_t *ioif_addr);
  86 int lv1_release_io_segment(uint64_t ioas_id, uint64_t ioif_addr);
  87 int lv1_construct_io_irq_outlet(uint64_t interrupt_id, uint64_t *outlet);
  88 int lv1_destruct_io_irq_outlet(uint64_t outlet);
  89 int lv1_map_htab(uint64_t lpar_id, uint64_t *htab_addr);
  90 int lv1_unmap_htab(uint64_t htab_addr);
  91 int lv1_get_version_info(uint64_t *firm_vers);
  92 int lv1_insert_htab_entry(uint64_t vas_id, uint64_t pteg, uint64_t pte_hi, uint64_t pte_lo, uint64_t lockflags, uint64_t flags, uint64_t *index, uint64_t *evicted_hi, uint64_t *evicted_lo);
  93 int lv1_read_virtual_uart(uint64_t port, uint64_t buffer, uint64_t bytes, uint64_t *bytes_read);
  94 int lv1_write_virtual_uart(uint64_t port, uint64_t buffer, uint64_t bytes, uint64_t *bytes_written);
  95 int lv1_set_virtual_uart_param(uint64_t port, uint64_t param, uint64_t value);
  96 int lv1_get_virtual_uart_param(uint64_t port, uint64_t param, uint64_t *value);
  97 int lv1_configure_virtual_uart(uint64_t lpar_addr, uint64_t *outlet);
  98 int lv1_open_device(uint64_t bus, uint64_t dev, uint64_t zero);
  99 int lv1_close_device(uint64_t bus, uint64_t dev);
 100 int lv1_map_device_mmio_region(uint64_t bus, uint64_t dev, uint64_t bus_addr, uint64_t size, uint64_t page_size, uint64_t *lpar_addr);
 101 int lv1_unmap_device_mmio_region(uint64_t bus, uint64_t dev, uint64_t lpar_addr);
 102 int lv1_allocate_device_dma_region(uint64_t bus, uint64_t dev, uint64_t io_size, uint64_t io_pagesize, uint64_t flag, uint64_t *dma_region);
 103 int lv1_free_device_dma_region(uint64_t bus, uint64_t dev, uint64_t dma_region);
 104 int lv1_map_device_dma_region(uint64_t bus, uint64_t dev, uint64_t lpar_addr, uint64_t dma_region, uint64_t size, uint64_t flags);
 105 int lv1_unmap_device_dma_region(uint64_t bus, uint64_t dev, uint64_t dma_region, uint64_t size);
 106 int lv1_read_pci_config(uint64_t ps3bus, uint64_t bus, uint64_t dev, uint64_t func, uint64_t offset, uint64_t size, uint64_t *result);
 107 int lv1_write_pci_config(uint64_t ps3bus, uint64_t bus, uint64_t dev, uint64_t func, uint64_t offset, uint64_t size, uint64_t data);
 108 int lv1_net_add_multicast_address(uint64_t bus, uint64_t dev, uint64_t addr, uint64_t flags);
 109 int lv1_net_remove_multicast_address(uint64_t bus, uint64_t dev, uint64_t zero, uint64_t one);
 110 int lv1_net_start_tx_dma(uint64_t bus, uint64_t dev, uint64_t bus_addr, uint64_t zero);
 111 int lv1_net_stop_tx_dma(uint64_t bus, uint64_t dev, uint64_t zero);
 112 int lv1_net_start_rx_dma(uint64_t bus, uint64_t dev, uint64_t bus_addr, uint64_t zero);
 113 int lv1_net_stop_rx_dma(uint64_t bus, uint64_t dev, uint64_t zero);
 114 int lv1_net_set_interrupt_status_indicator(uint64_t bus, uint64_t dev, uint64_t irq_status_addr, uint64_t zero);
 115 int lv1_net_set_interrupt_mask(uint64_t bus, uint64_t dev, uint64_t mask, uint64_t zero);
 116 int lv1_net_control(uint64_t bus, uint64_t dev, uint64_t p1, uint64_t p2, uint64_t p3, uint64_t p4, uint64_t *v1, uint64_t *v2);
 117 int lv1_connect_interrupt_event_receive_port(uint64_t bus, uint64_t dev, uint64_t outlet, uint64_t irq);
 118 int lv1_disconnect_interrupt_event_receive_port(uint64_t bus, uint64_t dev, uint64_t outlet, uint64_t irq);
 119 int lv1_deconfigure_virtual_uart_irq(void);
 120 int lv1_enable_logical_spe(uint64_t spe_id, uint64_t resource_id);
 121 int lv1_gpu_open(uint64_t zero);
 122 int lv1_gpu_close(void);
 123 int lv1_gpu_device_map(uint64_t dev, uint64_t *lpar_addr, uint64_t *lpar_size);
 124 int lv1_gpu_device_unmap(uint64_t dev);
 125 int lv1_gpu_memory_allocate(uint64_t ddr_size, uint64_t zero1, uint64_t zero2, uint64_t zero3, uint64_t zero4, uint64_t *handle, uint64_t *ddr_lpar);
 126 int lv1_gpu_memory_free(uint64_t handle);
 127 int lv1_gpu_context_allocate(uint64_t handle, uint64_t flags, uint64_t *chandle, uint64_t *lpar_dma_control, uint64_t *lpar_driver_info, uint64_t *lpar_reports, uint64_t *lpar_reports_size);
 128 int lv1_gpu_context_free(uint64_t chandle);
 129 int lv1_gpu_context_iomap(uint64_t changle, uint64_t gpu_ioif, uint64_t xdr_lpar, uint64_t fbsize, uint64_t ioflags);
 130 int lv1_gpu_context_attribute(uint64_t chandle, uint64_t op, uint64_t p1, uint64_t p2, uint64_t p3, uint64_t p4);
 131 int lv1_gpu_context_intr(uint64_t chandle, uint64_t *v1);
 132 int lv1_gpu_attribute(uint64_t p1, uint64_t p2, uint64_t p3, uint64_t p4, uint64_t p5);
 133 int lv1_get_rtc(uint64_t *rtc_val, uint64_t *timebase);
 134 int lv1_storage_read(uint64_t dev, uint64_t region, uint64_t sector, uint64_t nsectors, uint64_t flags, uint64_t buf, uint64_t *dma_tag);
 135 int lv1_storage_write(uint64_t dev, uint64_t region, uint64_t sector, uint64_t nsectors, uint64_t flags, uint64_t buf, uint64_t *dma_tag);
 136 int lv1_storage_send_device_command(uint64_t dev, uint64_t cmd_id, uint64_t cmd_block, uint64_t cmd_size, uint64_t data_buf, uint64_t blocks, uint64_t *dma_tag);
 137 int lv1_storage_get_async_status(uint64_t dev, uint64_t *dma_tag, uint64_t *status);
 138 int lv1_storage_check_async_status(uint64_t dev, uint64_t dma_tag, uint64_t *status);
 139 int lv1_panic(uint64_t howto);