From b0ff1d56191e6faceec2ca10c290cdf4ea03bb32 Mon Sep 17 00:00:00 2001 From: Matthias Schmidt Date: Thu, 10 Jan 2008 10:44:28 +0000 Subject: [PATCH] Add support for network devices found on Intel ICH9 hardware. I have one of these devices in a 3GHz Core 2 Duo. More information can be found here: http://download.intel.com/design/chipsets/datashts/31697202.pdf The diff is rather trivial, but let me know if I broke something :) em0@pci0:25:0: class=0x020000 card=0x00018086 chip=0x10bd8086 rev=0x02 hdr=0x00 vendor = 'Intel Corporation' device = '82566DM-2 Gigabit Network Connection' class = network subclass = ethernet em0: port 0x30e0-0x30ff mem 0x93224000-0x93224fff,0x93200000-0x9321ffff irq 11 at device 25.0 on pci0 Reviewed-by: sephe@ Taken-in-pieces-from: FreeBSD --- sys/dev/netif/em/if_em.c | 25 +++++++++++- sys/dev/netif/em/if_em_hw.c | 95 ++++++++++++++++++++++++++++----------------- sys/dev/netif/em/if_em_hw.h | 14 ++++++- 3 files changed, 96 insertions(+), 38 deletions(-) diff --git a/sys/dev/netif/em/if_em.c b/sys/dev/netif/em/if_em.c index 13f7865ac8..09e3f5bf3d 100644 --- a/sys/dev/netif/em/if_em.c +++ b/sys/dev/netif/em/if_em.c @@ -64,7 +64,7 @@ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $DragonFly: src/sys/dev/netif/em/if_em.c,v 1.61 2007/11/26 11:05:58 sephe Exp $ + * $DragonFly: src/sys/dev/netif/em/if_em.c,v 1.62 2008/01/10 10:44:28 matthias Exp $ * $FreeBSD$ */ /* @@ -212,6 +212,10 @@ static em_vendor_info_t em_vendor_info_array[] = { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, + PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, + PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, @@ -238,6 +242,17 @@ static em_vendor_info_t em_vendor_info_array[] = { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, + + { 0x8086, E1000_DEV_ID_82575EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, + PCI_ANY_ID, PCI_ANY_ID, 0}, + { 0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, + PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, 0x101A, PCI_ANY_ID, PCI_ANY_ID, 0}, { 0x8086, 0x1014, PCI_ANY_ID, PCI_ANY_ID, 0}, /* required last entry */ @@ -867,6 +882,7 @@ em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) /* FALLTHROUGH */ case em_82571: case em_82572: + case em_ich9lan: case em_80003es2lan: /* Limit Jumbo Frame size */ max_frame_size = 9234; break; @@ -1051,6 +1067,10 @@ em_init(void *arg) case em_ich8lan: pba = E1000_PBA_8K; break; + case em_ich9lan: +#define E1000_PBA_10K 0x000A + pba = E1000_PBA_10K; + break; default: /* Devices before 82547 had a Packet Buffer of 64K. */ if(adapter->hw.max_frame_size > EM_RXBUFFER_8192) @@ -1964,7 +1984,8 @@ em_allocate_pci_resources(device_t dev) } /* For ICH8 we need to find the flash memory. */ - if (adapter->hw.mac_type == em_ich8lan) { + if ((adapter->hw.mac_type == em_ich8lan) || + (adapter->hw.mac_type == em_ich9lan)) { rid = EM_FLASH; adapter->flash_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); diff --git a/sys/dev/netif/em/if_em_hw.c b/sys/dev/netif/em/if_em_hw.c index 72fa4a651b..4e969d38a5 100644 --- a/sys/dev/netif/em/if_em_hw.c +++ b/sys/dev/netif/em/if_em_hw.c @@ -30,7 +30,7 @@ POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ /*$FreeBSD: src/sys/dev/em/if_em_hw.c,v 1.1.2.8 2003/06/09 21:43:41 pdeuskar Exp $*/ -/*$DragonFly: src/sys/dev/netif/em/if_em_hw.c,v 1.11 2006/12/23 10:39:16 sephe Exp $*/ +/*$DragonFly: src/sys/dev/netif/em/if_em_hw.c,v 1.12 2008/01/10 10:44:28 matthias Exp $*/ /* if_em_hw.c * Shared functions for accessing and configuring the MAC @@ -424,6 +424,13 @@ em_set_mac_type(struct em_hw *hw) case E1000_DEV_ID_ICH8_IGP_M: hw->mac_type = em_ich8lan; break; + case E1000_DEV_ID_ICH9_IGP_AMT: + case E1000_DEV_ID_ICH9_IGP_C: + case E1000_DEV_ID_ICH9_IFE: + case E1000_DEV_ID_ICH9_IFE_GT: + case E1000_DEV_ID_ICH9_IFE_G: + hw->mac_type = em_ich9lan; + break; default: /* Should never have loaded on this device */ return -E1000_ERR_MAC_TYPE; @@ -431,6 +438,7 @@ em_set_mac_type(struct em_hw *hw) switch (hw->mac_type) { case em_ich8lan: + case em_ich9lan: hw->swfwhw_semaphore_present = TRUE; hw->asf_firmware_present = TRUE; break; @@ -487,6 +495,7 @@ em_set_media_type(struct em_hw *hw) hw->media_type = em_media_type_fiber; break; case em_ich8lan: + case em_ich9lan: case em_82573: /* The STATUS_TBIMODE bit is reserved or reused for the this * device. @@ -623,6 +632,7 @@ em_reset_hw(struct em_hw *hw) E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); break; case em_ich8lan: + case em_ich9lan: if (!hw->phy_reset_disable && em_check_phy_reset_block(hw) == E1000_SUCCESS) { /* em_ich8lan PHY HW reset requires MAC CORE reset @@ -713,7 +723,7 @@ em_reset_hw(struct em_hw *hw) em_pci_set_mwi(hw); } - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { uint32_t kab = E1000_READ_REG(hw, KABGTXD); kab |= E1000_KABGTXD_BGSQLBIAS; E1000_WRITE_REG(hw, KABGTXD, kab); @@ -796,6 +806,7 @@ em_initialize_hardware_bits(struct em_hw *hw) E1000_WRITE_REG(hw, TARC1, reg_tarc1); break; case em_ich8lan: + case em_ich9lan: if ((hw->revision_id < 3) || ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) @@ -862,7 +873,6 @@ em_init_hw(struct em_hw *hw) reg_data &= ~0x80000000; E1000_WRITE_REG(hw, STATUS, reg_data); } - /* Initialize Identification LED */ ret_val = em_id_led_init(hw); if (ret_val) { @@ -908,7 +918,7 @@ em_init_hw(struct em_hw *hw) /* Zero out the Multicast HASH table */ DEBUGOUT("Zeroing the MTA\n"); mta_size = E1000_MC_TBL_SIZE; - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) mta_size = E1000_MC_TBL_SIZE_ICH8LAN; for (i = 0; i < mta_size; i++) { E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); @@ -954,7 +964,7 @@ em_init_hw(struct em_hw *hw) } /* More time needed for PHY to initialize */ - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) msec_delay(15); /* Call a subroutine to configure the link and setup flow control. */ @@ -998,6 +1008,7 @@ em_init_hw(struct em_hw *hw) /* Fall through */ case em_82571: case em_82572: + case em_ich9lan: case em_ich8lan: ctrl = E1000_READ_REG(hw, TXDCTL1); ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; @@ -1115,6 +1126,7 @@ em_setup_link(struct em_hw *hw) if (hw->fc == E1000_FC_DEFAULT) { switch (hw->mac_type) { case em_ich8lan: + case em_ich9lan: case em_82573: hw->fc = E1000_FC_FULL; break; @@ -1951,6 +1963,7 @@ em_setup_copper_link(struct em_hw *hw) switch (hw->mac_type) { case em_80003es2lan: case em_ich8lan: + case em_ich9lan: /* Set the mac to wait the maximum time between each * iteration and increase the max iterations when * polling the phy; this fixes erroneous timeouts at 10Mbps. */ @@ -3859,7 +3872,8 @@ em_phy_hw_reset(struct em_hw *hw) return ret_val; em_release_software_semaphore(hw); - if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) + if (((hw->mac_type == em_ich8lan) || (hw->mac_type == em_ich9lan)) + && (hw->phy_type == em_phy_igp_3)) ret_val = em_init_lcd_from_nvm(hw); return ret_val; @@ -4102,6 +4116,7 @@ em_detect_gig_phy(struct em_hw *hw) if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; break; case em_ich8lan: + case em_ich9lan: if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; @@ -4550,6 +4565,7 @@ em_init_eeprom_params(struct em_hw *hw) eeprom->use_eewr = FALSE; break; case em_ich8lan: + case em_ich9lan: { int32_t i = 0; uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); @@ -5169,7 +5185,7 @@ em_is_onboard_nvm_eeprom(struct em_hw *hw) DEBUGFUNC("em_is_onboard_nvm_eeprom"); - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) return FALSE; if (hw->mac_type == em_82573) { @@ -5222,7 +5238,7 @@ em_validate_eeprom_checksum(struct em_hw *hw) } } - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { /* Drivers must allocate the shadow ram structure for the * EEPROM checksum to be updated. Otherwise, this bit as well * as the checksum must both be set correctly for this @@ -5235,7 +5251,7 @@ em_validate_eeprom_checksum(struct em_hw *hw) em_update_eeprom_checksum(hw); } } - + for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { DEBUGOUT("EEPROM Read Error\n"); @@ -5565,7 +5581,8 @@ em_commit_shadow_ram(struct em_hw *hw) } } - if (hw->mac_type == em_ich8lan && hw->eeprom_shadow_ram != NULL) { + if (((hw->mac_type == em_ich8lan) || (hw->mac_type == em_ich9lan)) && + hw->eeprom_shadow_ram != NULL) { /* We're writing to the opposite bank so if we're on bank 1, * write to bank 0 etc. We also need to erase the segment that * is going to be written */ @@ -5777,7 +5794,7 @@ em_init_rx_addrs(struct em_hw *hw) * the other port. */ if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) rar_num -= 1; - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) rar_num = E1000_RAR_ENTRIES_ICH8LAN; /* Zero out the other 15 receive addresses. */ @@ -5824,7 +5841,7 @@ em_mc_addr_list_update(struct em_hw *hw, /* Clear RAR[1-15] */ DEBUGOUT(" Clearing RAR[1-15]\n"); num_rar_entry = E1000_RAR_ENTRIES; - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; /* Reserve a spot for the Locally Administered Address to work around @@ -5843,7 +5860,7 @@ em_mc_addr_list_update(struct em_hw *hw, /* Clear the MTA */ DEBUGOUT(" Clearing MTA\n"); num_mta_entry = E1000_NUM_MTA_REGISTERS; - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; for (i = 0; i < num_mta_entry; i++) { @@ -5904,7 +5921,7 @@ em_hash_mc_addr(struct em_hw *hw, * LSB MSB */ case 0: - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { /* [47:38] i.e. 0x158 for above example address */ hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); } else { @@ -5913,7 +5930,7 @@ em_hash_mc_addr(struct em_hw *hw, } break; case 1: - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { /* [46:37] i.e. 0x2B1 for above example address */ hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); } else { @@ -5922,7 +5939,7 @@ em_hash_mc_addr(struct em_hw *hw, } break; case 2: - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { /*[45:36] i.e. 0x163 for above example address */ hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); } else { @@ -5931,7 +5948,7 @@ em_hash_mc_addr(struct em_hw *hw, } break; case 3: - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { /* [43:34] i.e. 0x18D for above example address */ hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); } else { @@ -5942,7 +5959,7 @@ em_hash_mc_addr(struct em_hw *hw, } hash_value &= 0xFFF; - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) hash_value &= 0x3FF; return hash_value; @@ -5971,7 +5988,7 @@ em_mta_set(struct em_hw *hw, * register are determined by the lower 5 bits of the value. */ hash_reg = (hash_value >> 5) & 0x7F; - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) hash_reg &= 0x1F; hash_bit = hash_value & 0x1F; @@ -6068,7 +6085,7 @@ em_write_vfta(struct em_hw *hw, { uint32_t temp; - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) return; if ((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) { @@ -6096,7 +6113,7 @@ em_clear_vfta(struct em_hw *hw) uint32_t vfta_offset = 0; uint32_t vfta_bit_in_reg = 0; - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) return; if (hw->mac_type == em_82573) { @@ -6154,7 +6171,7 @@ em_id_led_init(struct em_hw * hw) eeprom_data = ID_LED_DEFAULT_82573; else if ((eeprom_data == ID_LED_RESERVED_0000) || (eeprom_data == ID_LED_RESERVED_FFFF)) { - if (hw->mac_type == em_ich8lan) + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) eeprom_data = ID_LED_DEFAULT_ICH8LAN; else eeprom_data = ID_LED_DEFAULT; @@ -6465,7 +6482,7 @@ em_clear_hw_cntrs(struct em_hw *hw) temp = E1000_READ_REG(hw, XOFFTXC); temp = E1000_READ_REG(hw, FCRUC); - if (hw->mac_type != em_ich8lan) { + if (hw->mac_type != em_ich8lan && hw->mac_type != em_ich9lan) { temp = E1000_READ_REG(hw, PRC64); temp = E1000_READ_REG(hw, PRC127); temp = E1000_READ_REG(hw, PRC255); @@ -6494,7 +6511,7 @@ em_clear_hw_cntrs(struct em_hw *hw) temp = E1000_READ_REG(hw, TPR); temp = E1000_READ_REG(hw, TPT); - if (hw->mac_type != em_ich8lan) { + if (hw->mac_type != em_ich8lan && hw->mac_type != em_ich9lan) { temp = E1000_READ_REG(hw, PTC64); temp = E1000_READ_REG(hw, PTC127); temp = E1000_READ_REG(hw, PTC255); @@ -6526,7 +6543,7 @@ em_clear_hw_cntrs(struct em_hw *hw) temp = E1000_READ_REG(hw, IAC); temp = E1000_READ_REG(hw, ICRXOC); - if (hw->mac_type == em_ich8lan) return; + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) return; temp = E1000_READ_REG(hw, ICRXPTC); temp = E1000_READ_REG(hw, ICRXATC); @@ -6720,6 +6737,7 @@ em_get_bus_info(struct em_hw *hw) PCI_EX_LINK_WIDTH_SHIFT; break; case em_ich8lan: + case em_ich9lan: hw->bus_type = em_bus_type_pci_express; hw->bus_speed = em_bus_speed_2500; hw->bus_width = em_bus_width_pciex_1; @@ -7358,7 +7376,7 @@ em_set_d3_lplu_state(struct em_hw *hw, ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); if (ret_val) return ret_val; - } else if (hw->mac_type == em_ich8lan) { + } else if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { /* MAC writes into PHY register based on the state transition * and start auto-negotiation. SW driver can overwrite the settings * in CSR PHY power control E1000_PHY_CTRL register. */ @@ -7377,7 +7395,7 @@ em_set_d3_lplu_state(struct em_hw *hw, if (ret_val) return ret_val; } else { - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); } else { @@ -7428,7 +7446,7 @@ em_set_d3_lplu_state(struct em_hw *hw, if (ret_val) return ret_val; } else { - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); } else { @@ -7480,7 +7498,7 @@ em_set_d0_lplu_state(struct em_hw *hw, if (hw->mac_type <= em_82547_rev_2) return E1000_SUCCESS; - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); } else { ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); @@ -7489,7 +7507,7 @@ em_set_d0_lplu_state(struct em_hw *hw, } if (!active) { - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); } else { @@ -7530,7 +7548,7 @@ em_set_d0_lplu_state(struct em_hw *hw, } else { - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); } else { @@ -7817,7 +7835,7 @@ em_check_mng_mode(struct em_hw *hw) fwsm = E1000_READ_REG(hw, FWSM); - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich8lan) { if ((fwsm & E1000_FWSM_MODE_MASK) == (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) return TRUE; @@ -8126,6 +8144,7 @@ em_get_auto_rd_done(struct em_hw *hw) case em_82572: case em_82573: case em_80003es2lan: + case em_ich9lan: case em_ich8lan: while (timeout) { if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) @@ -8355,7 +8374,7 @@ em_check_phy_reset_block(struct em_hw *hw) uint32_t manc = 0; uint32_t fwsm = 0; - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { fwsm = E1000_READ_REG(hw, FWSM); return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS : E1000_BLK_PHY_RESET; @@ -8387,6 +8406,7 @@ em_arc_subsystem_valid(struct em_hw *hw) return TRUE; break; case em_ich8lan: + case em_ich9lan: return TRUE; default: break; @@ -8453,7 +8473,7 @@ em_get_software_flag(struct em_hw *hw) DEBUGFUNC("em_get_software_flag"); - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { while (timeout) { extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; @@ -8491,7 +8511,7 @@ em_release_software_flag(struct em_hw *hw) DEBUGFUNC("em_release_software_flag"); - if (hw->mac_type == em_ich8lan) { + if (hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) { extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); @@ -8996,6 +9016,11 @@ em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) } else if (hsfsts.hsf_status.berasesz == 0x1) { bank_size = ICH_FLASH_SEG_SIZE_4K; iteration = 1; + } else if (hsfsts.hsf_status.berasesz == 0x2) { + if (hw->mac_type == em_ich9lan) { + sub_sector_size = ICH_FLASH_SEG_SIZE_8K; + iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; + } } else if (hsfsts.hsf_status.berasesz == 0x3) { bank_size = ICH_FLASH_SEG_SIZE_64K; iteration = 1; diff --git a/sys/dev/netif/em/if_em_hw.h b/sys/dev/netif/em/if_em_hw.h index b58b6ee718..77af80ce41 100644 --- a/sys/dev/netif/em/if_em_hw.h +++ b/sys/dev/netif/em/if_em_hw.h @@ -30,7 +30,7 @@ POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ /*$FreeBSD: src/sys/dev/em/if_em_hw.h,v 1.1.2.8 2003/06/09 21:43:41 pdeuskar Exp $*/ -/*$DragonFly: src/sys/dev/netif/em/if_em_hw.h,v 1.11 2006/12/23 10:39:16 sephe Exp $*/ +/*$DragonFly: src/sys/dev/netif/em/if_em_hw.h,v 1.12 2008/01/10 10:44:28 matthias Exp $*/ /* if_em_hw.h * Structures, enums, and macros for the MAC @@ -72,6 +72,7 @@ typedef enum { em_82573, em_80003es2lan, em_ich8lan, + em_ich9lan, em_num_macs } em_mac_type; @@ -471,6 +472,8 @@ int32_t em_check_phy_reset_block(struct em_hw *hw); #define E1000_DEV_ID_82547EI_MOBILE 0x101A #define E1000_DEV_ID_82571EB_COPPER 0x105E #define E1000_DEV_ID_82571EB_FIBER 0x105F +#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 +#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 #define E1000_DEV_ID_82571EB_SERDES 0x1060 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC @@ -494,6 +497,14 @@ int32_t em_check_phy_reset_block(struct em_hw *hw); #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 #define E1000_DEV_ID_ICH8_IGP_M 0x104D +#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD +#define E1000_DEV_ID_ICH9_IGP_C 0x294C +#define E1000_DEV_ID_ICH9_IFE 0x10C0 +#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 +#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 +#define E1000_DEV_ID_82575EB_COPPER 0x10A7 +#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 +#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 #define NODE_ADDRESS_SIZE 6 @@ -3278,6 +3289,7 @@ struct em_host_command_info { #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ #define ICH_FLASH_SEG_SIZE_256 256 #define ICH_FLASH_SEG_SIZE_4K 4096 +#define ICH_FLASH_SEG_SIZE_8K 8192 #define ICH_FLASH_SEG_SIZE_64K 65536 #define ICH_CYCLE_READ 0x0 -- 2.11.4.GIT