| commit | 4013580e521a076ec4ee86e0516e8652e0c087f8 | |
| author | Imre Vadász <imre@vdsz.com> | |
| Sat, 7 Jan 2017 21:44:07 +0000 (7 22:44 +0100) | ||
| committer | Imre Vadász <imre@vdsz.com> | |
| Sun, 14 May 2017 15:36:37 +0000 (14 17:36 +0200) | ||
| tree | 6bc5ae8fea3a33b46a691cd3e2b94903b6221a0c | treesnapshot (tar.gz zip) |
| parent | 41c3a3cdf40dd4bae4b3a2a0eda1c46fc7d2522e | commitdiff |
sdhci - Implement ADMA2 transfer support. Keep SDMA support for now.
* Using ADMA2 transfers, only generates 1 or 2 interrupts for each
bio transfer, whereas the existing SDMA code was only transferring
in 4K blocks (with a completion interrupt for each 4K block).
* Since support for UHS high-speed modes is still missing this might
only give a small performance increase in many cases.
With very aggressive CPU C-state power-management and/or very slow
CPUs, this can improve performance a lot however. e.g. on an Atom
x5-Z8300 at 480MHz using deepest mwait c-state setting:
- eMMC read speed: ca. 17 MiB/s --> 30 MiB/s
- SD-card read speed: ca. 11MiB/s --> 18MiB/s
* Using ADMA2 transfers, only generates 1 or 2 interrupts for each
bio transfer, whereas the existing SDMA code was only transferring
in 4K blocks (with a completion interrupt for each 4K block).
* Since support for UHS high-speed modes is still missing this might
only give a small performance increase in many cases.
With very aggressive CPU C-state power-management and/or very slow
CPUs, this can improve performance a lot however. e.g. on an Atom
x5-Z8300 at 480MHz using deepest mwait c-state setting:
- eMMC read speed: ca. 17 MiB/s --> 30 MiB/s
- SD-card read speed: ca. 11MiB/s --> 18MiB/s
| sys/dev/disk/sdhci/sdhci.c | diffblobblamehistory | |
| sys/dev/disk/sdhci/sdhci.h | diffblobblamehistory |