?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Import 2.3.18pre1
[davej-history.git] / drivers / pcmcia / i82365.c
blob225ffa7579180b5ff2da3ca80bf33777f39c014a
1 /*======================================================================
2
3 Device driver for Intel 82365 and compatible PC Card controllers,
4 and Yenta-compatible PCI-to-CardBus controllers.
5
6 i82365.c 1.251 1999/09/07 15:19:23
7
8 The contents of this file are subject to the Mozilla Public
9 License Version 1.1 (the "License"); you may not use this file
10 except in compliance with the License. You may obtain a copy of
11 the License at http://www.mozilla.org/MPL/
12
13 Software distributed under the License is distributed on an "AS
14 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 rights and limitations under the License.
17
18 The initial developer of the original code is David A. Hinds
19 <dhinds@hyper.stanford.edu>. Portions created by David A. Hinds
20 are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
21
22 Alternatively, the contents of this file may be used under the
23 terms of the GNU Public License version 2 (the "GPL"), in which
24 case the provisions of the GPL are applicable instead of the
25 above. If you wish to allow the use of your version of this file
26 only under the terms of the GPL and not to allow others to use
27 your version of this file under the MPL, indicate your decision
28 by deleting the provisions above and replace them with the notice
29 and other provisions required by the GPL. If you do not delete
30 the provisions above, a recipient may use your version of this
31 file under either the MPL or the GPL.
32
33 ======================================================================*/
34
35 #include <linux/module.h>
36 #include <linux/types.h>
37 #include <linux/fcntl.h>
38 #include <linux/string.h>
39 #include <linux/kernel.h>
40 #include <linux/errno.h>
41 #include <linux/timer.h>
42 #include <linux/sched.h>
43 #include <linux/malloc.h>
44 #include <linux/pci.h>
45 #include <linux/ioport.h>
46 #include <linux/delay.h>
47 #include <linux/proc_fs.h>
48 #include <asm/irq.h>
49 #include <asm/io.h>
50 #include <asm/bitops.h>
51 #include <asm/segment.h>
52 #include <asm/system.h>
53
54 #include <pcmcia/version.h>
55 #include <pcmcia/cs_types.h>
56 #include <pcmcia/ss.h>
57 #include <pcmcia/cs.h>
58
59 /* ISA-bus controllers */
60 #include "i82365.h"
61 #include "cirrus.h"
62 #include "vg468.h"
63 #include "ricoh.h"
64 #include "o2micro.h"
65
66 /* PCI-bus controllers */
67 #include "yenta.h"
68 #include "ti113x.h"
69 #include "smc34c90.h"
70 #include "topic.h"
71
72 #ifdef PCMCIA_DEBUG
73 static int pc_debug = PCMCIA_DEBUG;
74 MODULE_PARM(pc_debug, "i");
75 #define DEBUG(n, args...) do { if (pc_debug>(n)) printk(KERN_DEBUG args); } while (0)
76 static const char *version =
77 "i82365.c $Revision: 1.249 $ $Date: 1999/08/28 04:01:46 $ (David Hinds)";
78 #else
79 #define DEBUG(n, args...) do { } while (0)
80 #endif
81
82 static void irq_count(int, void *, struct pt_regs *);
83 static inline int _check_irq(int irq, int flags)
84 {
85 if (request_irq(irq, irq_count, flags, "x", NULL) == 0) {
86 free_irq(irq, NULL);
87 return 0;
88 }
89 return -1;
90 }
91
92 /*====================================================================*/
93
94 /* Parameters that can be set with 'insmod' */
95
96 #ifdef CONFIG_ISA
97 /* Default base address for i82365sl and other ISA chips */
98 static int i365_base = 0x3e0;
99 /* Should we probe at 0x3e2 for an extra ISA controller? */
100 static int extra_sockets = 0;
101 /* Specify a socket number to ignore */
102 static int ignore = -1;
103 /* Bit map or list of interrupts to choose from */
104 static u_int irq_mask = 0xffff;
105 static int irq_list[16] = { -1 };
106 /* The card status change interrupt -- 0 means autoselect */
107 static int cs_irq = 0;
108 #endif
109
110 /* Probe for safe interrupts? */
111 static int do_scan = 1;
112 /* Poll status interval -- 0 means default to interrupt */
113 static int poll_interval = 0;
114 /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
115 static int cycle_time = 120;
116
117 /* Cirrus options */
118 static int has_dma = -1;
119 static int has_led = -1;
120 static int has_ring = -1;
121 static int dynamic_mode = 0;
122 static int freq_bypass = -1;
123 static int setup_time = -1;
124 static int cmd_time = -1;
125 static int recov_time = -1;
126
127 #ifdef CONFIG_ISA
128 /* Vadem options */
129 static int async_clock = -1;
130 static int cable_mode = -1;
131 static int wakeup = 0;
132 #endif
133
134 #ifdef CONFIG_ISA
135 MODULE_PARM(i365_base, "i");
136 MODULE_PARM(ignore, "i");
137 MODULE_PARM(extra_sockets, "i");
138 MODULE_PARM(irq_mask, "i");
139 MODULE_PARM(irq_list, "1-16i");
140 MODULE_PARM(cs_irq, "i");
141 MODULE_PARM(async_clock, "i");
142 MODULE_PARM(cable_mode, "i");
143 MODULE_PARM(wakeup, "i");
144 #endif
145
146 MODULE_PARM(do_scan, "i");
147 MODULE_PARM(poll_interval, "i");
148 MODULE_PARM(cycle_time, "i");
149 MODULE_PARM(has_dma, "i");
150 MODULE_PARM(has_led, "i");
151 MODULE_PARM(has_ring, "i");
152 MODULE_PARM(dynamic_mode, "i");
153 MODULE_PARM(freq_bypass, "i");
154 MODULE_PARM(setup_time, "i");
155 MODULE_PARM(cmd_time, "i");
156 MODULE_PARM(recov_time, "i");
157
158 #ifdef CONFIG_PCI
159 /* Scan PCI bus? */
160 static int do_pci_probe = 1;
161 /* Default memory base address for CardBus controllers */
162 static u_int cb_mem_base[] = { 0x68000000, 0xf8000000 };
163 static int fast_pci = -1;
164 static int hold_time = -1;
165 /* Override BIOS interrupt routing mode? */
166 static int irq_mode = -1;
167 static int has_clkrun = -1;
168 static int clkrun_sel = -1;
169 static int pci_latency = -1;
170 static int cb_latency = -1;
171 static int cb_bus_base = 0;
172 static int cb_bus_step = 2;
173 static int cb_write_post = -1;
174 MODULE_PARM(do_pci_probe, "i");
175 MODULE_PARM(cb_mem_base, "i");
176 MODULE_PARM(fast_pci, "i");
177 MODULE_PARM(hold_time, "i");
178 MODULE_PARM(irq_mode, "i");
179 MODULE_PARM(has_clkrun, "i");
180 MODULE_PARM(clkrun_sel, "i");
181 MODULE_PARM(pci_latency, "i");
182 MODULE_PARM(cb_latency, "i");
183 MODULE_PARM(cb_bus_base, "i");
184 MODULE_PARM(cb_bus_step, "i");
185 MODULE_PARM(cb_write_post, "i");
186 #endif
187
188 #ifdef CONFIG_ISA
189 #ifdef CONFIG_PCI
190 /* PCI card status change interrupts? */
191 static int pci_csc = 0;
192 /* PCI IO card functional interrupts? */
193 static int pci_int = 0;
194 MODULE_PARM(pci_csc, "i");
195 MODULE_PARM(pci_int, "i");
196 #else /* no PCI */
197 #define pci_csc 0
198 #define pci_int 0
199 #endif
200 #else /* no ISA */
201 #ifdef CONFIG_PCI
202 #define pci_csc 0
203 #define pci_int 1
204 #else
205 #error "No bus architectures defined!"
206 #endif
207 #endif
208
209 /*====================================================================*/
210
211 typedef struct cirrus_state_t {
212 u_char misc1, misc2;
213 u_char timer[6];
214 } cirrus_state_t;
215
216 typedef struct vg46x_state_t {
217 u_char ctl, ema;
218 } vg46x_state_t;
219
220 typedef struct ti113x_state_t {
221 u_int sysctl;
222 u_char cardctl, devctl, diag;
223 } ti113x_state_t;
224
225 typedef struct rl5c4xx_state_t {
226 u_short misc, ctl, io, mem;
227 } rl5c4xx_state_t;
228
229 typedef struct o2micro_state_t {
230 u_char mode_a, mode_b, mode_c, mode_d;
231 u_char mhpg, fifo, mode_e;
232 } o2micro_state_t;
233
234 typedef struct topic_state_t {
235 u_char slot, ccr, cdr;
236 u_int rcr;
237 } topic_state_t;
238
239 typedef struct socket_info_t {
240 u_short type, flags;
241 socket_cap_t cap;
242 u_short ioaddr;
243 u_short psock;
244 u_char cs_irq, intr;
245 void (*handler)(void *info, u_int events);
246 void *info;
247 #ifdef CONFIG_PROC_FS
248 struct proc_dir_entry *proc;
249 #endif
250 #ifdef CONFIG_PCI
251 u_short vendor, device;
252 u_char revision, bus, devfn;
253 u_short bcr;
254 u_char pci_lat, cb_lat, sub_bus;
255 u_char cache, pmcs;
256 u_int cb_phys;
257 char *cb_virt;
258 #endif
259 union {
260 cirrus_state_t cirrus;
261 vg46x_state_t vg46x;
262 #ifdef CONFIG_PCI
263 o2micro_state_t o2micro;
264 ti113x_state_t ti113x;
265 rl5c4xx_state_t rl5c4xx;
266 topic_state_t topic;
267 #endif
268 } state;
269 } socket_info_t;
270
271 /* Where we keep track of our sockets... */
272 static int sockets = 0;
273 static socket_info_t socket[8] = {
274 { 0, }, /* ... */
275 };
276
277 /* Default ISA interrupt mask */
278 #define I365_MASK 0xdeb8 /* irq 15,14,12,11,10,9,7,5,4,3 */
279
280 static void pcic_interrupt_wrapper(u_long);
281 static void pcic_interrupt(int irq, void *dev,
282 struct pt_regs *regs);
283 static int pcic_service(u_int sock, u_int cmd, void *arg);
284 #ifdef CONFIG_PROC_FS
285 static void pcic_proc_remove(u_short sock);
286 #endif
287
288 #ifdef CONFIG_ISA
289 static int grab_irq;
290 static spinlock_t isa_lock = SPIN_LOCK_UNLOCKED;
291 #endif
292 static struct timer_list poll_timer;
293
294 /*====================================================================*/
295
296 #ifdef CONFIG_PCI
297
298 #ifndef PCI_VENDOR_ID_INTEL
299 #define PCI_VENDOR_ID_INTEL 0x8086
300 #endif
301 #ifndef PCI_VENDOR_ID_OMEGA
302 #define PCI_VENDOR_ID_OMEGA 0x119b
303 #endif
304 #ifndef PCI_DEVICE_ID_OMEGA_PCMCIA
305 #define PCI_DEVICE_ID_OMEGA_PCMCIA 0x1221
306 #endif
307
308 /* Default settings for PCI command configuration register */
309 #define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
310 PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
311
312 #endif
313
314 /* These definitions must match the pcic table! */
315 typedef enum pcic_id {
316 #ifdef CONFIG_ISA
317 IS_I82365A, IS_I82365B, IS_I82365DF,
318 IS_IBM, IS_RF5Cx96, IS_VLSI, IS_VG468, IS_VG469,
319 IS_PD6710, IS_PD672X, IS_VT83C469,
320 #endif
321 #ifdef CONFIG_PCI
322 IS_PD6729, IS_PD6730, IS_OZ6729, IS_OZ6730,
323 IS_I82092AA, IS_OM82C092G,
324 IS_PD6832, IS_OZ6832, IS_OZ6836,
325 IS_RL5C465, IS_RL5C466, IS_RL5C475, IS_RL5C476, IS_RL5C478,
326 IS_SMC34C90,
327 IS_TI1130, IS_TI1131, IS_TI1250A, IS_TI1220, IS_TI1221, IS_TI1210,
328 IS_TI1251A, IS_TI1251B, IS_TI1450, IS_TI1225, IS_TI1211, IS_TI1420,
329 IS_TOPIC95_A, IS_TOPIC95_B, IS_TOPIC97,
330 IS_UNK_PCI, IS_UNK_CARDBUS
331 #endif
332 } pcic_id;
333
334 /* Flags for classifying groups of controllers */
335 #define IS_VADEM 0x0001
336 #define IS_CIRRUS 0x0002
337 #define IS_TI 0x0004
338 #define IS_O2MICRO 0x0008
339 #define IS_VIA 0x0010
340 #define IS_TOPIC 0x0020
341 #define IS_RICOH 0x0040
342 #define IS_UNKNOWN 0x0400
343 #define IS_VG_PWR 0x0800
344 #define IS_DF_PWR 0x1000
345 #define IS_PCI 0x2000
346 #define IS_CARDBUS 0x4000
347 #define IS_ALIVE 0x8000
348
349 typedef struct pcic_t {
350 char *name;
351 u_short flags;
352 #ifdef CONFIG_PCI
353 u_short vendor, device;
354 #endif
355 } pcic_t;
356
357 static pcic_t pcic[] = {
358 #ifdef CONFIG_ISA
359 { "Intel i82365sl A step", 0 },
360 { "Intel i82365sl B step", 0 },
361 { "Intel i82365sl DF", IS_DF_PWR },
362 { "IBM Clone", 0 },
363 { "Ricoh RF5C296/396", 0 },
364 { "VLSI 82C146", 0 },
365 { "Vadem VG-468", IS_VADEM },
366 { "Vadem VG-469", IS_VADEM|IS_VG_PWR },
367 { "Cirrus PD6710", IS_CIRRUS },
368 { "Cirrus PD672x", IS_CIRRUS },
369 { "VIA VT83C469", IS_CIRRUS|IS_VIA },
370 #endif
371 #ifdef CONFIG_PCI
372 { "Cirrus PD6729", IS_CIRRUS|IS_PCI,
373 PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729 },
374 { "Cirrus PD6730", IS_CIRRUS|IS_PCI,
375 PCI_VENDOR_ID_CIRRUS, 0xffff },
376 { "O2Micro OZ6729", IS_O2MICRO|IS_PCI|IS_VG_PWR,
377 PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_6729 },
378 { "O2Micro OZ6730", IS_O2MICRO|IS_PCI|IS_VG_PWR,
379 PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_6730 },
380 { "Intel 82092AA", IS_PCI,
381 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_OMEGA_PCMCIA },
382 { "Omega Micro 82C092G", IS_PCI,
383 PCI_VENDOR_ID_OMEGA, PCI_DEVICE_ID_OMEGA_PCMCIA },
384 { "Cirrus PD6832", IS_CIRRUS|IS_CARDBUS,
385 PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832 },
386 { "O2Micro OZ6832/OZ6833", IS_O2MICRO|IS_CARDBUS|IS_VG_PWR,
387 PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_6832 },
388 { "O2Micro OZ6836/OZ6860", IS_O2MICRO|IS_CARDBUS|IS_VG_PWR,
389 PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_6836 },
390 { "Ricoh RL5C465", IS_RICOH|IS_CARDBUS|IS_DF_PWR,
391 PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C465 },
392 { "Ricoh RL5C466", IS_RICOH|IS_CARDBUS|IS_DF_PWR,
393 PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C466 },
394 { "Ricoh RL5C475", IS_RICOH|IS_CARDBUS|IS_DF_PWR,
395 PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C475 },
396 { "Ricoh RL5C476", IS_RICOH|IS_CARDBUS|IS_DF_PWR,
397 PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476 },
398 { "Ricoh RL5C478", IS_RICOH|IS_CARDBUS|IS_DF_PWR,
399 PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C478 },
400 { "SMC 34C90", IS_CARDBUS|IS_DF_PWR,
401 PCI_VENDOR_ID_SMC, PCI_DEVICE_ID_SMC_34C90 },
402 { "TI 1130", IS_TI|IS_CARDBUS|IS_DF_PWR,
403 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1130 },
404 { "TI 1131", IS_TI|IS_CARDBUS|IS_DF_PWR,
405 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1131 },
406 { "TI 1250A", IS_TI|IS_CARDBUS|IS_DF_PWR,
407 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1250A },
408 { "TI 1220", IS_TI|IS_CARDBUS|IS_DF_PWR,
409 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1220 },
410 { "TI 1221", IS_TI|IS_CARDBUS|IS_DF_PWR,
411 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1221 },
412 { "TI 1210", IS_TI|IS_CARDBUS|IS_DF_PWR,
413 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1210 },
414 { "TI 1251A", IS_TI|IS_CARDBUS|IS_DF_PWR,
415 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1251A },
416 { "TI 1251B", IS_TI|IS_CARDBUS|IS_DF_PWR,
417 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1251B },
418 { "TI 1450", IS_TI|IS_CARDBUS|IS_DF_PWR,
419 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1450 },
420 { "TI 1225", IS_TI|IS_CARDBUS|IS_DF_PWR,
421 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1225 },
422 { "TI 1211", IS_TI|IS_CARDBUS|IS_DF_PWR,
423 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1211 },
424 { "TI 1420", IS_TI|IS_CARDBUS|IS_DF_PWR,
425 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420 },
426 { "Toshiba ToPIC95-A", IS_CARDBUS|IS_TOPIC|IS_DF_PWR,
427 PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC95_A },
428 { "Toshiba ToPIC95-B", IS_CARDBUS|IS_TOPIC|IS_DF_PWR,
429 PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC95_B },
430 { "Toshiba ToPIC97", IS_CARDBUS|IS_TOPIC|IS_DF_PWR,
431 PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC97 },
432 { "Unknown", IS_PCI|IS_UNKNOWN, 0, 0 },
433 { "Unknown", IS_CARDBUS|IS_DF_PWR|IS_UNKNOWN, 0, 0 }
434 #endif
435 };
436
437 #define PCIC_COUNT (sizeof(pcic)/sizeof(pcic_t))
438
439 /*====================================================================*/
440
441 /* Some PCI shortcuts */
442
443 #ifdef CONFIG_PCI
444
445 #define pci_readb pcibios_read_config_byte
446 #define pci_writeb pcibios_write_config_byte
447 #define pci_readw pcibios_read_config_word
448 #define pci_writew pcibios_write_config_word
449 #define pci_readl pcibios_read_config_dword
450 #define pci_writel pcibios_write_config_dword
451
452 #define cb_readb(s, r) readb(socket[s].cb_virt + (r))
453 #define cb_readl(s, r) readl(socket[s].cb_virt + (r))
454 #define cb_writeb(s, r, v) writeb(v, socket[s].cb_virt + (r))
455 #define cb_writel(s, r, v) writel(v, socket[s].cb_virt + (r))
456
457 static void cb_get_power(u_short sock, socket_state_t *state);
458 static void cb_set_power(u_short sock, socket_state_t *state);
459 #endif
460
461 /*====================================================================*/
462
463 static u_char i365_get(u_short sock, u_short reg)
464 {
465 #ifdef CONFIG_PCI
466 if (socket[sock].cb_virt)
467 return cb_readb(sock, 0x0800 + reg);
468 else
469 #endif
470 {
471 u_short port = socket[sock].ioaddr;
472 u_char val;
473 reg = I365_REG(socket[sock].psock, reg);
474 outb(reg, port); val = inb(port+1);
475 return val;
476 }
477 }
478
479 static void i365_set(u_short sock, u_short reg, u_char data)
480 {
481 #ifdef CONFIG_PCI
482 if (socket[sock].cb_virt)
483 cb_writeb(sock, 0x0800 + reg, data);
484 else
485 #endif
486 {
487 u_short port = socket[sock].ioaddr;
488 u_char val = I365_REG(socket[sock].psock, reg);
489 outb(val, port); outb(data, port+1);
490 }
491 }
492
493 static void i365_bset(u_short sock, u_short reg, u_char mask)
494 {
495 u_char d = i365_get(sock, reg);
496 d |= mask;
497 i365_set(sock, reg, d);
498 }
499
500 static void i365_bclr(u_short sock, u_short reg, u_char mask)
501 {
502 u_char d = i365_get(sock, reg);
503 d &= ~mask;
504 i365_set(sock, reg, d);
505 }
506
507 static void i365_bflip(u_short sock, u_short reg, u_char mask, int b)
508 {
509 u_char d = i365_get(sock, reg);
510 if (b)
511 d |= mask;
512 else
513 d &= ~mask;
514 i365_set(sock, reg, d);
515 }
516
517 static u_short i365_get_pair(u_short sock, u_short reg)
518 {
519 u_short a, b;
520 a = i365_get(sock, reg);
521 b = i365_get(sock, reg+1);
522 return (a + (b<<8));
523 }
524
525 static void i365_set_pair(u_short sock, u_short reg, u_short data)
526 {
527 i365_set(sock, reg, data & 0xff);
528 i365_set(sock, reg+1, data >> 8);
529 }
530
531 /*======================================================================
532
533 Code to save and restore global state information for Cirrus
534 PD67xx controllers, and to set and report global configuration
535 options.
536
537 The VIA controllers also use these routines, as they are mostly
538 Cirrus lookalikes, without the timing registers.
539
540 ======================================================================*/
541
542 #define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
543
544 static void cirrus_get_state(u_short s)
545 {
546 int i;
547 cirrus_state_t *p = &socket[s].state.cirrus;
548 p->misc1 = i365_get(s, PD67_MISC_CTL_1);
549 p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
550 p->misc2 = i365_get(s, PD67_MISC_CTL_2);
551 for (i = 0; i < 6; i++)
552 p->timer[i] = i365_get(s, PD67_TIME_SETUP(0)+i);
553 }
554
555 static void cirrus_set_state(u_short s)
556 {
557 int i;
558 u_char misc;
559 cirrus_state_t *p = &socket[s].state.cirrus;
560
561 misc = i365_get(s, PD67_MISC_CTL_2);
562 i365_set(s, PD67_MISC_CTL_2, p->misc2);
563 if (misc & PD67_MC2_SUSPEND) mdelay(50);
564 misc = i365_get(s, PD67_MISC_CTL_1);
565 misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
566 i365_set(s, PD67_MISC_CTL_1, misc | p->misc1);
567 for (i = 0; i < 6; i++)
568 i365_set(s, PD67_TIME_SETUP(0)+i, p->timer[i]);
569 }
570
571 #ifdef CONFIG_PCI
572 static int cirrus_set_irq_mode(u_short s, int pcsc, int pint)
573 {
574 flip(socket[s].bcr, PD6832_BCR_MGMT_IRQ_ENA, !pcsc);
575 return 0;
576 }
577 #endif /* CONFIG_PCI */
578
579 static u_int cirrus_set_opts(u_short s, char *buf)
580 {
581 socket_info_t *t = &socket[s];
582 cirrus_state_t *p = &socket[s].state.cirrus;
583 u_int mask = 0xffff;
584
585 if (has_ring == -1) has_ring = 1;
586 flip(p->misc2, PD67_MC2_IRQ15_RI, has_ring);
587 flip(p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
588 if (p->misc2 & PD67_MC2_IRQ15_RI)
589 strcat(buf, " [ring]");
590 if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
591 strcat(buf, " [dyn mode]");
592 if (p->misc1 & PD67_MC1_INPACK_ENA)
593 strcat(buf, " [inpack]");
594 if (!(t->flags & (IS_PCI | IS_CARDBUS))) {
595 if (p->misc2 & PD67_MC2_IRQ15_RI)
596 mask &= ~0x8000;
597 if (has_led > 0) {
598 strcat(buf, " [led]");
599 mask &= ~0x1000;
600 }
601 if (has_dma > 0) {
602 strcat(buf, " [dma]");
603 mask &= ~0x0600;
604 flip(p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
605 if (p->misc2 & PD67_MC2_FREQ_BYPASS)
606 strcat(buf, " [freq bypass]");
607 }
608 #ifdef CONFIG_PCI
609 } else {
610 p->misc1 &= ~PD67_MC1_MEDIA_ENA;
611 flip(p->misc2, PD67_MC2_FAST_PCI, fast_pci);
612 if (p->misc2 & PD67_MC2_IRQ15_RI)
613 mask &= (socket[s].type == IS_PD6730) ? ~0x0400 : ~0x8000;
614 #endif
615 }
616 if (!(t->flags & IS_VIA)) {
617 if (setup_time >= 0)
618 p->timer[0] = p->timer[3] = setup_time;
619 if (cmd_time > 0) {
620 p->timer[1] = cmd_time;
621 p->timer[4] = cmd_time*2+4;
622 }
623 if (p->timer[1] == 0) {
624 p->timer[1] = 6; p->timer[4] = 16;
625 if (p->timer[0] == 0)
626 p->timer[0] = p->timer[3] = 1;
627 }
628 if (recov_time >= 0)
629 p->timer[2] = p->timer[5] = recov_time;
630 buf += strlen(buf);
631 sprintf(buf, " [%d/%d/%d] [%d/%d/%d]", p->timer[0], p->timer[1],
632 p->timer[2], p->timer[3], p->timer[4], p->timer[5]);
633 }
634 return mask;
635 }
636
637 /*======================================================================
638
639 Code to save and restore global state information for Vadem VG468
640 and VG469 controllers, and to set and report global configuration
641 options.
642
643 ======================================================================*/
644
645 #ifdef CONFIG_ISA
646
647 static void vg46x_get_state(u_short s)
648 {
649 vg46x_state_t *p = &socket[s].state.vg46x;
650 p->ctl = i365_get(s, VG468_CTL);
651 if (socket[s].type == IS_VG469)
652 p->ema = i365_get(s, VG469_EXT_MODE);
653 }
654
655 static void vg46x_set_state(u_short s)
656 {
657 vg46x_state_t *p = &socket[s].state.vg46x;
658 i365_set(s, VG468_CTL, p->ctl);
659 if (socket[s].type == IS_VG469)
660 i365_set(s, VG469_EXT_MODE, p->ema);
661 }
662
663 static u_int vg46x_set_opts(u_short s, char *buf)
664 {
665 vg46x_state_t *p = &socket[s].state.vg46x;
666
667 flip(p->ctl, VG468_CTL_ASYNC, async_clock);
668 flip(p->ema, VG469_MODE_CABLE, cable_mode);
669 if (p->ctl & VG468_CTL_ASYNC)
670 strcat(buf, " [async]");
671 if (p->ctl & VG468_CTL_INPACK)
672 strcat(buf, " [inpack]");
673 if (socket[s].type == IS_VG469) {
674 u_char vsel = i365_get(s, VG469_VSELECT);
675 if (vsel & VG469_VSEL_EXT_STAT) {
676 strcat(buf, " [ext mode]");
677 if (vsel & VG469_VSEL_EXT_BUS)
678 strcat(buf, " [isa buf]");
679 }
680 if (p->ema & VG469_MODE_CABLE)
681 strcat(buf, " [cable]");
682 if (p->ema & VG469_MODE_COMPAT)
683 strcat(buf, " [c step]");
684 }
685 return 0xffff;
686 }
687
688 #endif
689
690 /*======================================================================
691
692 Code to save and restore global state information for TI 1130 and
693 TI 1131 controllers, and to set and report global configuration
694 options.
695
696 ======================================================================*/
697
698 #ifdef CONFIG_PCI
699
700 static void ti113x_get_state(u_short s)
701 {
702 socket_info_t *t = &socket[s];
703 ti113x_state_t *p = &socket[s].state.ti113x;
704 pci_readl(t->bus, t->devfn, TI113X_SYSTEM_CONTROL, &p->sysctl);
705 pci_readb(t->bus, t->devfn, TI113X_CARD_CONTROL, &p->cardctl);
706 pci_readb(t->bus, t->devfn, TI113X_DEVICE_CONTROL, &p->devctl);
707 pci_readb(t->bus, t->devfn, TI1250_DIAGNOSTIC, &p->diag);
708 }
709
710 static void ti113x_set_state(u_short s)
711 {
712 socket_info_t *t = &socket[s];
713 ti113x_state_t *p = &socket[s].state.ti113x;
714 pci_writel(t->bus, t->devfn, TI113X_SYSTEM_CONTROL, p->sysctl);
715 pci_writeb(t->bus, t->devfn, TI113X_CARD_CONTROL, p->cardctl);
716 pci_writeb(t->bus, t->devfn, TI113X_DEVICE_CONTROL, p->devctl);
717 pci_writeb(t->bus, t->devfn, TI1250_MULTIMEDIA_CTL, 0);
718 pci_writeb(t->bus, t->devfn, TI1250_DIAGNOSTIC, p->diag);
719 i365_set_pair(s, TI113X_IO_OFFSET(0), 0);
720 i365_set_pair(s, TI113X_IO_OFFSET(1), 0);
721 }
722
723 static int ti113x_set_irq_mode(u_short s, int pcsc, int pint)
724 {
725 socket_info_t *t = &socket[s];
726 ti113x_state_t *p = &t->state.ti113x;
727 t->intr = (pcsc) ? I365_INTR_ENA : 0;
728 if (t->type <= IS_TI1131) {
729 p->cardctl &= ~(TI113X_CCR_PCI_IRQ_ENA |
730 TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC);
731 if (pcsc)
732 p->cardctl |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC;
733 if (pint)
734 p->cardctl |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ;
735 } else if (t->type == IS_TI1250A) {
736 p->diag &= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ;
737 if (pcsc)
738 p->diag |= TI1250_DIAG_PCI_CSC;
739 if (pint)
740 p->diag |= TI1250_DIAG_PCI_IREQ;
741 }
742 return 0;
743 }
744
745 static u_int ti113x_set_opts(u_short s, char *buf)
746 {
747 socket_info_t *t = &socket[s];
748 ti113x_state_t *p = &t->state.ti113x;
749 u_int mask = 0xffff;
750 int old = (t->type <= IS_TI1131);
751
752 flip(p->sysctl, TI113X_SCR_CLKRUN_ENA, has_clkrun);
753 flip(p->sysctl, TI113X_SCR_CLKRUN_SEL, clkrun_sel);
754 flip(p->cardctl, TI113X_CCR_RIENB, has_ring);
755 p->cardctl &= ~TI113X_CCR_ZVENABLE;
756 switch (irq_mode) {
757 case 1:
758 p->devctl &= ~TI113X_DCR_IMODE_MASK;
759 p->devctl |= TI113X_DCR_IMODE_ISA;
760 break;
761 case 2:
762 p->devctl &= ~TI113X_DCR_IMODE_MASK;
763 p->devctl |= TI113X_DCR_IMODE_SERIAL;
764 break;
765 case 3:
766 p->devctl &= ~TI113X_DCR_IMODE_MASK;
767 p->devctl |= TI12XX_DCR_IMODE_ALL_SERIAL;
768 break;
769 default:
770 if ((p->devctl & TI113X_DCR_IMODE_MASK) == 0)
771 p->devctl |= TI113X_DCR_IMODE_ISA;
772 }
773 if (p->cardctl & TI113X_CCR_RIENB) {
774 strcat(buf, " [ring]");
775 if (old) mask &= ~0x8000;
776 }
777 if (old && (p->sysctl & TI113X_SCR_CLKRUN_ENA)) {
778 if (p->sysctl & TI113X_SCR_CLKRUN_SEL) {
779 strcat(buf, " [clkrun irq 12]");
780 mask &= ~0x1000;
781 } else {
782 strcat(buf, " [clkrun irq 10]");
783 mask &= ~0x0400;
784 }
785 }
786 if (p->sysctl & TI113X_SCR_PWRSAVINGS)
787 strcat(buf, " [pwr save]");
788 switch (p->devctl & TI113X_DCR_IMODE_MASK) {
789 case TI12XX_DCR_IMODE_PCI_ONLY:
790 strcat(buf, " [pci only]");
791 mask = 0;
792 break;
793 case TI113X_DCR_IMODE_ISA:
794 strcat(buf, " [isa irq]");
795 if (old) mask &= ~0x0018;
796 break;
797 case TI113X_DCR_IMODE_SERIAL:
798 strcat(buf, " [pci + serial irq]");
799 mask = 0xffff;
800 break;
801 case TI12XX_DCR_IMODE_ALL_SERIAL:
802 strcat(buf, " [serial pci & irq]");
803 mask = 0xffff;
804 break;
805 }
806 return mask;
807 }
808
809 #endif
810
811 /*======================================================================
812
813 Code to save and restore global state information for the Ricoh
814 RL5C4XX controllers, and to set and report global configuration
815 options.
816
817 ======================================================================*/
818
819 #ifdef CONFIG_PCI
820
821 static void rl5c4xx_get_state(u_short s)
822 {
823 socket_info_t *t = &socket[s];
824 rl5c4xx_state_t *p = &socket[s].state.rl5c4xx;
825 pci_readw(t->bus, t->devfn, RL5C4XX_MISC, &p->misc);
826 pci_readw(t->bus, t->devfn, RL5C4XX_16BIT_CTL, &p->ctl);
827 pci_readw(t->bus, t->devfn, RL5C4XX_16BIT_IO_0, &p->io);
828 pci_readw(t->bus, t->devfn, RL5C4XX_16BIT_MEM_0, &p->mem);
829 }
830
831 static void rl5c4xx_set_state(u_short s)
832 {
833 socket_info_t *t = &socket[s];
834 rl5c4xx_state_t *p = &socket[s].state.rl5c4xx;
835 pci_writew(t->bus, t->devfn, RL5C4XX_MISC, p->misc);
836 pci_writew(t->bus, t->devfn, RL5C4XX_16BIT_CTL, p->ctl);
837 pci_writew(t->bus, t->devfn, RL5C4XX_16BIT_IO_0, p->io);
838 pci_writew(t->bus, t->devfn, RL5C4XX_16BIT_MEM_0, p->mem);
839 }
840
841 static u_int rl5c4xx_set_opts(u_short s, char *buf)
842 {
843 rl5c4xx_state_t *p = &socket[s].state.rl5c4xx;
844 u_int mask = 0xffff;
845 int old = (socket[s].type < IS_RL5C475);
846
847 p->ctl = RL5C4XX_16CTL_IO_TIMING | RL5C4XX_16CTL_MEM_TIMING;
848 if (old) p->ctl |= RL5C46X_16CTL_LEVEL_1 | RL5C46X_16CTL_LEVEL_2;
849
850 if (setup_time >= 0) {
851 p->io = (p->io & ~RL5C4XX_SETUP_MASK) +
852 ((setup_time+1) << RL5C4XX_SETUP_SHIFT);
853 p->mem = (p->mem & ~RL5C4XX_SETUP_MASK) +
854 (setup_time << RL5C4XX_SETUP_SHIFT);
855 }
856 if (cmd_time >= 0) {
857 p->io = (p->io & ~RL5C4XX_CMD_MASK) +
858 (cmd_time << RL5C4XX_CMD_SHIFT);
859 p->mem = (p->mem & ~RL5C4XX_CMD_MASK) +
860 (cmd_time << RL5C4XX_CMD_SHIFT);
861 }
862 if (hold_time >= 0) {
863 p->io = (p->io & ~RL5C4XX_HOLD_MASK) +
864 (hold_time << RL5C4XX_HOLD_SHIFT);
865 p->mem = (p->mem & ~RL5C4XX_HOLD_MASK) +
866 (hold_time << RL5C4XX_HOLD_SHIFT);
867 }
868 if (!old) {
869 switch (irq_mode) {
870 case 1:
871 p->misc &= ~RL5C47X_MISC_SRIRQ_ENA; break;
872 case 2:
873 p->misc |= RL5C47X_MISC_SRIRQ_ENA; break;
874 }
875 if (p->misc & RL5C47X_MISC_SRIRQ_ENA)
876 sprintf(buf, " [serial irq]");
877 else
878 sprintf(buf, " [isa irq]");
879 buf += strlen(buf);
880 }
881 sprintf(buf, " [io %d/%d/%d] [mem %d/%d/%d]",
882 (p->io & RL5C4XX_SETUP_MASK) >> RL5C4XX_SETUP_SHIFT,
883 (p->io & RL5C4XX_CMD_MASK) >> RL5C4XX_CMD_SHIFT,
884 (p->io & RL5C4XX_HOLD_MASK) >> RL5C4XX_HOLD_SHIFT,
885 (p->mem & RL5C4XX_SETUP_MASK) >> RL5C4XX_SETUP_SHIFT,
886 (p->mem & RL5C4XX_CMD_MASK) >> RL5C4XX_CMD_SHIFT,
887 (p->mem & RL5C4XX_HOLD_MASK) >> RL5C4XX_HOLD_SHIFT);
888 return mask;
889 }
890
891 #endif
892
893 /*======================================================================
894
895 Code to save and restore global state information for O2Micro
896 controllers, and to set and report global configuration options.
897
898 ======================================================================*/
899
900 #ifdef CONFIG_PCI
901
902 static void o2micro_get_state(u_short s)
903 {
904 socket_info_t *t = &socket[s];
905 o2micro_state_t *p = &socket[s].state.o2micro;
906 if ((t->revision == 0x34) || (t->revision == 0x62)) {
907 p->mode_a = i365_get(s, O2_MODE_A_2);
908 p->mode_b = i365_get(s, O2_MODE_B_2);
909 } else {
910 p->mode_a = i365_get(s, O2_MODE_A);
911 p->mode_b = i365_get(s, O2_MODE_B);
912 }
913 p->mode_c = i365_get(s, O2_MODE_C);
914 p->mode_d = i365_get(s, O2_MODE_D);
915 if (t->flags & IS_CARDBUS) {
916 p->mhpg = i365_get(s, O2_MHPG_DMA);
917 p->fifo = i365_get(s, O2_FIFO_ENA);
918 p->mode_e = i365_get(s, O2_MODE_E);
919 }
920 }
921
922 static void o2micro_set_state(u_short s)
923 {
924 socket_info_t *t = &socket[s];
925 o2micro_state_t *p = &socket[s].state.o2micro;
926 if ((t->revision == 0x34) || (t->revision == 0x62)) {
927 i365_set(s, O2_MODE_A_2, p->mode_a);
928 i365_set(s, O2_MODE_B_2, p->mode_b);
929 } else {
930 i365_set(s, O2_MODE_A, p->mode_a);
931 i365_set(s, O2_MODE_B, p->mode_b);
932 }
933 i365_set(s, O2_MODE_C, p->mode_c);
934 i365_set(s, O2_MODE_D, p->mode_d);
935 if (t->flags & IS_CARDBUS) {
936 i365_set(s, O2_MHPG_DMA, p->mhpg);
937 i365_set(s, O2_FIFO_ENA, p->fifo);
938 i365_set(s, O2_MODE_E, p->mode_e);
939 }
940 }
941
942 static u_int o2micro_set_opts(u_short s, char *buf)
943 {
944 socket_info_t *t = &socket[s];
945 o2micro_state_t *p = &socket[s].state.o2micro;
946 u_int mask = 0xffff;
947
948 p->mode_b = (p->mode_b & ~O2_MODE_B_IDENT) | O2_MODE_B_ID_CSTEP;
949 flip(p->mode_b, O2_MODE_B_IRQ15_RI, has_ring);
950 p->mode_c &= ~(O2_MODE_C_ZVIDEO | O2_MODE_C_DREQ_MASK);
951 if (t->flags & IS_CARDBUS) {
952 p->mode_d &= ~O2_MODE_D_W97_IRQ;
953 p->mode_e &= ~O2_MODE_E_MHPG_DMA;
954 p->mhpg |= O2_MHPG_CINT_ENA | O2_MHPG_CSC_ENA;
955 p->mhpg &= ~O2_MHPG_CHANNEL;
956 } else {
957 if (p->mode_b & O2_MODE_B_IRQ15_RI) mask &= ~0x8000;
958 }
959 sprintf(buf, " [a %02x] [b %02x] [c %02x] [d %02x]",
960 p->mode_a, p->mode_b, p->mode_c, p->mode_d);
961 if (t->flags & IS_CARDBUS) {
962 buf += strlen(buf);
963 sprintf(buf, " [mhpg %02x] [fifo %02x] [e %02x]",
964 p->mhpg, p->fifo, p->mode_e);
965 }
966 return mask;
967 }
968
969 #endif
970
971 /*======================================================================
972
973 Code to save and restore global state information for the Toshiba
974 ToPIC 95 and 97 controllers, and to set and report global
975 configuration options.
976
977 ======================================================================*/
978
979 #ifdef CONFIG_PCI
980
981 static void topic_get_state(u_short s)
982 {
983 socket_info_t *t = &socket[s];
984 topic_state_t *p = &socket[s].state.topic;
985 pci_readb(t->bus, t->devfn, TOPIC_SLOT_CONTROL, &p->slot);
986 pci_readb(t->bus, t->devfn, TOPIC_CARD_CONTROL, &p->ccr);
987 pci_readb(t->bus, t->devfn, TOPIC_CARD_DETECT, &p->cdr);
988 pci_readl(t->bus, t->devfn, TOPIC_REGISTER_CONTROL, &p->rcr);
989 }
990
991 static void topic_set_state(u_short s)
992 {
993 socket_info_t *t = &socket[s];
994 topic_state_t *p = &socket[s].state.topic;
995 pci_writeb(t->bus, t->devfn, TOPIC_SLOT_CONTROL, p->slot);
996 pci_writeb(t->bus, t->devfn, TOPIC_CARD_CONTROL, p->ccr);
997 pci_writeb(t->bus, t->devfn, TOPIC_CARD_DETECT, p->cdr);
998 pci_writel(t->bus, t->devfn, TOPIC_REGISTER_CONTROL, p->rcr);
999 }
1000
1001 static int topic_set_irq_mode(u_short s, int pcsc, int pint)
1002 {
1003 if (socket[s].type == IS_TOPIC97) {
1004 topic_state_t *p = &socket[s].state.topic;
1005 flip(p->ccr, TOPIC97_ICR_IRQSEL, pcsc);
1006 return 0;
1007 } else {
1008 return !pcsc;
1009 }
1010 }
1011
1012 static u_int topic_set_opts(u_short s, char *buf)
1013 {
1014 topic_state_t *p = &socket[s].state.topic;
1015
1016 p->slot |= TOPIC_SLOT_SLOTON|TOPIC_SLOT_SLOTEN|TOPIC_SLOT_ID_LOCK;
1017 p->cdr |= TOPIC_CDR_MODE_PC32;
1018 p->cdr &= ~(TOPIC_CDR_SW_DETECT);
1019 sprintf(buf, " [slot 0x%02x] [ccr 0x%02x] [cdr 0x%02x] [rcr 0x%02x]",
1020 p->slot, p->ccr, p->cdr, p->rcr);
1021 return 0xffff;
1022 }
1023
1024 #endif
1025
1026 /*======================================================================
1027
1028 Routines to handle common CardBus options
1029
1030 ======================================================================*/
1031
1032 #ifdef CONFIG_PCI
1033
1034 static void cb_get_state(u_short s)
1035 {
1036 socket_info_t *t = &socket[s];
1037 struct pci_dev *dev = pci_find_slot(t->bus, t->devfn);
1038
1039 if (!dev)
1040 return;
1041 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &t->cache);
1042 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &t->pci_lat);
1043 pci_read_config_byte(dev, CB_LATENCY_TIMER, &t->cb_lat);
1044 pci_read_config_byte(dev, CB_CARDBUS_BUS, &t->cap.cardbus);
1045 pci_read_config_byte(dev, CB_SUBORD_BUS, &t->sub_bus);
1046 pci_read_config_word(dev, CB_BRIDGE_CONTROL, &t->bcr);
1047
1048 t->cap.pci_irq = dev->irq;
1049 if (t->cap.pci_irq >= NR_IRQS) t->cap.pci_irq = 0;
1050 }
1051
1052 static void cb_set_state(u_short s)
1053 {
1054 socket_info_t *t = &socket[s];
1055 struct pci_dev *dev = pci_find_slot(t->bus, t->devfn);
1056
1057 if (t->pmcs)
1058 pci_write_config_word(dev, t->pmcs, PCI_PMCS_PWR_STATE_D0);
1059
1060 pci_write_config_dword(dev, CB_LEGACY_MODE_BASE, 0);
1061 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, t->cb_phys);
1062 pci_write_config_word(dev, PCI_COMMAND, CMD_DFLT);
1063 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, t->cache);
1064 pci_write_config_byte(dev, PCI_LATENCY_TIMER, t->pci_lat);
1065 pci_write_config_byte(dev, CB_LATENCY_TIMER, t->cb_lat);
1066 pci_write_config_byte(dev, CB_CARDBUS_BUS, t->cap.cardbus);
1067 pci_write_config_byte(dev, CB_SUBORD_BUS, t->sub_bus);
1068 pci_write_config_word(dev, CB_BRIDGE_CONTROL, t->bcr);
1069 }
1070
1071 static int cb_get_irq_mode(u_short s)
1072 {
1073 return (!(socket[s].bcr & CB_BCR_ISA_IRQ));
1074 }
1075
1076 static int cb_set_irq_mode(u_short s, int pcsc, int pint)
1077 {
1078 socket_info_t *t = &socket[s];
1079 flip(t->bcr, CB_BCR_ISA_IRQ, !(pint));
1080 if (t->flags & IS_CIRRUS)
1081 return cirrus_set_irq_mode(s, pcsc, pint);
1082 else if (t->flags & IS_TI)
1083 return ti113x_set_irq_mode(s, pcsc, pint);
1084 else if (t->flags & IS_TOPIC)
1085 return topic_set_irq_mode(s, pcsc, pint);
1086 return 0;
1087 }
1088
1089 static void pci_scan(u_short sock);
1090
1091 static void cb_set_opts(u_short s, char *buf)
1092 {
1093 socket_info_t *t = &socket[s];
1094 t->bcr |= CB_BCR_WRITE_POST;
1095 /* some TI1130's seem to exhibit problems with write posting */
1096 if (((t->type == IS_TI1130) && (t->revision == 4) &&
1097 (cb_write_post < 0)) || (cb_write_post == 0))
1098 t->bcr &= ~CB_BCR_WRITE_POST;
1099 if (t->cache == 0) t->cache = 8;
1100 if (pci_latency >= 0) t->pci_lat = pci_latency;
1101 if (t->pci_lat == 0) t->pci_lat = 0xa8;
1102 if (cb_latency >= 0) t->cb_lat = cb_latency;
1103 if (t->cb_lat == 0) t->cb_lat = 0xb0;
1104 if ((t->cap.pci_irq == 0) && (pci_csc || pci_int) && do_scan)
1105 pci_scan(s);
1106 if (t->cap.pci_irq == 0)
1107 strcat(buf, " [no pci irq]");
1108 else
1109 sprintf(buf, " [pci irq %d]", t->cap.pci_irq);
1110 buf += strlen(buf);
1111 if ((cb_bus_base > 0) || (t->cap.cardbus == 0)) {
1112 if (cb_bus_base <= 0) cb_bus_base = 0x20;
1113 t->cap.cardbus = cb_bus_base;
1114 t->sub_bus = cb_bus_base+cb_bus_step;
1115 cb_bus_base += cb_bus_step+1;
1116 }
1117 if (!(t->flags & IS_TOPIC))
1118 t->cap.features |= SS_CAP_PAGE_REGS;
1119 sprintf(buf, " [lat %d/%d] [bus %d/%d]",
1120 t->pci_lat, t->cb_lat, t->cap.cardbus, t->sub_bus);
1121 }
1122
1123 #endif
1124
1125 /*======================================================================
1126
1127 Generic routines to get and set controller options
1128
1129 ======================================================================*/
1130
1131 static void get_host_state(u_short s)
1132 {
1133 socket_info_t *t = &socket[s];
1134 if (t->flags & IS_CIRRUS)
1135 cirrus_get_state(s);
1136 #ifdef CONFIG_ISA
1137 else if (t->flags & IS_VADEM)
1138 vg46x_get_state(s);
1139 #endif
1140 #ifdef CONFIG_PCI
1141 else if (t->flags & IS_O2MICRO)
1142 o2micro_get_state(s);
1143 else if (t->flags & IS_TI)
1144 ti113x_get_state(s);
1145 else if (t->flags & IS_RICOH)
1146 rl5c4xx_get_state(s);
1147 else if (t->flags & IS_TOPIC)
1148 topic_get_state(s);
1149 if (t->flags & IS_CARDBUS)
1150 cb_get_state(s);
1151 #endif
1152 }
1153
1154 static void set_host_state(u_short s)
1155 {
1156 socket_info_t *t = &socket[s];
1157 #ifdef CONFIG_PCI
1158 if (t->flags & IS_CARDBUS)
1159 cb_set_state(s);
1160 #endif
1161 if (t->flags & IS_CIRRUS)
1162 cirrus_set_state(s);
1163 else {
1164 i365_set(s, I365_GBLCTL, 0x00);
1165 i365_set(s, I365_GENCTL, 0x00);
1166 }
1167 i365_bflip(s, I365_INTCTL, I365_INTR_ENA, t->intr);
1168 #ifdef CONFIG_ISA
1169 if (t->flags & IS_VADEM)
1170 vg46x_set_state(s);
1171 #endif
1172 #ifdef CONFIG_PCI
1173 if (t->flags & IS_O2MICRO)
1174 o2micro_set_state(s);
1175 else if (t->flags & IS_TI)
1176 ti113x_set_state(s);
1177 else if (t->flags & IS_RICOH)
1178 rl5c4xx_set_state(s);
1179 else if (t->flags & IS_TOPIC)
1180 topic_set_state(s);
1181 #endif
1182 }
1183
1184 static u_int set_host_opts(u_short s, u_short ns)
1185 {
1186 u_short i;
1187 u_int m = 0xffff;
1188 char buf[128];
1189
1190 for (i = s; i < s+ns; i++) {
1191 if (socket[i].flags & IS_ALIVE) {
1192 printk(KERN_INFO " host opts [%d]: already alive!\n", i);
1193 continue;
1194 }
1195 buf[0] = '\0';
1196 get_host_state(i);
1197 if (socket[i].flags & IS_CIRRUS)
1198 m = cirrus_set_opts(i, buf);
1199 #ifdef CONFIG_ISA
1200 else if (socket[i].flags & IS_VADEM)
1201 m = vg46x_set_opts(i, buf);
1202 #endif
1203 #ifdef CONFIG_PCI
1204 else if (socket[i].flags & IS_O2MICRO)
1205 m = o2micro_set_opts(i, buf);
1206 else if (socket[i].flags & IS_TI)
1207 m = ti113x_set_opts(i, buf);
1208 else if (socket[i].flags & IS_RICOH)
1209 m = rl5c4xx_set_opts(i, buf);
1210 else if (socket[i].flags & IS_TOPIC)
1211 m = topic_set_opts(i, buf);
1212 if (socket[i].flags & IS_CARDBUS)
1213 cb_set_opts(i, buf+strlen(buf));
1214 #endif
1215 set_host_state(i);
1216 printk(KERN_INFO " host opts [%d]:%s\n", i,
1217 (*buf) ? buf : " none");
1218 }
1219 #ifdef CONFIG_PCI
1220 /* Mask out all PCI interrupts */
1221 for (i = 0; i < sockets; i++)
1222 m &= ~(1<<socket[i].cap.pci_irq);
1223 {
1224 struct pci_dev *p;
1225 for (p = pci_devices; p; p = p->next)
1226 m &= ~(1<<p->irq);
1227 }
1228 #endif
1229 return m;
1230 }
1231
1232 /*======================================================================
1233
1234 Interrupt testing code, for ISA and PCI interrupts
1235
1236 ======================================================================*/
1237
1238 static volatile u_int irq_hits;
1239 static u_short irq_sock;
1240
1241 static void irq_count(int irq, void *dev, struct pt_regs *regs)
1242 {
1243 #ifdef CONFIG_PCI
1244 if (socket[irq_sock].flags & IS_CARDBUS) {
1245 cb_writel(irq_sock, CB_SOCKET_EVENT, -1);
1246 } else
1247 #endif
1248 i365_get(irq_sock, I365_CSC);
1249 irq_hits++;
1250 DEBUG(2, ("-> hit on irq %d\n", irq));
1251 }
1252
1253 static u_int test_irq(u_short sock, int irq, int pci)
1254 {
1255 u_char csc = (pci) ? 0 : irq;
1256 DEBUG(2, " testing %s irq %d\n", pci ? "PCI" : "ISA", irq);
1257
1258 if (request_irq(irq, irq_count, (pci?SA_SHIRQ:0), "scan", NULL) != 0)
1259 return 1;
1260 irq_hits = 0; irq_sock = sock;
1261 current->state = TASK_INTERRUPTIBLE;
1262 schedule_timeout(HZ/100);
1263 if (irq_hits) {
1264 free_irq(irq, NULL);
1265 DEBUG(2, (" spurious hit!\n"));
1266 return 1;
1267 }
1268
1269 /* Generate one interrupt */
1270 #ifdef CONFIG_PCI
1271 if (socket[sock].flags & IS_CARDBUS) {
1272 cb_writel(sock, CB_SOCKET_EVENT, -1);
1273 i365_set(sock, I365_CSCINT, I365_CSC_STSCHG | (csc << 4));
1274 cb_writel(sock, CB_SOCKET_EVENT, -1);
1275 cb_writel(sock, CB_SOCKET_MASK, CB_SM_CSTSCHG);
1276 cb_writel(sock, CB_SOCKET_FORCE, CB_SE_CSTSCHG);
1277 udelay(1000);
1278 cb_writel(sock, CB_SOCKET_EVENT, -1);
1279 cb_writel(sock, CB_SOCKET_MASK, 0);
1280 } else
1281 #endif
1282 {
1283 i365_set(sock, I365_CSCINT, I365_CSC_DETECT | (csc << 4));
1284 i365_bset(sock, I365_GENCTL, I365_CTL_SW_IRQ);
1285 udelay(1000);
1286 }
1287
1288 free_irq(irq, NULL);
1289
1290 /* mask all interrupts */
1291 i365_set(sock, I365_CSCINT, 0);
1292 DEBUG(2, " hits = %d\n", irq_hits);
1293
1294 return (irq_hits != 1);
1295 }
1296
1297 #ifdef CONFIG_ISA
1298
1299 static u_int isa_scan(u_short sock, u_int mask0)
1300 {
1301 u_int mask1 = 0;
1302 int i;
1303
1304 #ifdef __alpha__
1305 #define PIC 0x4d0
1306 /* Don't probe level-triggered interrupts -- reserved for PCI */
1307 mask0 &= ~(inb(PIC) | (inb(PIC+1) << 8));
1308 #endif
1309
1310 #ifdef CONFIG_PCI
1311 /* Only scan if we can select ISA csc irq's */
1312 if (!(socket[sock].flags & IS_CARDBUS) ||
1313 (cb_set_irq_mode(sock, 0, 0) == 0))
1314 #endif
1315 if (do_scan) {
1316 set_host_state(sock);
1317 i365_set(sock, I365_CSCINT, 0);
1318 for (i = 0; i < 16; i++)
1319 if ((mask0 & (1 << i)) && (test_irq(sock, i, 0) == 0))
1320 mask1 |= (1 << i);
1321 for (i = 0; i < 16; i++)
1322 if ((mask1 & (1 << i)) && (test_irq(sock, i, 0) != 0))
1323 mask1 ^= (1 << i);
1324 }
1325
1326 printk(KERN_INFO " ISA irqs (");
1327 if (mask1) {
1328 printk("scanned");
1329 } else {
1330 /* Fallback: just find interrupts that aren't in use */
1331 for (i = 0; i < 16; i++)
1332 if ((mask0 & (1 << i)) && (_check_irq(i, 0) == 0))
1333 mask1 |= (1 << i);
1334 printk("default");
1335 /* If scan failed, default to polled status */
1336 if (!cs_irq && (poll_interval == 0)) poll_interval = HZ;
1337 }
1338 printk(") = ");
1339
1340 for (i = 0; i < 16; i++)
1341 if (mask1 & (1<<i))
1342 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i);
1343 if (mask1 == 0) printk("none!");
1344
1345 return mask1;
1346 }
1347
1348 #endif /* CONFIG_ISA */
1349
1350 #ifdef CONFIG_PCI
1351
1352 static void pci_scan(u_short sock)
1353 {
1354 u_int i;
1355
1356 cb_set_irq_mode(sock, 1, 0);
1357 set_host_state(sock);
1358 i365_set(sock, I365_CSCINT, 0);
1359 /* Only probe irq's 9..11, to be conservative */
1360 for (i = 9; i < 12; i++) {
1361 if ((test_irq(sock, i, 1) == 0) &&
1362 (test_irq(sock, i, 1) == 0))
1363 break;
1364 }
1365 if (i < 12) socket[sock].cap.pci_irq = i;
1366 }
1367
1368 #endif /* CONFIG_PCI */
1369
1370 /*====================================================================*/
1371
1372 /* Time conversion functions */
1373
1374 static int to_cycles(int ns)
1375 {
1376 return ns/cycle_time;
1377 } /* speed_convert */
1378
1379 static int to_ns(int cycles)
1380 {
1381 return cycle_time*cycles;
1382 }
1383
1384 /*====================================================================*/
1385
1386 #ifdef CONFIG_ISA
1387
1388 static int identify(u_short port, u_short sock)
1389 {
1390 u_char val;
1391 int type = -1;
1392
1393 /* Use the next free entry in the socket table */
1394 socket[sockets].ioaddr = port;
1395 socket[sockets].psock = sock;
1396
1397 /* Wake up a sleepy Cirrus controller */
1398 if (wakeup) {
1399 i365_bclr(sockets, PD67_MISC_CTL_2, PD67_MC2_SUSPEND);
1400 /* Pause at least 50 ms */
1401 mdelay(50);
1402 }
1403
1404 if ((val = i365_get(sockets, I365_IDENT)) & 0x70)
1405 return -1;
1406 switch (val) {
1407 case 0x82:
1408 type = IS_I82365A; break;
1409 case 0x83:
1410 type = IS_I82365B; break;
1411 case 0x84:
1412 type = IS_I82365DF; break;
1413 case 0x88: case 0x89: case 0x8a:
1414 type = IS_IBM; break;
1415 }
1416
1417 /* Check for Vadem VG-468 chips */
1418 outb(0x0e, port);
1419 outb(0x37, port);
1420 i365_bset(sockets, VG468_MISC, VG468_MISC_VADEMREV);
1421 val = i365_get(sockets, I365_IDENT);
1422 if (val & I365_IDENT_VADEM) {
1423 i365_bclr(sockets, VG468_MISC, VG468_MISC_VADEMREV);
1424 type = ((val & 7) >= 4) ? IS_VG469 : IS_VG468;
1425 }
1426
1427 /* Check for Ricoh chips */
1428 val = i365_get(sockets, RF5C_CHIP_ID);
1429 if ((val == RF5C_CHIP_RF5C296) || (val == RF5C_CHIP_RF5C396))
1430 type = IS_RF5Cx96;
1431
1432 /* Check for Cirrus CL-PD67xx chips */
1433 i365_set(sockets, PD67_CHIP_INFO, 0);
1434 val = i365_get(sockets, PD67_CHIP_INFO);
1435 if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
1436 val = i365_get(sockets, PD67_CHIP_INFO);
1437 if ((val & PD67_INFO_CHIP_ID) == 0) {
1438 type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
1439 i365_set(sockets, PD67_EXT_INDEX, 0xe5);
1440 if (i365_get(sockets, PD67_EXT_INDEX) != 0xe5)
1441 type = IS_VT83C469;
1442 }
1443 }
1444 return type;
1445 } /* identify */
1446
1447 #endif
1448
1449 /*======================================================================
1450
1451 See if a card is present, powered up, in IO mode, and already
1452 bound to a (non PC Card) Linux driver. We leave these alone.
1453
1454 We make an exception for cards that seem to be serial devices.
1455
1456 ======================================================================*/
1457
1458 static int is_alive(u_short sock)
1459 {
1460 u_char stat;
1461 u_short start, stop;
1462
1463 stat = i365_get(sock, I365_STATUS);
1464 start = i365_get_pair(sock, I365_IO(0)+I365_W_START);
1465 stop = i365_get_pair(sock, I365_IO(0)+I365_W_STOP);
1466 if ((stat & I365_CS_DETECT) && (stat & I365_CS_POWERON) &&
1467 (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD) &&
1468 (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(0)) &&
1469 (check_region(start, stop-start+1) != 0) &&
1470 ((start & 0xfeef) != 0x02e8))
1471 return 1;
1472 else
1473 return 0;
1474 }
1475
1476 /*====================================================================*/
1477
1478 static void add_socket(u_short port, int psock, int type)
1479 {
1480 socket[sockets].ioaddr = port;
1481 socket[sockets].psock = psock;
1482 socket[sockets].type = type;
1483 socket[sockets].flags = pcic[type].flags;
1484 if (is_alive(sockets))
1485 socket[sockets].flags |= IS_ALIVE;
1486 sockets++;
1487 }
1488
1489 static void add_pcic(int ns, int type)
1490 {
1491 u_int mask = 0, i, base;
1492 int use_pci = 0, isa_irq = 0;
1493 socket_info_t *t = &socket[sockets-ns];
1494
1495 base = sockets-ns;
1496 if (t->ioaddr > 0) request_region(t->ioaddr, 2, "i82365");
1497
1498 if (base == 0) printk("\n");
1499 printk(KERN_INFO " %s", pcic[type].name);
1500 #ifdef CONFIG_PCI
1501 if (t->flags & IS_UNKNOWN)
1502 printk(" [0x%04x 0x%04x]", t->vendor, t->device);
1503 if (t->flags & IS_CARDBUS)
1504 printk(" PCI-to-CardBus at bus %d slot %d, mem 0x%08x",
1505 t->bus, PCI_SLOT(t->devfn), t->cb_phys);
1506 else if (t->flags & IS_PCI)
1507 printk(" PCI-to-PCMCIA at bus %d slot %d, port %#x",
1508 t->bus, PCI_SLOT(t->devfn), t->ioaddr);
1509 else
1510 #endif
1511 printk(" ISA-to-PCMCIA at port %#x ofs 0x%02x",
1512 t->ioaddr, t->psock*0x40);
1513 printk(", %d socket%s\n", ns, ((ns > 1) ? "s" : ""));
1514
1515 #ifdef CONFIG_ISA
1516 /* Set host options, build basic interrupt mask */
1517 if (irq_list[0] == -1)
1518 mask = irq_mask;
1519 else
1520 for (i = mask = 0; i < 16; i++)
1521 mask |= (1<<irq_list[i]);
1522 #endif
1523 mask &= I365_MASK & set_host_opts(base, ns);
1524 #ifdef CONFIG_ISA
1525 /* Scan for ISA interrupts */
1526 mask = isa_scan(base, mask);
1527 #else
1528 printk(KERN_INFO " PCI card interrupts,");
1529 #endif
1530
1531 #ifdef CONFIG_PCI
1532 /* Can we use a PCI interrupt for card status changes? */
1533 if (pci_csc && t->cap.pci_irq) {
1534 for (i = 0; i < ns; i++)
1535 if (_check_irq(t[i].cap.pci_irq, SA_SHIRQ)) break;
1536 if (i == ns) {
1537 use_pci = 1;
1538 printk(" PCI status changes\n");
1539 }
1540 }
1541 #endif
1542
1543 #ifdef CONFIG_ISA
1544 /* Poll if only two interrupts available */
1545 if (!use_pci && !poll_interval) {
1546 u_int tmp = (mask & (mask-1));
1547 if ((tmp & (tmp-1)) == 0)
1548 poll_interval = HZ;
1549 }
1550 /* Only try an ISA cs_irq if this is the first controller */
1551 if (!use_pci && !grab_irq && (cs_irq || !poll_interval)) {
1552 /* Avoid irq 12 unless it is explicitly requested */
1553 u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12));
1554 for (cs_irq = 15; cs_irq > 0; cs_irq--)
1555 if ((cs_mask & (1 << cs_irq)) &&
1556 (_check_irq(cs_irq, 0) == 0))
1557 break;
1558 if (cs_irq) {
1559 grab_irq = 1;
1560 isa_irq = cs_irq;
1561 printk(" status change on irq %d\n", cs_irq);
1562 }
1563 }
1564 #endif
1565
1566 if (!use_pci && !isa_irq) {
1567 if (poll_interval == 0)
1568 poll_interval = HZ;
1569 printk(" polling interval = %d ms\n",
1570 poll_interval * 1000 / HZ);
1571
1572 }
1573
1574 /* Update socket interrupt information, capabilities */
1575 for (i = 0; i < ns; i++) {
1576 t[i].cap.features |= SS_CAP_PCCARD;
1577 t[i].cap.map_size = 0x1000;
1578 t[i].cap.irq_mask = mask;
1579 if (pci_int && t[i].cap.pci_irq)
1580 t[i].cap.irq_mask |= (1 << t[i].cap.pci_irq);
1581 t[i].cs_irq = isa_irq;
1582 #ifdef CONFIG_PCI
1583 if (t[i].flags & IS_CARDBUS) {
1584 t[i].cap.features |= SS_CAP_CARDBUS;
1585 cb_set_irq_mode(i, pci_csc && t[i].cap.pci_irq,
1586 pci_int && t[i].cap.pci_irq);
1587 }
1588 #endif
1589 }
1590
1591 } /* add_pcic */
1592
1593 /*====================================================================*/
1594
1595 #ifdef CONFIG_PCI
1596
1597 typedef struct pci_dev *pci_id_t;
1598 static int pci_lookup(u_int class, pci_id_t *id,
1599 u_char *bus, u_char *devfn)
1600 {
1601 if ((*id = pci_find_class(class<<8, *id)) != NULL) {
1602 *bus = (*id)->bus->number;
1603 *devfn = (*id)->devfn;
1604 return 0;
1605 } else return -1;
1606 }
1607
1608 static void add_pci_bridge(int type, u_char bus, u_char devfn,
1609 u_short v, u_short d)
1610 {
1611 socket_info_t *s = &socket[sockets];
1612 u_short i, ns;
1613 u_int addr;
1614
1615 if (type == PCIC_COUNT) type = IS_UNK_PCI;
1616 pci_readl(bus, devfn, PCI_BASE_ADDRESS_0, &addr);
1617 addr &= ~0x1;
1618 pci_writew(bus, devfn, PCI_COMMAND, CMD_DFLT);
1619 for (i = ns = 0; i < ((type == IS_I82092AA) ? 4 : 2); i++) {
1620 s->bus = bus; s->devfn = devfn;
1621 s->vendor = v; s->device = d;
1622 add_socket(addr, i, type);
1623 ns++; s++;
1624 }
1625 add_pcic(ns, type);
1626 }
1627
1628 static void add_cb_bridge(int type, u_char bus, u_char devfn,
1629 u_short v, u_short d0)
1630 {
1631 socket_info_t *s = &socket[sockets];
1632 u_short d, ns;
1633 u_char a, b, r, max;
1634
1635 /* PCI bus enumeration is broken on some systems */
1636 for (ns = 0; ns < sockets; ns++)
1637 if ((socket[ns].bus == bus) && (socket[ns].devfn == devfn))
1638 return;
1639
1640 if (type == PCIC_COUNT) type = IS_UNK_CARDBUS;
1641 pci_readb(bus, devfn, PCI_HEADER_TYPE, &a);
1642 pci_readb(bus, devfn, PCI_CLASS_REVISION, &r);
1643 max = (a & 0x80) ? 8 : 1;
1644 for (ns = 0; ns < max; ns++, s++, devfn++) {
1645 if (pci_readw(bus, devfn, PCI_DEVICE_ID, &d) || (d != d0))
1646 break;
1647 s->bus = bus; s->devfn = devfn;
1648 s->vendor = v; s->device = d; s->revision = r;
1649
1650 /* Check for power management capabilities */
1651 pci_readb(bus, devfn, PCI_STATUS, &a);
1652 if (a & PCI_STATUS_CAPLIST) {
1653 pci_readb(bus, devfn, PCI_CB_CAPABILITY_POINTER, &b);
1654 while (b != 0) {
1655 pci_readb(bus, devfn, b+PCI_CAPABILITY_ID, &a);
1656 if (a == PCI_CAPABILITY_PM) {
1657 s->pmcs = b + PCI_PM_CONTROL_STATUS;
1658 break;
1659 }
1660 pci_readb(bus, devfn, b+PCI_NEXT_CAPABILITY, &b);
1661 }
1662 }
1663 /* If capability exists, make sure we're in D0 state */
1664 if (s->pmcs)
1665 pci_writew(bus, devfn, s->pmcs, PCI_PMCS_PWR_STATE_D0);
1666
1667 /* Map CardBus registers if they are not already mapped */
1668 pci_writel(bus, devfn, CB_LEGACY_MODE_BASE, 0);
1669 pci_readl(bus, devfn, PCI_BASE_ADDRESS_0, &s->cb_phys);
1670 if (s->cb_phys == 0) {
1671 int i;
1672 pci_writew(bus, devfn, PCI_COMMAND, CMD_DFLT);
1673 for (i = 0; i < sizeof(cb_mem_base)/sizeof(u_int); i++) {
1674 s->cb_phys = cb_mem_base[i];
1675 s->cb_virt = ioremap(s->cb_phys, 0x1000);
1676 pci_writel(bus, devfn, PCI_BASE_ADDRESS_0, s->cb_phys);
1677 /* Simple sanity checks */
1678 if (((readb(s->cb_virt+0x800+I365_IDENT) & 0xf0)
1679 == 0x80) &&
1680 !(readb(s->cb_virt+0x800+I365_CSC) &&
1681 readb(s->cb_virt+0x800+I365_CSC) &&
1682 readb(s->cb_virt+0x800+I365_CSC)))
1683 break;
1684 iounmap(s->cb_virt);
1685 }
1686 if (i == sizeof(cb_mem_base)/sizeof(u_int)) {
1687 pci_writel(bus, devfn, PCI_BASE_ADDRESS_0, 0);
1688 s->cb_phys = 0; s->cb_virt = NULL;
1689 printk("\n");
1690 printk(KERN_NOTICE " Bridge register mapping failed:"
1691 " check cb_mem_base setting\n");
1692 break;
1693 }
1694 cb_mem_base[0] = cb_mem_base[i] + PAGE_SIZE;
1695 } else {
1696 s->cb_virt = ioremap(s->cb_phys, 0x1000);
1697 }
1698
1699 request_mem_region(s->cb_phys, 0x1000, "i82365");
1700 add_socket(0, 0, type);
1701 }
1702 if (ns == 0) return;
1703
1704 s -= ns;
1705 if (ns == 2) {
1706 /* Nasty special check for bad bus mapping */
1707 pci_readb(bus, s[0].devfn, CB_CARDBUS_BUS, &a);
1708 pci_readb(bus, s[1].devfn, CB_CARDBUS_BUS, &b);
1709 if (a == b) {
1710 pci_writeb(bus, s[0].devfn, CB_CARDBUS_BUS, 0);
1711 pci_writeb(bus, s[1].devfn, CB_CARDBUS_BUS, 0);
1712 }
1713 }
1714 add_pcic(ns, type);
1715
1716 /* Re-do card type & voltage detection */
1717 cb_writel(sockets-ns, CB_SOCKET_FORCE, CB_SF_CVSTEST);
1718 current->state = TASK_INTERRUPTIBLE;
1719 schedule_timeout(HZ/5);
1720
1721 /* Set up PCI bus bridge structures if needed */
1722 for (a = 0; a < ns; a++) {
1723 struct pci_dev *self = pci_find_slot(bus, s[a].devfn);
1724 struct pci_bus *child, *parent = self->bus;
1725 for (child = parent->children; child; child = child->next)
1726 if (child->number == s[a].cap.cardbus) break;
1727 if (!child) {
1728 child = kmalloc(sizeof(struct pci_bus), GFP_KERNEL);
1729 memset(child, 0, sizeof(struct pci_bus));
1730 child->self = self;
1731 child->primary = bus;
1732 child->number = child->secondary = s[a].cap.cardbus;
1733 child->subordinate = s[a].sub_bus;
1734 child->parent = parent;
1735 child->ops = parent->ops;
1736 child->next = parent->children;
1737 }
1738 s[a].cap.cb_bus = parent->children = child;
1739 }
1740 }
1741
1742 static void pci_probe(u_int class, void (add_fn)(int, u_char, u_char,
1743 u_short, u_short))
1744 {
1745 u_short i, v, d;
1746 u_char bus, devfn;
1747 pci_id_t id;
1748
1749 id = 0;
1750 while (pci_lookup(class, &id, &bus, &devfn) == 0) {
1751 if (PCI_FUNC(devfn) != 0) continue;
1752 pci_readw(bus, devfn, PCI_VENDOR_ID, &v);
1753 pci_readw(bus, devfn, PCI_DEVICE_ID, &d);
1754 for (i = 0; i < PCIC_COUNT; i++)
1755 if ((pcic[i].vendor == v) && (pcic[i].device == d)) break;
1756 add_fn(i, bus, devfn, v, d);
1757 }
1758 }
1759
1760 #endif /* CONFIG_PCI */
1761
1762 /*====================================================================*/
1763
1764 #ifdef CONFIG_ISA
1765
1766 static void isa_probe(void)
1767 {
1768 int i, j, sock, k;
1769 int ns, id;
1770 u_short port;
1771
1772 if (check_region(i365_base, 2) != 0) {
1773 if (sockets == 0)
1774 printk("port conflict at %#x\n", i365_base);
1775 return;
1776 }
1777
1778 id = identify(i365_base, 0);
1779 if ((id == IS_I82365DF) && (identify(i365_base, 1) != id)) {
1780 for (i = 0; i < 4; i++) {
1781 if (i == ignore) continue;
1782 port = i365_base + ((i & 1) << 2) + ((i & 2) << 1);
1783 sock = (i & 1) << 1;
1784 if (identify(port, sock) == IS_I82365DF) {
1785 add_socket(port, sock, IS_VLSI);
1786 add_pcic(1, IS_VLSI);
1787 }
1788 }
1789 } else {
1790 for (i = 0; i < (extra_sockets ? 8 : 4); i += 2) {
1791 port = i365_base + 2*(i>>2);
1792 sock = (i & 3);
1793 id = identify(port, sock);
1794 if (id < 0) continue;
1795
1796 for (j = ns = 0; j < 2; j++) {
1797 /* Does the socket exist? */
1798 if ((ignore == i+j) || (identify(port, sock+j) < 0))
1799 continue;
1800 /* Check for bad socket decode */
1801 for (k = 0; k <= sockets; k++)
1802 i365_set(k, I365_MEM(0)+I365_W_OFF, k);
1803 for (k = 0; k <= sockets; k++)
1804 if (i365_get(k, I365_MEM(0)+I365_W_OFF) != k)
1805 break;
1806 if (k <= sockets) break;
1807 add_socket(port, sock+j, id); ns++;
1808 }
1809 if (ns != 0) add_pcic(ns, id);
1810 }
1811 }
1812 }
1813
1814 #endif
1815
1816 /*====================================================================*/
1817
1818 static int pcic_init(void)
1819 {
1820 DEBUG(0, "%s\n", version);
1821 printk(KERN_INFO "Intel PCIC probe: ");
1822 sockets = 0;
1823
1824 #ifdef CONFIG_PCI
1825 if (do_pci_probe && pcibios_present()) {
1826 pci_probe(PCI_CLASS_BRIDGE_CARDBUS, add_cb_bridge);
1827 pci_probe(PCI_CLASS_BRIDGE_PCMCIA, add_pci_bridge);
1828 }
1829 #endif
1830
1831 #ifdef CONFIG_ISA
1832 isa_probe();
1833 #endif
1834
1835 if (sockets == 0) {
1836 printk("not found.\n");
1837 return -ENODEV;
1838 }
1839
1840 /* Set up interrupt handler, and/or polling */
1841 #ifdef CONFIG_ISA
1842 if (grab_irq != 0)
1843 request_irq(cs_irq, pcic_interrupt, 0, "i82365", NULL);
1844 #endif
1845 #ifdef CONFIG_PCI
1846 if (pci_csc) {
1847 u_int i, irq, mask = 0;
1848 for (i = 0; i < sockets; i++) {
1849 irq = socket[i].cap.pci_irq;
1850 if (irq && !(mask & (1<<irq)))
1851 request_irq(irq, pcic_interrupt, SA_SHIRQ, "i82365", NULL);
1852 mask |= (1<<irq);
1853 }
1854 }
1855 #endif
1856
1857 if (register_ss_entry(sockets, &pcic_service) != 0)
1858 printk(KERN_NOTICE "i82365: register_ss_entry() failed\n");
1859
1860 /* Finally, schedule a polling interrupt */
1861 if (poll_interval != 0) {
1862 poll_timer.function = pcic_interrupt_wrapper;
1863 poll_timer.data = 0;
1864 poll_timer.prev = poll_timer.next = NULL;
1865 poll_timer.expires = jiffies + poll_interval;
1866 add_timer(&poll_timer);
1867 }
1868
1869 return 0;
1870
1871 } /* pcic_init */
1872
1873 /*====================================================================*/
1874
1875 static void pcic_finish(void)
1876 {
1877 int i;
1878 #ifdef CONFIG_PROC_FS
1879 for (i = 0; i < sockets; i++) pcic_proc_remove(i);
1880 #endif
1881 unregister_ss_entry(&pcic_service);
1882 if (poll_interval != 0)
1883 del_timer(&poll_timer);
1884 #ifdef CONFIG_ISA
1885 if (grab_irq != 0)
1886 free_irq(cs_irq, NULL);
1887 #endif
1888 #ifdef CONFIG_PCI
1889 if (pci_csc) {
1890 u_int irq, mask = 0;
1891 for (i = 0; i < sockets; i++) {
1892 irq = socket[i].cap.pci_irq;
1893 if (irq && !(mask & (1<<irq)))
1894 free_irq(irq, NULL);
1895 mask |= (1<<irq);
1896 }
1897 }
1898 #endif
1899 for (i = 0; i < sockets; i++) {
1900 i365_set(i, I365_CSCINT, 0);
1901 #ifdef CONFIG_PCI
1902 if (socket[i].cb_virt) {
1903 iounmap(socket[i].cb_virt);
1904 release_mem_region(socket[i].cb_phys, 0x1000);
1905 } else
1906 #endif
1907 release_region(socket[i].ioaddr, 2);
1908 }
1909 } /* pcic_finish */
1910
1911 /*====================================================================*/
1912
1913 static void pcic_interrupt_wrapper(u_long data)
1914 {
1915 pcic_interrupt(0, NULL, NULL);
1916 poll_timer.expires = jiffies + poll_interval;
1917 add_timer(&poll_timer);
1918 }
1919
1920 static void pcic_interrupt(int irq, void *dev, struct pt_regs *regs)
1921 {
1922 int i, j, csc;
1923 u_int events, active;
1924 #ifdef CONFIG_ISA
1925 u_long flags = 0;
1926 #endif
1927
1928 DEBUG(4, "i82365: pcic_interrupt(%d)\n", irq);
1929
1930 for (j = 0; j < 20; j++) {
1931 active = 0;
1932 for (i = 0; i < sockets; i++) {
1933 if ((socket[i].cs_irq != irq) &&
1934 (socket[i].cap.pci_irq != irq))
1935 continue;
1936 #ifdef CONFIG_ISA
1937 if (!(socket[i].flags & IS_CARDBUS))
1938 spin_lock_irqsave(&isa_lock, flags);
1939 #endif
1940 csc = i365_get(i, I365_CSC);
1941 if ((csc == 0) || (!socket[i].handler) ||
1942 (i365_get(i, I365_IDENT) & 0x70)) {
1943 #ifdef CONFIG_ISA
1944 if (!(socket[i].flags & IS_CARDBUS))
1945 spin_unlock_irqrestore(&isa_lock, flags);
1946 #endif
1947 continue;
1948 }
1949 events = (csc & I365_CSC_DETECT) ? SS_DETECT : 0;
1950 if (i365_get(i, I365_INTCTL) & I365_PC_IOCARD)
1951 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
1952 else {
1953 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
1954 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
1955 events |= (csc & I365_CSC_READY) ? SS_READY : 0;
1956 }
1957 #ifdef CONFIG_ISA
1958 if (!(socket[i].flags & IS_CARDBUS))
1959 spin_unlock_irqrestore(&isa_lock, flags);
1960 #endif
1961 DEBUG(2, "i82365: socket %d event 0x%02x\n", i, events);
1962 if (events)
1963 socket[i].handler(socket[i].info, events);
1964 active |= events;
1965 }
1966 if (!active) break;
1967 }
1968 if (j == 20)
1969 printk(KERN_NOTICE "i82365: infinite loop in interrupt handler\n");
1970
1971 DEBUG(4, ("i82365: interrupt done\n"));
1972 } /* pcic_interrupt */
1973
1974 /*====================================================================*/
1975
1976 static int pcic_register_callback(u_short sock, ss_callback_t *call)
1977 {
1978 if (call == NULL) {
1979 socket[sock].handler = NULL;
1980 MOD_DEC_USE_COUNT;
1981 } else {
1982 MOD_INC_USE_COUNT;
1983 socket[sock].handler = call->handler;
1984 socket[sock].info = call->info;
1985 }
1986 return 0;
1987 } /* pcic_register_callback */
1988
1989 /*====================================================================*/
1990
1991 static int pcic_inquire_socket(u_short sock, socket_cap_t *cap)
1992 {
1993 *cap = socket[sock].cap;
1994 return 0;
1995 } /* pcic_inquire_socket */
1996
1997 /*====================================================================*/
1998
1999 static int i365_get_status(u_short sock, u_int *value)
2000 {
2001 u_int status;
2002
2003 status = i365_get(sock, I365_STATUS);
2004 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT)
2005 ? SS_DETECT : 0;
2006 if (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD)
2007 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
2008 else {
2009 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
2010 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
2011 }
2012 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
2013 *value |= (status & I365_CS_READY) ? SS_READY : 0;
2014 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
2015
2016 #ifdef CONFIG_PCI
2017 if (socket[sock].flags & IS_CARDBUS) {
2018 status = cb_readl(sock, CB_SOCKET_STATE);
2019 #ifndef CONFIG_CARDBUS
2020 *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
2021 #endif
2022 *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
2023 *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
2024 } else if (socket[sock].flags & IS_O2MICRO) {
2025 status = i365_get(sock, O2_MODE_B);
2026 *value |= (status & O2_MODE_B_VS1) ? 0 : SS_3VCARD;
2027 *value |= (status & O2_MODE_B_VS2) ? 0 : SS_XVCARD;
2028 }
2029 #endif
2030 #ifdef CONFIG_ISA
2031 if (socket[sock].type == IS_VG469) {
2032 status = i365_get(sock, VG469_VSENSE);
2033 if (socket[sock].psock & 1) {
2034 *value |= (status & VG469_VSENSE_B_VS1) ? 0 : SS_3VCARD;
2035 *value |= (status & VG469_VSENSE_B_VS2) ? 0 : SS_XVCARD;
2036 } else {
2037 *value |= (status & VG469_VSENSE_A_VS1) ? 0 : SS_3VCARD;
2038 *value |= (status & VG469_VSENSE_A_VS2) ? 0 : SS_XVCARD;
2039 }
2040 }
2041 #endif
2042
2043 DEBUG(1, "i82365: GetStatus(%d) = %#4.4x\n", sock, *value);
2044 return 0;
2045 } /* i365_get_status */
2046
2047 /*====================================================================*/
2048
2049 static int i365_get_socket(u_short sock, socket_state_t *state)
2050 {
2051 socket_info_t *t = &socket[sock];
2052 u_char reg, vcc, vpp;
2053
2054 reg = i365_get(sock, I365_POWER);
2055 state->flags = (reg & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
2056 state->flags |= (reg & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
2057 vcc = reg & I365_VCC_MASK; vpp = reg & I365_VPP1_MASK;
2058 state->Vcc = state->Vpp = 0;
2059 #ifdef CONFIG_PCI
2060 if (t->flags & IS_CARDBUS) {
2061 cb_get_power(sock, state);
2062 } else
2063 #endif
2064 if (t->flags & IS_CIRRUS) {
2065 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) {
2066 if (reg & I365_VCC_5V) state->Vcc = 33;
2067 if (vpp == I365_VPP1_5V) state->Vpp = 33;
2068 } else {
2069 if (reg & I365_VCC_5V) state->Vcc = 50;
2070 if (vpp == I365_VPP1_5V) state->Vpp = 50;
2071 }
2072 if (vpp == I365_VPP1_12V) state->Vpp = 120;
2073 } else if (t->flags & IS_VG_PWR) {
2074 if (i365_get(sock, VG469_VSELECT) & VG469_VSEL_VCC) {
2075 if (reg & I365_VCC_5V) state->Vcc = 33;
2076 if (vpp == I365_VPP1_5V) state->Vpp = 33;
2077 } else {
2078 if (reg & I365_VCC_5V) state->Vcc = 50;
2079 if (vpp == I365_VPP1_5V) state->Vpp = 50;
2080 }
2081 if (vpp == I365_VPP1_12V) state->Vpp = 120;
2082 } else if (t->flags & IS_DF_PWR) {
2083 if (vcc == I365_VCC_3V) state->Vcc = 33;
2084 if (vcc == I365_VCC_5V) state->Vcc = 50;
2085 if (vpp == I365_VPP1_5V) state->Vpp = 50;
2086 if (vpp == I365_VPP1_12V) state->Vpp = 120;
2087 } else {
2088 if (reg & I365_VCC_5V) {
2089 state->Vcc = 50;
2090 if (vpp == I365_VPP1_5V) state->Vpp = 50;
2091 if (vpp == I365_VPP1_12V) state->Vpp = 120;
2092 }
2093 }
2094
2095 /* IO card, RESET flags, IO interrupt */
2096 reg = i365_get(sock, I365_INTCTL);
2097 state->flags |= (reg & I365_PC_RESET) ? 0 : SS_RESET;
2098 if (reg & I365_PC_IOCARD) state->flags |= SS_IOCARD;
2099 #ifdef CONFIG_PCI
2100 if (cb_get_irq_mode(sock) != 0)
2101 state->io_irq = t->cap.pci_irq;
2102 else
2103 #endif
2104 state->io_irq = reg & I365_IRQ_MASK;
2105
2106 /* speaker control */
2107 if (t->flags & IS_CIRRUS) {
2108 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_SPKR_ENA)
2109 state->flags |= SS_SPKR_ENA;
2110 }
2111
2112 /* Card status change mask */
2113 reg = i365_get(sock, I365_CSCINT);
2114 state->csc_mask = (reg & I365_CSC_DETECT) ? SS_DETECT : 0;
2115 if (state->flags & SS_IOCARD)
2116 state->csc_mask |= (reg & I365_CSC_STSCHG) ? SS_STSCHG : 0;
2117 else {
2118 state->csc_mask |= (reg & I365_CSC_BVD1) ? SS_BATDEAD : 0;
2119 state->csc_mask |= (reg & I365_CSC_BVD2) ? SS_BATWARN : 0;
2120 state->csc_mask |= (reg & I365_CSC_READY) ? SS_READY : 0;
2121 }
2122
2123 DEBUG(1, "i82365: GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
2124 "io_irq %d, csc_mask %#2.2x\n", sock, state->flags,
2125 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
2126 return 0;
2127 } /* i365_get_socket */
2128
2129 /*====================================================================*/
2130
2131 static int i365_set_socket(u_short sock, socket_state_t *state)
2132 {
2133 socket_info_t *t = &socket[sock];
2134 u_char reg;
2135
2136 DEBUG(1, "i82365: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
2137 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
2138 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
2139
2140 /* First set global controller options */
2141 #ifdef CONFIG_PCI
2142 if ((t->flags & IS_CARDBUS) && t->cap.pci_irq)
2143 cb_set_irq_mode(sock, pci_csc,
2144 (t->cap.pci_irq == state->io_irq));
2145 t->bcr &= ~CB_BCR_CB_RESET;
2146 #endif
2147 set_host_state(sock);
2148
2149 /* IO card, RESET flag, IO interrupt */
2150 reg = t->intr;
2151 if (state->io_irq != t->cap.pci_irq) reg |= state->io_irq;
2152 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
2153 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
2154 i365_set(sock, I365_INTCTL, reg);
2155
2156 reg = I365_PWR_NORESET;
2157 if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO;
2158 if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT;
2159
2160 #ifdef CONFIG_PCI
2161 if (t->flags & IS_CARDBUS) {
2162 cb_set_power(sock, state);
2163 reg |= i365_get(sock, I365_POWER) &
2164 (I365_VCC_MASK|I365_VPP1_MASK);
2165 } else
2166 #endif
2167 if (t->flags & IS_CIRRUS) {
2168 if (state->Vpp != 0) {
2169 if (state->Vpp == 120)
2170 reg |= I365_VPP1_12V;
2171 else if (state->Vpp == state->Vcc)
2172 reg |= I365_VPP1_5V;
2173 else return -EINVAL;
2174 }
2175 if (state->Vcc != 0) {
2176 reg |= I365_VCC_5V;
2177 if (state->Vcc == 33)
2178 i365_bset(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
2179 else if (state->Vcc == 50)
2180 i365_bclr(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
2181 else return -EINVAL;
2182 }
2183 } else if (t->flags & IS_VG_PWR) {
2184 if (state->Vpp != 0) {
2185 if (state->Vpp == 120)
2186 reg |= I365_VPP1_12V;
2187 else if (state->Vpp == state->Vcc)
2188 reg |= I365_VPP1_5V;
2189 else return -EINVAL;
2190 }
2191 if (state->Vcc != 0) {
2192 reg |= I365_VCC_5V;
2193 if (state->Vcc == 33)
2194 i365_bset(sock, VG469_VSELECT, VG469_VSEL_VCC);
2195 else if (state->Vcc == 50)
2196 i365_bclr(sock, VG469_VSELECT, VG469_VSEL_VCC);
2197 else return -EINVAL;
2198 }
2199 } else if (t->flags & IS_DF_PWR) {
2200 switch (state->Vcc) {
2201 case 0: break;
2202 case 33: reg |= I365_VCC_3V; break;
2203 case 50: reg |= I365_VCC_5V; break;
2204 default: return -EINVAL;
2205 }
2206 switch (state->Vpp) {
2207 case 0: break;
2208 case 50: reg |= I365_VPP1_5V; break;
2209 case 120: reg |= I365_VPP1_12V; break;
2210 default: return -EINVAL;
2211 }
2212 } else {
2213 switch (state->Vcc) {
2214 case 0: break;
2215 case 50: reg |= I365_VCC_5V; break;
2216 default: return -EINVAL;
2217 }
2218 switch (state->Vpp) {
2219 case 0: break;
2220 case 50: reg |= I365_VPP1_5V | I365_VPP2_5V; break;
2221 case 120: reg |= I365_VPP1_12V | I365_VPP2_12V; break;
2222 default: return -EINVAL;
2223 }
2224 }
2225
2226 if (reg != i365_get(sock, I365_POWER))
2227 i365_set(sock, I365_POWER, reg);
2228
2229 /* Chipset-specific functions */
2230 if (t->flags & IS_CIRRUS) {
2231 /* Speaker control */
2232 i365_bflip(sock, PD67_MISC_CTL_1, PD67_MC1_SPKR_ENA,
2233 state->flags & SS_SPKR_ENA);
2234 }
2235
2236 /* Card status change interrupt mask */
2237 reg = t->cs_irq << 4;
2238 if (state->csc_mask & SS_DETECT) reg |= I365_CSC_DETECT;
2239 if (state->flags & SS_IOCARD) {
2240 if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG;
2241 } else {
2242 if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1;
2243 if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2;
2244 if (state->csc_mask & SS_READY) reg |= I365_CSC_READY;
2245 }
2246 i365_set(sock, I365_CSCINT, reg);
2247 i365_get(sock, I365_CSC);
2248
2249 return 0;
2250 } /* i365_set_socket */
2251
2252 /*====================================================================*/
2253
2254 static int i365_get_io_map(u_short sock, struct pccard_io_map *io)
2255 {
2256 u_char map, ioctl, addr;
2257
2258 map = io->map;
2259 if (map > 1) return -EINVAL;
2260 io->start = i365_get_pair(sock, I365_IO(map)+I365_W_START);
2261 io->stop = i365_get_pair(sock, I365_IO(map)+I365_W_STOP);
2262 ioctl = i365_get(sock, I365_IOCTL);
2263 addr = i365_get(sock, I365_ADDRWIN);
2264 io->speed = to_ns(ioctl & I365_IOCTL_WAIT(map)) ? 1 : 0;
2265 io->flags = (addr & I365_ENA_IO(map)) ? MAP_ACTIVE : 0;
2266 io->flags |= (ioctl & I365_IOCTL_0WS(map)) ? MAP_0WS : 0;
2267 io->flags |= (ioctl & I365_IOCTL_16BIT(map)) ? MAP_16BIT : 0;
2268 io->flags |= (ioctl & I365_IOCTL_IOCS16(map)) ? MAP_AUTOSZ : 0;
2269 DEBUG(1, "i82365: GetIOMap(%d, %d) = %#2.2x, %d ns, "
2270 "%#4.4x-%#4.4x\n", sock, map, io->flags, io->speed,
2271 io->start, io->stop);
2272 return 0;
2273 } /* i365_get_io_map */
2274
2275 /*====================================================================*/
2276
2277 static int i365_set_io_map(u_short sock, struct pccard_io_map *io)
2278 {
2279 u_char map, ioctl;
2280
2281 DEBUG(1, "i82365: SetIOMap(%d, %d, %#2.2x, %d ns, "
2282 "%#4.4x-%#4.4x)\n", sock, io->map, io->flags,
2283 io->speed, io->start, io->stop);
2284 map = io->map;
2285 if ((map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) ||
2286 (io->stop < io->start)) return -EINVAL;
2287 /* Turn off the window before changing anything */
2288 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(map))
2289 i365_bclr(sock, I365_ADDRWIN, I365_ENA_IO(map));
2290 i365_set_pair(sock, I365_IO(map)+I365_W_START, io->start);
2291 i365_set_pair(sock, I365_IO(map)+I365_W_STOP, io->stop);
2292 ioctl = i365_get(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map);
2293 if (io->speed) ioctl |= I365_IOCTL_WAIT(map);
2294 if (io->flags & MAP_0WS) ioctl |= I365_IOCTL_0WS(map);
2295 if (io->flags & MAP_16BIT) ioctl |= I365_IOCTL_16BIT(map);
2296 if (io->flags & MAP_AUTOSZ) ioctl |= I365_IOCTL_IOCS16(map);
2297 i365_set(sock, I365_IOCTL, ioctl);
2298 /* Turn on the window if necessary */
2299 if (io->flags & MAP_ACTIVE)
2300 i365_bset(sock, I365_ADDRWIN, I365_ENA_IO(map));
2301 return 0;
2302 } /* i365_set_io_map */
2303
2304 /*====================================================================*/
2305
2306 static int i365_get_mem_map(u_short sock, struct pccard_mem_map *mem)
2307 {
2308 u_short base, i;
2309 u_char map, addr;
2310
2311 map = mem->map;
2312 if (map > 4) return -EINVAL;
2313 addr = i365_get(sock, I365_ADDRWIN);
2314 mem->flags = (addr & I365_ENA_MEM(map)) ? MAP_ACTIVE : 0;
2315 base = I365_MEM(map);
2316
2317 i = i365_get_pair(sock, base+I365_W_START);
2318 mem->flags |= (i & I365_MEM_16BIT) ? MAP_16BIT : 0;
2319 mem->flags |= (i & I365_MEM_0WS) ? MAP_0WS : 0;
2320 mem->sys_start += ((u_long)(i & 0x0fff) << 12);
2321
2322 i = i365_get_pair(sock, base+I365_W_STOP);
2323 mem->speed = (i & I365_MEM_WS0) ? 1 : 0;
2324 mem->speed += (i & I365_MEM_WS1) ? 2 : 0;
2325 mem->speed = to_ns(mem->speed);
2326 mem->sys_stop = ((u_long)(i & 0x0fff) << 12) + 0x0fff;
2327
2328 i = i365_get_pair(sock, base+I365_W_OFF);
2329 mem->flags |= (i & I365_MEM_WRPROT) ? MAP_WRPROT : 0;
2330 mem->flags |= (i & I365_MEM_REG) ? MAP_ATTRIB : 0;
2331 mem->card_start = ((u_int)(i & 0x3fff) << 12) + mem->sys_start;
2332 mem->card_start &= 0x3ffffff;
2333
2334 #ifdef CONFIG_PCI
2335 /* Take care of high byte, for PCI controllers */
2336 if (socket[sock].type == IS_PD6729) {
2337 i365_set(sock, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
2338 addr = i365_get(sock, PD67_EXT_DATA) << 24;
2339 } else if (socket[sock].flags & IS_CARDBUS) {
2340 addr = i365_get(sock, CB_MEM_PAGE(map)) << 24;
2341 mem->sys_stop += addr; mem->sys_start += addr;
2342 }
2343 #endif
2344
2345 DEBUG(1, "i82365: GetMemMap(%d, %d) = %#2.2x, %d ns, %#5.5lx-%#5."
2346 "5lx, %#5.5x\n", sock, mem->map, mem->flags, mem->speed,
2347 mem->sys_start, mem->sys_stop, mem->card_start);
2348 return 0;
2349 } /* i365_get_mem_map */
2350
2351 /*====================================================================*/
2352
2353 static int i365_set_mem_map(u_short sock, struct pccard_mem_map *mem)
2354 {
2355 u_short base, i;
2356 u_char map;
2357
2358 DEBUG(1, "i82365: SetMemMap(%d, %d, %#2.2x, %d ns, %#5.5lx-%#5.5"
2359 "lx, %#5.5x)\n", sock, mem->map, mem->flags, mem->speed,
2360 mem->sys_start, mem->sys_stop, mem->card_start);
2361
2362 map = mem->map;
2363 if ((map > 4) || (mem->card_start > 0x3ffffff) ||
2364 (mem->sys_start > mem->sys_stop) || (mem->speed > 1000))
2365 return -EINVAL;
2366 if (!(socket[sock].flags & (IS_PCI | IS_CARDBUS)) &&
2367 ((mem->sys_start > 0xffffff) || (mem->sys_stop > 0xffffff)))
2368 return -EINVAL;
2369
2370 /* Turn off the window before changing anything */
2371 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
2372 i365_bclr(sock, I365_ADDRWIN, I365_ENA_MEM(map));
2373
2374 #ifdef CONFIG_PCI
2375 /* Take care of high byte, for PCI controllers */
2376 if (socket[sock].type == IS_PD6729) {
2377 i365_set(sock, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
2378 i365_set(sock, PD67_EXT_DATA, (mem->sys_start >> 24));
2379 } else if (socket[sock].flags & IS_CARDBUS)
2380 i365_set(sock, CB_MEM_PAGE(map), mem->sys_start >> 24);
2381 #endif
2382
2383 base = I365_MEM(map);
2384 i = (mem->sys_start >> 12) & 0x0fff;
2385 if (mem->flags & MAP_16BIT) i |= I365_MEM_16BIT;
2386 if (mem->flags & MAP_0WS) i |= I365_MEM_0WS;
2387 i365_set_pair(sock, base+I365_W_START, i);
2388
2389 i = (mem->sys_stop >> 12) & 0x0fff;
2390 switch (to_cycles(mem->speed)) {
2391 case 0: break;
2392 case 1: i |= I365_MEM_WS0; break;
2393 case 2: i |= I365_MEM_WS1; break;
2394 default: i |= I365_MEM_WS1 | I365_MEM_WS0; break;
2395 }
2396 i365_set_pair(sock, base+I365_W_STOP, i);
2397
2398 i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
2399 if (mem->flags & MAP_WRPROT) i |= I365_MEM_WRPROT;
2400 if (mem->flags & MAP_ATTRIB) i |= I365_MEM_REG;
2401 i365_set_pair(sock, base+I365_W_OFF, i);
2402
2403 /* Turn on the window if necessary */
2404 if (mem->flags & MAP_ACTIVE)
2405 i365_bset(sock, I365_ADDRWIN, I365_ENA_MEM(map));
2406 return 0;
2407 } /* i365_set_mem_map */
2408
2409 /*======================================================================
2410
2411 Power control for Cardbus controllers: used both for 16-bit and
2412 Cardbus cards.
2413
2414 ======================================================================*/
2415
2416 #ifdef CONFIG_PCI
2417
2418 static void cb_get_power(u_short sock, socket_state_t *state)
2419 {
2420 u_int reg = cb_readl(sock, CB_SOCKET_CONTROL);
2421 state->Vcc = state->Vpp = 0;
2422 switch (reg & CB_SC_VCC_MASK) {
2423 case CB_SC_VCC_3V: state->Vcc = 33; break;
2424 case CB_SC_VCC_5V: state->Vcc = 50; break;
2425 }
2426 switch (reg & CB_SC_VCC_MASK) {
2427 case CB_SC_VPP_3V: state->Vpp = 33; break;
2428 case CB_SC_VPP_5V: state->Vpp = 50; break;
2429 case CB_SC_VPP_12V: state->Vpp = 120; break;
2430 }
2431 }
2432
2433 static void cb_set_power(u_short sock, socket_state_t *state)
2434 {
2435 u_int reg = 0;
2436 switch (state->Vcc) {
2437 case 33: reg = CB_SC_VCC_3V; break;
2438 case 50: reg = CB_SC_VCC_5V; break;
2439 default: reg = 0; break;
2440 }
2441 switch (state->Vpp) {
2442 case 33: reg |= CB_SC_VPP_3V; break;
2443 case 50: reg |= CB_SC_VPP_5V; break;
2444 case 120: reg |= CB_SC_VPP_12V; break;
2445 }
2446 if (reg != cb_readl(sock, CB_SOCKET_CONTROL))
2447 cb_writel(sock, CB_SOCKET_CONTROL, reg);
2448 }
2449
2450 #endif
2451
2452 /*======================================================================
2453
2454 All the stuff that is strictly for Cardbus cards goes here.
2455
2456 ======================================================================*/
2457
2458 #ifdef CONFIG_CARDBUS
2459
2460 static int cb_get_status(u_short sock, u_int *value)
2461 {
2462 u_int s;
2463 s = cb_readl(sock, CB_SOCKET_STATE);
2464 *value = ((s & CB_SS_32BIT) ? SS_CARDBUS : 0);
2465 *value |= ((s & CB_SS_CCD1) || (s & CB_SS_CCD2)) ? 0 : SS_DETECT;
2466 *value |= (s & CB_SS_CSTSCHG) ? SS_STSCHG : 0;
2467 *value |= (s & CB_SS_PWRCYCLE) ? (SS_POWERON|SS_READY) : 0;
2468 *value |= (s & CB_SS_3VCARD) ? SS_3VCARD : 0;
2469 *value |= (s & CB_SS_XVCARD) ? SS_XVCARD : 0;
2470 DEBUG(1, "yenta: GetStatus(%d) = %#4.4x\n", sock, *value);
2471 return 0;
2472 } /* cb_get_status */
2473
2474 static int cb_get_socket(u_short sock, socket_state_t *state)
2475 {
2476 socket_info_t *s = &socket[sock];
2477 u_short bcr;
2478
2479 cb_get_power(sock, state);
2480 pci_readw(s->bus, s->devfn, CB_BRIDGE_CONTROL, &bcr);
2481 state->flags |= (bcr & CB_BCR_CB_RESET) ? SS_RESET : 0;
2482 if (cb_get_irq_mode(sock) != 0)
2483 state->io_irq = s->cap.pci_irq;
2484 else
2485 state->io_irq = i365_get(sock, I365_INTCTL) & I365_IRQ_MASK;
2486 DEBUG(1, "yenta: GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
2487 "io_irq %d, csc_mask %#2.2x\n", sock, state->flags,
2488 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
2489 return 0;
2490 } /* cb_get_socket */
2491
2492 static int cb_set_socket(u_short sock, socket_state_t *state)
2493 {
2494 socket_info_t *s = &socket[sock];
2495 u_int reg;
2496
2497 DEBUG(1, "yenta: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
2498 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
2499 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
2500
2501 /* First set global controller options */
2502 if (s->cap.pci_irq)
2503 cb_set_irq_mode(sock, pci_csc,
2504 (s->cap.pci_irq == state->io_irq));
2505 s->bcr &= ~CB_BCR_CB_RESET;
2506 s->bcr |= (state->flags & SS_RESET) ? CB_BCR_CB_RESET : 0;
2507 set_host_state(sock);
2508
2509 cb_set_power(sock, state);
2510
2511 /* Handle IO interrupt using ISA routing */
2512 reg = i365_get(sock, I365_INTCTL) & ~I365_IRQ_MASK;
2513 if (state->io_irq != s->cap.pci_irq) reg |= state->io_irq;
2514 i365_set(sock, I365_INTCTL, reg);
2515
2516 /* Handle CSC mask */
2517 reg = (socket[sock].cs_irq << 4);
2518 if (state->csc_mask & SS_DETECT) reg |= I365_CSC_DETECT;
2519 i365_set(sock, I365_CSCINT, reg);
2520 i365_get(sock, I365_CSC);
2521
2522 return 0;
2523 } /* cb_set_socket */
2524
2525 static int cb_get_bridge(u_short sock, struct cb_bridge_map *m)
2526 {
2527 socket_info_t *s = &socket[sock];
2528 u_char map;
2529
2530 map = m->map;
2531 if (map > 1) return -EINVAL;
2532 m->flags &= MAP_IOSPACE;
2533 map += (m->flags & MAP_IOSPACE) ? 2 : 0;
2534 pci_readl(s->bus, s->devfn, CB_MEM_BASE(map), &m->start);
2535 pci_readl(s->bus, s->devfn, CB_MEM_LIMIT(map), &m->stop);
2536 if (m->start || m->stop) {
2537 m->flags |= MAP_ACTIVE;
2538 m->stop |= (map > 1) ? 3 : 0x0fff;
2539 }
2540 if (map > 1) {
2541 u_short bcr;
2542 pci_readw(s->bus, s->devfn, CB_BRIDGE_CONTROL, &bcr);
2543 m->flags |= (bcr & CB_BCR_PREFETCH(map)) ? MAP_PREFETCH : 0;
2544 }
2545 DEBUG(1, "yenta: GetBridge(%d, %d) = %#2.2x, %#4.4x-%#4.4x\n",
2546 sock, map, m->flags, m->start, m->stop);
2547 return 0;
2548 }
2549
2550 static int cb_set_bridge(u_short sock, struct cb_bridge_map *m)
2551 {
2552 socket_info_t *s = &socket[sock];
2553 u_char map;
2554
2555 DEBUG(1, "yenta: SetBridge(%d, %d, %#2.2x, %#4.4x-%#4.4x)\n",
2556 sock, m->map, m->flags, m->start, m->stop);
2557 map = m->map;
2558 if (!(s->flags & IS_CARDBUS) || (map > 1) || (m->stop < m->start))
2559 return -EINVAL;
2560 if (m->flags & MAP_IOSPACE) {
2561 if ((m->stop > 0xffff) || (m->start & 3) ||
2562 ((m->stop & 3) != 3))
2563 return -EINVAL;
2564 map += 2;
2565 } else {
2566 u_short bcr;
2567 if ((m->start & 0x0fff) || ((m->stop & 0x0fff) != 0x0fff))
2568 return -EINVAL;
2569 pci_readw(s->bus, s->devfn, CB_BRIDGE_CONTROL, &bcr);
2570 bcr &= ~CB_BCR_PREFETCH(map);
2571 bcr |= (m->flags & MAP_PREFETCH) ? CB_BCR_PREFETCH(map) : 0;
2572 pci_writew(s->bus, s->devfn, CB_BRIDGE_CONTROL, bcr);
2573 }
2574 if (m->flags & MAP_ACTIVE) {
2575 pci_writel(s->bus, s->devfn, CB_MEM_BASE(map), m->start);
2576 pci_writel(s->bus, s->devfn, CB_MEM_LIMIT(map), m->stop);
2577 } else {
2578 pci_writel(s->bus, s->devfn, CB_IO_BASE(map), 0);
2579 pci_writel(s->bus, s->devfn, CB_IO_LIMIT(map), 0);
2580 }
2581 return 0;
2582 }
2583
2584 #endif /* CONFIG_CARDBUS */
2585
2586 /*======================================================================
2587
2588 Routines for accessing socket information and register dumps via
2589 /proc/bus/pccard/...
2590
2591 ======================================================================*/
2592
2593 #ifdef CONFIG_PROC_FS
2594
2595 static int proc_read_info(char *buf, char **start, off_t pos,
2596 int count, int *eof, void *data)
2597 {
2598 socket_info_t *s = data;
2599 char *p = buf;
2600 p += sprintf(p, "type: %s\npsock: %d\n",
2601 pcic[s->type].name, s->psock);
2602 #ifdef CONFIG_PCI
2603 if (s->flags & (IS_PCI|IS_CARDBUS))
2604 p += sprintf(p, "bus: %02x\ndevfn: %02x.%1x\n",
2605 s->bus, PCI_SLOT(s->devfn), PCI_FUNC(s->devfn));
2606 if (s->flags & IS_CARDBUS)
2607 p += sprintf(p, "cardbus: %02x\n", s->cap.cardbus);
2608 #endif
2609 return (p - buf);
2610 }
2611
2612 static int proc_read_exca(char *buf, char **start, off_t pos,
2613 int count, int *eof, void *data)
2614 {
2615 u_short sock = (socket_info_t *)data - socket;
2616 char *p = buf;
2617 int i, top;
2618
2619 #ifdef CONFIG_ISA
2620 u_long flags = 0;
2621 if (!(socket[sock].flags & IS_CARDBUS))
2622 spin_lock_irqsave(&isa_lock, flags);
2623 #endif
2624 top = 0x40;
2625 if (socket[sock].flags & IS_CARDBUS)
2626 top = (socket[sock].flags & IS_CIRRUS) ? 0x140 : 0x50;
2627 for (i = 0; i < top; i += 4) {
2628 if (i == 0x50) {
2629 p += sprintf(p, "\n");
2630 i = 0x100;
2631 }
2632 p += sprintf(p, "%02x %02x %02x %02x%s",
2633 i365_get(sock,i), i365_get(sock,i+1),
2634 i365_get(sock,i+2), i365_get(sock,i+3),
2635 ((i % 16) == 12) ? "\n" : " ");
2636 }
2637 #ifdef CONFIG_ISA
2638 if (!(socket[sock].flags & IS_CARDBUS))
2639 spin_unlock_irqrestore(&isa_lock, flags);
2640 #endif
2641 return (p - buf);
2642 }
2643
2644
2645 #ifdef CONFIG_PCI
2646 static int proc_read_pci(char *buf, char **start, off_t pos,
2647 int count, int *eof, void *data)
2648 {
2649 socket_info_t *s = data;
2650 u_char bus = s->bus, devfn = s->devfn;
2651 char *p = buf;
2652 u_int a, b, c, d;
2653 int i;
2654
2655 for (i = 0; i < 0xc0; i += 0x10) {
2656 pci_readl(bus, devfn, i, &a);
2657 pci_readl(bus, devfn, i+4, &b);
2658 pci_readl(bus, devfn, i+8, &c);
2659 pci_readl(bus, devfn, i+12, &d);
2660 p += sprintf(p, "%08x %08x %08x %08x\n", a, b, c, d);
2661 }
2662 return (p - buf);
2663 }
2664 #endif
2665
2666 #ifdef CONFIG_CARDBUS
2667 static int proc_read_cardbus(char *buf, char **start, off_t pos,
2668 int count, int *eof, void *data)
2669 {
2670 u_short sock = (socket_info_t *)data - socket;
2671 int len;
2672
2673 len = sprintf(buf, "%08x %08x %08x %08x %08x %08x\n",
2674 cb_readl(sock,0), cb_readl(sock,4),
2675 cb_readl(sock,8), cb_readl(sock,12),
2676 cb_readl(sock,16), cb_readl(sock,32));
2677 return len;
2678 }
2679 #endif
2680
2681 static void pcic_proc_setup(u_short sock, struct proc_dir_entry *base)
2682 {
2683 socket_info_t *s = &socket[sock];
2684 struct proc_dir_entry *ent;
2685 ent = create_proc_entry("info", 0, base);
2686 ent->read_proc = proc_read_info;
2687 ent->data = s;
2688 ent = create_proc_entry("exca", 0, base);
2689 ent->read_proc = proc_read_exca;
2690 ent->data = s;
2691 #ifdef CONFIG_PCI
2692 if (s->flags & (IS_PCI|IS_CARDBUS)) {
2693 ent = create_proc_entry("pci", 0, base);
2694 ent->read_proc = proc_read_pci;
2695 ent->data = s;
2696 }
2697 #endif
2698 #ifdef CONFIG_CARDBUS
2699 if (s->flags & IS_CARDBUS) {
2700 ent = create_proc_entry("cardbus", 0, base);
2701 ent->read_proc = proc_read_cardbus;
2702 ent->data = s;
2703 }
2704 #endif
2705 s->proc = base;
2706 }
2707
2708 static void pcic_proc_remove(u_short sock)
2709 {
2710 struct proc_dir_entry *base = socket[sock].proc;
2711 if (base == NULL) return;
2712 remove_proc_entry("info", base);
2713 remove_proc_entry("exca", base);
2714 #ifdef CONFIG_PCI
2715 if (socket[sock].flags & (IS_PCI|IS_CARDBUS))
2716 remove_proc_entry("pci", base);
2717 #endif
2718 #ifdef CONFIG_CARDBUS
2719 if (socket[sock].flags & IS_CARDBUS)
2720 remove_proc_entry("cardbus", base);
2721 #endif
2722 }
2723
2724 #endif /* CONFIG_PROC_FS */
2725
2726 /*====================================================================*/
2727
2728 typedef int (*subfn_t)(u_short, void *);
2729
2730 static subfn_t pcic_service_table[] = {
2731 (subfn_t)&pcic_register_callback,
2732 (subfn_t)&pcic_inquire_socket,
2733 (subfn_t)&i365_get_status,
2734 (subfn_t)&i365_get_socket,
2735 (subfn_t)&i365_set_socket,
2736 (subfn_t)&i365_get_io_map,
2737 (subfn_t)&i365_set_io_map,
2738 (subfn_t)&i365_get_mem_map,
2739 (subfn_t)&i365_set_mem_map,
2740 #ifdef CONFIG_CARDBUS
2741 (subfn_t)&cb_get_bridge,
2742 (subfn_t)&cb_set_bridge,
2743 #else
2744 NULL, NULL,
2745 #endif
2746 #ifdef CONFIG_PROC_FS
2747 (subfn_t)&pcic_proc_setup
2748 #endif
2749 };
2750
2751 #define NFUNC (sizeof(pcic_service_table)/sizeof(subfn_t))
2752
2753 static int pcic_service(u_int sock, u_int cmd, void *arg)
2754 {
2755 subfn_t fn;
2756
2757 DEBUG(2, "pcic_ioctl(%d, %d, 0x%p)\n", sock, cmd, arg);
2758
2759 if (cmd >= NFUNC)
2760 return -EINVAL;
2761
2762 if (socket[sock].flags & IS_ALIVE) {
2763 if (cmd == SS_GetStatus)
2764 *(u_int *)arg = 0;
2765 return -EINVAL;
2766 }
2767
2768 fn = pcic_service_table[cmd];
2769 #ifdef CONFIG_CARDBUS
2770 if ((socket[sock].flags & IS_CARDBUS) &&
2771 (cb_readl(sock, CB_SOCKET_STATE) & CB_SS_32BIT)) {
2772 if (cmd == SS_GetStatus)
2773 fn = (subfn_t)&cb_get_status;
2774 else if (cmd == SS_GetSocket)
2775 fn = (subfn_t)&cb_get_socket;
2776 else if (cmd == SS_SetSocket)
2777 fn = (subfn_t)&cb_set_socket;
2778 }
2779 #endif
2780
2781 #ifdef CONFIG_ISA
2782 if (!(socket[sock].flags & IS_CARDBUS)) {
2783 int ret;
2784 u_long flags;
2785 spin_lock_irqsave(&isa_lock, flags);
2786 ret = (fn == NULL) ? -EINVAL : fn(sock, arg);
2787 spin_unlock_irqrestore(&isa_lock, flags);
2788 return ret;
2789 }
2790 #endif
2791 return (fn == NULL) ? -EINVAL : fn(sock, arg);
2792 } /* pcic_service */
2793
2794 /*====================================================================*/
2795
2796 int pcmcia_i82365_init(void)
2797 {
2798 servinfo_t serv;
2799 CardServices(GetCardServicesInfo, &serv);
2800 if (serv.Revision != CS_RELEASE_CODE) {
2801 printk(KERN_NOTICE "i82365: Card Services release "
2802 "does not match!\n");
2803 return -1;
2804 }
2805 return pcic_init();
2806 }
2807
2808 #ifdef MODULE
2809
2810 int init_module(void)
2811 {
2812 return pcmcia_i82365_init();
2813 }
2814
2815 void cleanup_module(void)
2816 {
2817 pcic_finish();
2818 }
2819
2820 #endif
2821
2822 /*====================================================================*/
2823
Copy of Dave Jones history.git as used by http://archive.org/details/git-history-of-linux