?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Import 2.3.18pre1
[davej-history.git] / arch / sparc64 / kernel / pci_psycho.c
blob1afe5a67bf199c1db65588be0d50e7b0dc8f4edd
1 /* $Id: pci_psycho.c,v 1.4 1999/09/05 09:33:36 ecd Exp $
2 * pci_psycho.c: PSYCHO/U2P specific PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/malloc.h>
14
15 #include <asm/pbm.h>
16 #include <asm/iommu.h>
17 #include <asm/irq.h>
18
19 #include "pci_impl.h"
20
21 /* All PSYCHO registers are 64-bits. The following accessor
22 * routines are how they are accessed. The REG parameter
23 * is a physical address.
24 */
25 #define psycho_read(__reg) \
26 ({ u64 __ret; \
27 __asm__ __volatile__("ldxa [%1] %2, %0" \
28 : "=r" (__ret) \
29 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
30 : "memory"); \
31 __ret; \
32 })
33 #define psycho_write(__reg, __val) \
34 __asm__ __volatile__("stxa %0, [%1] %2" \
35 : /* no outputs */ \
36 : "r" (__val), "r" (__reg), \
37 "i" (ASI_PHYS_BYPASS_EC_E))
38
39 /* Misc. PSYCHO PCI controller register offsets and definitions. */
40 #define PSYCHO_CONTROL 0x0010UL
41 #define PSYCHO_CONTROL_IMPL 0xf000000000000000 /* Implementation of this PSYCHO*/
42 #define PSYCHO_CONTROL_VER 0x0f00000000000000 /* Version of this PSYCHO */
43 #define PSYCHO_CONTROL_MID 0x00f8000000000000 /* UPA Module ID of PSYCHO */
44 #define PSYCHO_CONTROL_IGN 0x0007c00000000000 /* Interrupt Group Number */
45 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0 /* Reserved */
46 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008 /* Address Parity Check Enable */
47 #define PSYCHO_CONTROL_APERR 0x0000000000000004 /* Incoming System Addr Parerr */
48 #define PSYCHO_CONTROL_IAP 0x0000000000000002 /* Invert UPA Parity */
49 #define PSYCHO_CONTROL_MODE 0x0000000000000001 /* PSYCHO clock mode */
50 #define PSYCHO_PCIA_CTRL 0x2000UL
51 #define PSYCHO_PCIB_CTRL 0x4000UL
52 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000 /* Reserved */
53 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000 /* Streaming byte hole error */
54 #define PSYCHO_PCICTRL_SERR 0x0000000400000000 /* SERR signal asserted */
55 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000 /* PCI speed (1 is U2P clock) */
56 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000 /* Reserved */
57 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */
58 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800 /* Reserved */
59 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400 /* Streaming byte hole int enab */
60 #define PSYCHO_PCICTRL_WEN 0x0000000000000200 /* Power Mgmt Wake Enable */
61 #define PSYCHO_PCICTRL_EEN 0x0000000000000100 /* PCI Error Interrupt Enable */
62 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0 /* Reserved */
63 #define PSYCHO_PCICTRL_AEN 0x000000000000003f /* PCI DVMA Arbitration Enable */
64
65 /* U2P Programmer's Manual, page 13-55, configuration space
66 * address format:
67 *
68 * 32 24 23 16 15 11 10 8 7 2 1 0
69 * ---------------------------------------------------------
70 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
71 * ---------------------------------------------------------
72 */
73 #define PSYCHO_CONFIG_BASE(PBM) \
74 ((PBM)->parent->config_space | (1UL << 24))
75 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
76 (((unsigned long)(BUS) << 16) | \
77 ((unsigned long)(DEVFN) << 8) | \
78 ((unsigned long)(REG)))
79
80 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
81 unsigned char bus,
82 unsigned int devfn,
83 int where)
84 {
85 if (!pbm)
86 return NULL;
87 return (void *)
88 (PSYCHO_CONFIG_BASE(pbm) |
89 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
90 }
91
92 static int psycho_out_of_range(struct pci_pbm_info *pbm,
93 unsigned char bus,
94 unsigned char devfn)
95 {
96 return ((pbm->parent == 0) ||
97 ((pbm == &pbm->parent->pbm_B) &&
98 (bus == pbm->pci_first_busno) &&
99 PCI_SLOT(devfn) > 8) ||
100 ((pbm == &pbm->parent->pbm_A) &&
101 (bus == pbm->pci_first_busno) &&
102 PCI_SLOT(devfn) > 8));
103 }
104
105 /* PSYCHO PCI configuration space accessors. */
106
107 static int psycho_read_byte(struct pci_dev *dev, int where, u8 *value)
108 {
109 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
110 unsigned char bus = dev->bus->number;
111 unsigned int devfn = dev->devfn;
112 u8 *addr;
113
114 *value = 0xff;
115 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
116 if (!addr)
117 return PCIBIOS_SUCCESSFUL;
118
119 if (psycho_out_of_range(pbm, bus, devfn))
120 return PCIBIOS_SUCCESSFUL;
121 pci_config_read8(addr, value);
122 return PCIBIOS_SUCCESSFUL;
123 }
124
125 static int psycho_read_word(struct pci_dev *dev, int where, u16 *value)
126 {
127 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
128 unsigned char bus = dev->bus->number;
129 unsigned int devfn = dev->devfn;
130 u16 *addr;
131
132 *value = 0xffff;
133 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
134 if (!addr)
135 return PCIBIOS_SUCCESSFUL;
136
137 if (psycho_out_of_range(pbm, bus, devfn))
138 return PCIBIOS_SUCCESSFUL;
139
140 if (where & 0x01) {
141 printk("pcibios_read_config_word: misaligned reg [%x]\n",
142 where);
143 return PCIBIOS_SUCCESSFUL;
144 }
145 pci_config_read16(addr, value);
146 return PCIBIOS_SUCCESSFUL;
147 }
148
149 static int psycho_read_dword(struct pci_dev *dev, int where, u32 *value)
150 {
151 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
152 unsigned char bus = dev->bus->number;
153 unsigned int devfn = dev->devfn;
154 u32 *addr;
155
156 *value = 0xffffffff;
157 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
158 if (!addr)
159 return PCIBIOS_SUCCESSFUL;
160
161 if (psycho_out_of_range(pbm, bus, devfn))
162 return PCIBIOS_SUCCESSFUL;
163
164 if (where & 0x03) {
165 printk("pcibios_read_config_dword: misaligned reg [%x]\n",
166 where);
167 return PCIBIOS_SUCCESSFUL;
168 }
169
170 pci_config_read32(addr, value);
171 return PCIBIOS_SUCCESSFUL;
172 }
173
174 static int psycho_write_byte(struct pci_dev *dev, int where, u8 value)
175 {
176 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
177 unsigned char bus = dev->bus->number;
178 unsigned int devfn = dev->devfn;
179 u8 *addr;
180
181 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
182 if (!addr)
183 return PCIBIOS_SUCCESSFUL;
184
185 if (psycho_out_of_range(pbm, bus, devfn))
186 return PCIBIOS_SUCCESSFUL;
187
188 pci_config_write8(addr, value);
189 return PCIBIOS_SUCCESSFUL;
190 }
191
192 static int psycho_write_word(struct pci_dev *dev, int where, u16 value)
193 {
194 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
195 unsigned char bus = dev->bus->number;
196 unsigned int devfn = dev->devfn;
197 u16 *addr;
198
199 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
200 if (!addr)
201 return PCIBIOS_SUCCESSFUL;
202
203 if (psycho_out_of_range(pbm, bus, devfn))
204 return PCIBIOS_SUCCESSFUL;
205
206 if (where & 0x01) {
207 printk("pcibios_write_config_word: misaligned reg [%x]\n",
208 where);
209 return PCIBIOS_SUCCESSFUL;
210 }
211 pci_config_write16(addr, value);
212 return PCIBIOS_SUCCESSFUL;
213 }
214
215 static int psycho_write_dword(struct pci_dev *dev, int where, u32 value)
216 {
217 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
218 unsigned char bus = dev->bus->number;
219 unsigned int devfn = dev->devfn;
220 u32 *addr;
221
222 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
223 if (!addr)
224 return PCIBIOS_SUCCESSFUL;
225
226 if (psycho_out_of_range(pbm, bus, devfn))
227 return PCIBIOS_SUCCESSFUL;
228
229 if (where & 0x03) {
230 printk("pcibios_write_config_dword: misaligned reg [%x]\n",
231 where);
232 return PCIBIOS_SUCCESSFUL;
233 }
234 pci_config_write32(addr, value);
235 return PCIBIOS_SUCCESSFUL;
236 }
237
238 static struct pci_ops psycho_ops = {
239 psycho_read_byte,
240 psycho_read_word,
241 psycho_read_dword,
242 psycho_write_byte,
243 psycho_write_word,
244 psycho_write_dword
245 };
246
247 /* PSYCHO interrupt mapping support. */
248 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
249 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
250 static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
251 {
252 unsigned int bus = (ino & 0x10) >> 4;
253 unsigned int slot = (ino & 0x0c) >> 2;
254
255 if (bus == 0)
256 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
257 else
258 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
259 }
260
261 #define PSYCHO_IMAP_SCSI 0x1000UL
262 #define PSYCHO_IMAP_ETH 0x1008UL
263 #define PSYCHO_IMAP_BPP 0x1010UL
264 #define PSYCHO_IMAP_AU_REC 0x1018UL
265 #define PSYCHO_IMAP_AU_PLAY 0x1020UL
266 #define PSYCHO_IMAP_PFAIL 0x1028UL
267 #define PSYCHO_IMAP_KMS 0x1030UL
268 #define PSYCHO_IMAP_FLPY 0x1038UL
269 #define PSYCHO_IMAP_SHW 0x1040UL
270 #define PSYCHO_IMAP_KBD 0x1048UL
271 #define PSYCHO_IMAP_MS 0x1050UL
272 #define PSYCHO_IMAP_SER 0x1058UL
273 #define PSYCHO_IMAP_TIM0 0x1060UL
274 #define PSYCHO_IMAP_TIM1 0x1068UL
275 #define PSYCHO_IMAP_UE 0x1070UL
276 #define PSYCHO_IMAP_CE 0x1078UL
277 #define PSYCHO_IMAP_A_ERR 0x1080UL
278 #define PSYCHO_IMAP_B_ERR 0x1088UL
279 #define PSYCHO_IMAP_PMGMT 0x1090UL
280 #define PSYCHO_IMAP_GFX 0x1098UL
281 #define PSYCHO_IMAP_EUPA 0x10a0UL
282
283 static unsigned long __onboard_imap_off[] = {
284 /*0x20*/ PSYCHO_IMAP_SCSI,
285 /*0x21*/ PSYCHO_IMAP_ETH,
286 /*0x22*/ PSYCHO_IMAP_BPP,
287 /*0x23*/ PSYCHO_IMAP_AU_REC,
288 /*0x24*/ PSYCHO_IMAP_AU_PLAY,
289 /*0x25*/ PSYCHO_IMAP_PFAIL,
290 /*0x26*/ PSYCHO_IMAP_KMS,
291 /*0x27*/ PSYCHO_IMAP_FLPY,
292 /*0x28*/ PSYCHO_IMAP_SHW,
293 /*0x29*/ PSYCHO_IMAP_KBD,
294 /*0x2a*/ PSYCHO_IMAP_MS,
295 /*0x2b*/ PSYCHO_IMAP_SER,
296 /*0x2c*/ PSYCHO_IMAP_TIM0,
297 /*0x2d*/ PSYCHO_IMAP_TIM1,
298 /*0x2e*/ PSYCHO_IMAP_UE,
299 /*0x2f*/ PSYCHO_IMAP_CE,
300 /*0x30*/ PSYCHO_IMAP_A_ERR,
301 /*0x31*/ PSYCHO_IMAP_B_ERR,
302 /*0x32*/ PSYCHO_IMAP_PMGMT
303 };
304 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
305 #define PSYCHO_ONBOARD_IRQ_LAST 0x32
306 #define psycho_onboard_imap_offset(__ino) \
307 __onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
308
309 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
310 #define PSYCHO_ICLR_SCSI 0x1800UL
311
312 #define psycho_iclr_offset(ino) \
313 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
314 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
315
316 /* PCI PSYCHO INO number to Sparc PIL level. */
317 static unsigned char psycho_pil_table[] = {
318 /*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
319 /*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
320 /*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
321 /*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
322 /*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
323 /*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
324 /*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
325 /*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
326 /*0x20*/3, /* SCSI */
327 /*0x21*/5, /* Ethernet */
328 /*0x22*/8, /* Parallel Port */
329 /*0x23*/13, /* Audio Record */
330 /*0x24*/14, /* Audio Playback */
331 /*0x25*/15, /* PowerFail */
332 /*0x26*/3, /* second SCSI */
333 /*0x27*/11, /* Floppy */
334 /*0x28*/2, /* Spare Hardware */
335 /*0x29*/9, /* Keyboard */
336 /*0x2a*/4, /* Mouse */
337 /*0x2b*/12, /* Serial */
338 /*0x2c*/10, /* Timer 0 */
339 /*0x2d*/11, /* Timer 1 */
340 /*0x2e*/15, /* Uncorrectable ECC */
341 /*0x2f*/15, /* Correctable ECC */
342 /*0x30*/15, /* PCI Bus A Error */
343 /*0x31*/15, /* PCI Bus B Error */
344 /*0x32*/1, /* Power Management */
345 };
346
347 static int __init psycho_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
348 {
349 int ret;
350
351 ret = psycho_pil_table[ino];
352 if (ret == 0 && pdev == NULL) {
353 ret = 1;
354 } else if (ret == 0) {
355 switch ((pdev->class >> 16) & 0x0f) {
356 case PCI_BASE_CLASS_STORAGE:
357 ret = 4;
358
359 case PCI_BASE_CLASS_NETWORK:
360 ret = 6;
361
362 case PCI_BASE_CLASS_DISPLAY:
363 ret = 9;
364
365 case PCI_BASE_CLASS_MULTIMEDIA:
366 case PCI_BASE_CLASS_MEMORY:
367 case PCI_BASE_CLASS_BRIDGE:
368 ret = 10;
369
370 default:
371 ret = 1;
372 };
373 }
374
375 return ret;
376 }
377
378 static unsigned int __init psycho_irq_build(struct pci_controller_info *p,
379 struct pci_dev *pdev,
380 unsigned int ino)
381 {
382 struct ino_bucket *bucket;
383 volatile unsigned int *imap, *iclr;
384 unsigned long imap_off, iclr_off;
385 int pil, inofixup = 0;
386
387 ino &= PCI_IRQ_INO;
388 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
389 /* PCI slot */
390 imap_off = psycho_pcislot_imap_offset(ino);
391 } else {
392 /* Onboard device */
393 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
394 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
395 prom_halt();
396 }
397 imap_off = psycho_onboard_imap_offset(ino);
398 }
399
400 /* Now build the IRQ bucket. */
401 pil = psycho_ino_to_pil(pdev, ino);
402 imap = (volatile unsigned int *)__va(p->controller_regs + imap_off);
403 imap += 1;
404
405 iclr_off = psycho_iclr_offset(ino);
406 iclr = (volatile unsigned int *)__va(p->controller_regs + iclr_off);
407 iclr += 1;
408
409 if ((ino & 0x20) == 0)
410 inofixup = ino & 0x03;
411
412 bucket = __bucket(build_irq(pil, inofixup, iclr, imap));
413 bucket->flags |= IBF_PCI;
414
415 return __irq(bucket);
416 }
417
418 /* PSYCHO error handling support. */
419 enum psycho_error_type {
420 UE_ERR, CE_ERR, PCI_ERR
421 };
422
423 /* Helper function of IOMMU error checking, which checks out
424 * the state of the streaming buffers. The IOMMU lock is
425 * held when this is called.
426 *
427 * For the PCI error case we know which PBM (and thus which
428 * streaming buffer) caused the error, but for the uncorrectable
429 * error case we do not. So we always check both streaming caches.
430 */
431 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
432 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
433 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0 /* LRU Lock Pointer */
434 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008 /* LRU Lock Enable */
435 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004 /* Rerun Disable */
436 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002 /* Diagnostic Mode Enable */
437 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001 /* Streaming Buffer Enable */
438 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
439 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
440 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
441 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
442 #define PSYCHO_STC_DATA_A 0xb000UL
443 #define PSYCHO_STC_DATA_B 0xc000UL
444 #define PSYCHO_STC_ERR_A 0xb400UL
445 #define PSYCHO_STC_ERR_B 0xc400UL
446 #define PSYCHO_STCERR_WRITE 0x0000000000000002 /* Write Error */
447 #define PSYCHO_STCERR_READ 0x0000000000000001 /* Read Error */
448 #define PSYCHO_STC_TAG_A 0xb800UL
449 #define PSYCHO_STC_TAG_B 0xc800UL
450 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000 /* Physical Page Number */
451 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000 /* Virtual Page Number */
452 #define PSYCHO_STCTAG_VALID 0x0000000000000002 /* Valid */
453 #define PSYCHO_STCTAG_WRITE 0x0000000000000001 /* Writable */
454 #define PSYCHO_STC_LINE_A 0xb900UL
455 #define PSYCHO_STC_LINE_B 0xc900UL
456 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000 /* LRU Index */
457 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000 /* Dirty Data Start Pointer */
458 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00 /* Line Address */
459 #define PSYCHO_STCLINE_EPTR 0x00000000000000fc /* Dirty Data End Pointer */
460 #define PSYCHO_STCLINE_VALID 0x0000000000000002 /* Valid */
461 #define PSYCHO_STCLINE_FOFN 0x0000000000000001 /* Fetch Outstanding / Flush Necessary */
462
463 static spinlock_t stc_buf_lock = SPIN_LOCK_UNLOCKED;
464 static unsigned long stc_error_buf[128];
465 static unsigned long stc_tag_buf[16];
466 static unsigned long stc_line_buf[16];
467
468 static void __psycho_check_one_stc(struct pci_controller_info *p,
469 struct pci_pbm_info *pbm,
470 int is_pbm_a)
471 {
472 struct pci_strbuf *strbuf = &pbm->stc;
473 unsigned long regbase = p->controller_regs;
474 unsigned long err_base, tag_base, line_base;
475 u64 control;
476 int i;
477
478 if (is_pbm_a) {
479 err_base = regbase + PSYCHO_STC_ERR_A;
480 tag_base = regbase + PSYCHO_STC_TAG_A;
481 line_base = regbase + PSYCHO_STC_LINE_A;
482 } else {
483 err_base = regbase + PSYCHO_STC_ERR_A;
484 tag_base = regbase + PSYCHO_STC_TAG_A;
485 line_base = regbase + PSYCHO_STC_LINE_A;
486 }
487
488 spin_lock(&stc_buf_lock);
489
490 /* This is __REALLY__ dangerous. When we put the
491 * streaming buffer into diagnostic mode to probe
492 * it's tags and error status, we _must_ clear all
493 * of the line tag valid bits before re-enabling
494 * the streaming buffer. If any dirty data lives
495 * in the STC when we do this, we will end up
496 * invalidating it before it has a chance to reach
497 * main memory.
498 */
499 control = psycho_read(strbuf->strbuf_control);
500 psycho_write(strbuf->strbuf_control,
501 (control | PSYCHO_STRBUF_CTRL_DENAB));
502 for (i = 0; i < 128; i++) {
503 unsigned long val;
504
505 val = psycho_read(err_base + (i * 8UL));
506 psycho_write(err_base + (i * 8UL), 0UL);
507 stc_error_buf[i] = val;
508 }
509 for (i = 0; i < 16; i++) {
510 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
511 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
512 psycho_write(tag_base + (i * 8UL), 0UL);
513 psycho_write(line_base + (i * 8UL), 0UL);
514 }
515
516 /* OK, state is logged, exit diagnostic mode. */
517 psycho_write(strbuf->strbuf_control, control);
518
519 for (i = 0; i < 16; i++) {
520 int j, saw_error, first, last;
521
522 saw_error = 0;
523 first = i * 8;
524 last = first + 8;
525 for (j = first; j < last; j++) {
526 unsigned long errval = stc_error_buf[j];
527 if (errval != 0) {
528 saw_error++;
529 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
530 p->index,
531 (is_pbm_a ? 'A' : 'B'),
532 j,
533 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
534 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
535 }
536 }
537 if (saw_error != 0) {
538 unsigned long tagval = stc_tag_buf[i];
539 unsigned long lineval = stc_line_buf[i];
540 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
541 p->index,
542 (is_pbm_a ? 'A' : 'B'),
543 i,
544 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
545 (tagval & PSYCHO_STCTAG_VPN),
546 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
547 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
548 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
549 "V(%d)FOFN(%d)]\n",
550 p->index,
551 (is_pbm_a ? 'A' : 'B'),
552 i,
553 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
554 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
555 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
556 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
557 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
558 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
559 }
560 }
561
562 spin_unlock(&stc_buf_lock);
563 }
564
565 static void __psycho_check_stc_error(struct pci_controller_info *p,
566 unsigned long afsr,
567 unsigned long afar,
568 enum psycho_error_type type)
569 {
570 struct pci_pbm_info *pbm;
571
572 pbm = &p->pbm_A;
573 if (pbm->stc.strbuf_enabled)
574 __psycho_check_one_stc(p, pbm, 1);
575
576 pbm = &p->pbm_B;
577 if (pbm->stc.strbuf_enabled)
578 __psycho_check_one_stc(p, pbm, 0);
579 }
580
581 /* When an Uncorrectable Error or a PCI Error happens, we
582 * interrogate the IOMMU state to see if it is the cause.
583 */
584 #define PSYCHO_IOMMU_CONTROL 0x0200UL
585 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000 /* Reserved */
586 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000 /* Translation Error Status */
587 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000 /* Translation Error encountered */
588 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000 /* Enable translation locking */
589 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000 /* Translation lock pointer */
590 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000 /* TSB Size */
591 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000 /* TSB Table 1024 8-byte entries */
592 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000 /* TSB Table 2048 8-byte entries */
593 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000 /* TSB Table 4096 8-byte entries */
594 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000 /* TSB Table 8192 8-byte entries */
595 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000 /* TSB Table 16k 8-byte entries */
596 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000 /* TSB Table 32k 8-byte entries */
597 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000 /* TSB Table 64k 8-byte entries */
598 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000 /* TSB Table 128k 8-byte entries */
599 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8 /* Reserved */
600 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004 /* Assumed page size, 0=8k 1=64k */
601 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002 /* Diagnostic mode enable */
602 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001 /* IOMMU Enable */
603 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
604 #define PSYCHO_IOMMU_FLUSH 0x0210UL
605 #define PSYCHO_IOMMU_TAG 0xa580UL
606 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
607 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
608 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
609 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
610 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
611 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
612 #define PSYCHO_IOMMU_DATA 0xa600UL
613 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
614 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
615 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
616 static void psycho_check_iommu_error(struct pci_controller_info *p,
617 unsigned long afsr,
618 unsigned long afar,
619 enum psycho_error_type type)
620 {
621 unsigned long iommu_tag[16];
622 unsigned long iommu_data[16];
623 unsigned long flags;
624 u64 control;
625 int i;
626
627 spin_lock_irqsave(&p->iommu.lock, flags);
628 control = psycho_read(p->iommu.iommu_control);
629 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
630 char *type_string;
631
632 /* Clear the error encountered bit. */
633 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
634 psycho_write(p->iommu.iommu_control, control);
635
636 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
637 case 0:
638 type_string = "Protection Error";
639 break;
640 case 1:
641 type_string = "Invalid Error";
642 break;
643 case 2:
644 type_string = "TimeOut Error";
645 break;
646 case 3:
647 default:
648 type_string = "ECC Error";
649 break;
650 };
651 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
652 p->index, type_string);
653
654 /* Put the IOMMU into diagnostic mode and probe
655 * it's TLB for entries with error status.
656 *
657 * It is very possible for another DVMA to occur
658 * while we do this probe, and corrupt the system
659 * further. But we are so screwed at this point
660 * that we are likely to crash hard anyways, so
661 * get as much diagnostic information to the
662 * console as we can.
663 */
664 psycho_write(p->iommu.iommu_control,
665 control | PSYCHO_IOMMU_CTRL_DENAB);
666 for (i = 0; i < 16; i++) {
667 unsigned long base = p->controller_regs;
668
669 iommu_tag[i] =
670 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
671 iommu_data[i] =
672 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
673
674 /* Now clear out the entry. */
675 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
676 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
677 }
678
679 /* Leave diagnostic mode. */
680 psycho_write(p->iommu.iommu_control, control);
681
682 for (i = 0; i < 16; i++) {
683 unsigned long tag, data;
684
685 tag = iommu_tag[i];
686 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
687 continue;
688
689 data = iommu_data[i];
690 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
691 case 0:
692 type_string = "Protection Error";
693 break;
694 case 1:
695 type_string = "Invalid Error";
696 break;
697 case 2:
698 type_string = "TimeOut Error";
699 break;
700 case 3:
701 default:
702 type_string = "ECC Error";
703 break;
704 };
705 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
706 p->index, i, type_string,
707 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
708 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
709 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
710 (tag & PSYCHO_IOMMU_TAG_VPAGE) << PAGE_SHIFT);
711 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
712 p->index, i,
713 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
714 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
715 (data & PSYCHO_IOMMU_DATA_PPAGE) << PAGE_SHIFT);
716 }
717 }
718 __psycho_check_stc_error(p, afsr, afar, type);
719 spin_unlock_irqrestore(&p->iommu.lock, flags);
720 }
721
722 /* Uncorrectable Errors. Cause of the error and the address are
723 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
724 * relating to UPA interface transactions.
725 */
726 #define PSYCHO_UE_AFSR 0x0030UL
727 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */
728 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */
729 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */
730 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */
731 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */
732 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/
733 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000 /* Reserved */
734 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000 /* Bytemask of failed transfer */
735 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000 /* Doubleword Offset */
736 #define PSYCHO_UEAFSR_MID 0x000000001f000000 /* UPA MID causing the fault */
737 #define PSYCHO_UEAFSR_BLK 0x0000000000800000 /* Trans was block operation */
738 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffff /* Reserved */
739 #define PSYCHO_UE_AFAR 0x0038UL
740
741 static void psycho_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
742 {
743 struct pci_controller_info *p = dev_id;
744 unsigned long afsr_reg = p->controller_regs + PSYCHO_UE_AFSR;
745 unsigned long afar_reg = p->controller_regs + PSYCHO_UE_AFAR;
746 unsigned long afsr, afar, error_bits;
747 int reported;
748
749 /* Latch uncorrectable error status. */
750 afar = psycho_read(afar_reg);
751 afsr = psycho_read(afsr_reg);
752
753 /* Clear the primary/secondary error status bits. */
754 error_bits = afsr &
755 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
756 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
757 psycho_write(afsr_reg, error_bits);
758
759 /* Log the error. */
760 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
761 p->index,
762 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
763 "PIO" :
764 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
765 "DMA Read" :
766 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
767 "DMA Write" : "???")))));
768 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
769 p->index,
770 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
771 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
772 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
773 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
774 printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar);
775 printk("PSYCHO%d: UE Secondary errors [", p->index);
776 reported = 0;
777 if (afsr & PSYCHO_UEAFSR_SPIO) {
778 reported++;
779 printk("(PIO)");
780 }
781 if (afsr & PSYCHO_UEAFSR_SDRD) {
782 reported++;
783 printk("(DMA Read)");
784 }
785 if (afsr & PSYCHO_UEAFSR_SDWR) {
786 reported++;
787 printk("(DMA Write)");
788 }
789 if (!reported)
790 printk("(none)");
791 printk("]\n");
792
793 /* Interrogate IOMMU for error status. */
794 psycho_check_iommu_error(p, afsr, afar, UE_ERR);
795 }
796
797 /* Correctable Errors. */
798 #define PSYCHO_CE_AFSR 0x0040UL
799 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */
800 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */
801 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */
802 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */
803 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */
804 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/
805 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000 /* Reserved */
806 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000 /* Syndrome Bits */
807 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000 /* Bytemask of failed transfer */
808 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000 /* Double Offset */
809 #define PSYCHO_CEAFSR_MID 0x000000001f000000 /* UPA MID causing the fault */
810 #define PSYCHO_CEAFSR_BLK 0x0000000000800000 /* Trans was block operation */
811 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffff /* Reserved */
812 #define PSYCHO_CE_AFAR 0x0040UL
813
814 static void psycho_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
815 {
816 struct pci_controller_info *p = dev_id;
817 unsigned long afsr_reg = p->controller_regs + PSYCHO_CE_AFSR;
818 unsigned long afar_reg = p->controller_regs + PSYCHO_CE_AFAR;
819 unsigned long afsr, afar, error_bits;
820 int reported;
821
822 /* Latch error status. */
823 afar = psycho_read(afar_reg);
824 afsr = psycho_read(afsr_reg);
825
826 /* Clear primary/secondary error status bits. */
827 error_bits = afsr &
828 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
829 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
830 psycho_write(afsr_reg, error_bits);
831
832 /* Log the error. */
833 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
834 p->index,
835 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
836 "PIO" :
837 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
838 "DMA Read" :
839 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
840 "DMA Write" : "???")))));
841 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
842 "UPA_MID[%02lx] was_block(%d)\n",
843 p->index,
844 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
845 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
846 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
847 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
848 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
849 printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar);
850 printk("PSYCHO%d: CE Secondary errors [", p->index);
851 reported = 0;
852 if (afsr & PSYCHO_CEAFSR_SPIO) {
853 reported++;
854 printk("(PIO)");
855 }
856 if (afsr & PSYCHO_CEAFSR_SDRD) {
857 reported++;
858 printk("(DMA Read)");
859 }
860 if (afsr & PSYCHO_CEAFSR_SDWR) {
861 reported++;
862 printk("(DMA Write)");
863 }
864 if (!reported)
865 printk("(none)");
866 printk("]\n");
867 }
868
869 /* PCI Errors. They are signalled by the PCI bus module since they
870 * are assosciated with a specific bus segment.
871 */
872 #define PSYCHO_PCI_AFSR_A 0x2010UL
873 #define PSYCHO_PCI_AFSR_B 0x4010UL
874 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000 /* Primary Master Abort Error */
875 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000 /* Primary Target Abort Error */
876 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000 /* Primary Excessive Retries */
877 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000 /* Primary Parity Error */
878 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000 /* Secondary Master Abort Error */
879 #define PSYCHO_PCIAFSR_STA 0x0400000000000000 /* Secondary Target Abort Error */
880 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000 /* Secondary Excessive Retries */
881 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000 /* Secondary Parity Error */
882 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000 /* Reserved */
883 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000 /* Bytemask of failed transfer */
884 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000 /* Trans was block operation */
885 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000 /* Reserved */
886 #define PSYCHO_PCIAFSR_MID 0x000000003e000000 /* MID causing the error */
887 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffff /* Reserved */
888 #define PSYCHO_PCI_AFAR_A 0x2018UL
889 #define PSYCHO_PCI_AFAR_B 0x4018UL
890
891 static void psycho_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
892 {
893 struct pci_pbm_info *pbm = dev_id;
894 struct pci_controller_info *p = pbm->parent;
895 unsigned long afsr_reg, afar_reg;
896 unsigned long afsr, afar, error_bits;
897 int is_pbm_a, reported;
898
899 is_pbm_a = (pbm == &pbm->parent->pbm_A);
900 if (is_pbm_a) {
901 afsr_reg = p->controller_regs + PSYCHO_PCI_AFSR_A;
902 afar_reg = p->controller_regs + PSYCHO_PCI_AFAR_A;
903 } else {
904 afsr_reg = p->controller_regs + PSYCHO_PCI_AFSR_B;
905 afar_reg = p->controller_regs + PSYCHO_PCI_AFAR_B;
906 }
907
908 /* Latch error status. */
909 afar = psycho_read(afar_reg);
910 afsr = psycho_read(afsr_reg);
911
912 /* Clear primary/secondary error status bits. */
913 error_bits = afsr &
914 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
915 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
916 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
917 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
918 psycho_write(afsr_reg, error_bits);
919
920 /* Log the error. */
921 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
922 p->index, (is_pbm_a ? 'A' : 'B'),
923 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
924 "Master Abort" :
925 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
926 "Target Abort" :
927 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
928 "Excessive Retries" :
929 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
930 "Parity Error" : "???"))))));
931 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
932 p->index, (is_pbm_a ? 'A' : 'B'),
933 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
934 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
935 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
936 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
937 p->index, (is_pbm_a ? 'A' : 'B'), afar);
938 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
939 p->index, (is_pbm_a ? 'A' : 'B'));
940 reported = 0;
941 if (afsr & PSYCHO_PCIAFSR_SMA) {
942 reported++;
943 printk("(Master Abort)");
944 }
945 if (afsr & PSYCHO_PCIAFSR_STA) {
946 reported++;
947 printk("(Target Abort)");
948 }
949 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
950 reported++;
951 printk("(Excessive Retries)");
952 }
953 if (afsr & PSYCHO_PCIAFSR_SPERR) {
954 reported++;
955 printk("(Parity Error)");
956 }
957 if (!reported)
958 printk("(none)");
959 printk("]\n");
960
961 /* For the error types shown, scan PBM's PCI bus for devices
962 * which have logged that error type.
963 */
964
965 /* If we see a Target Abort, this could be the result of an
966 * IOMMU translation error of some sort. It is extremely
967 * useful to log this information as usually it indicates
968 * a bug in the IOMMU support code or a PCI device driver.
969 */
970 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
971 psycho_check_iommu_error(p, afsr, afar, PCI_ERR);
972 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
973 }
974 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
975 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
976
977 /* For excessive retries, PSYCHO/PBM will abort the device
978 * and there is no way to specifically check for excessive
979 * retries in the config space status registers. So what
980 * we hope is that we'll catch it via the master/target
981 * abort events.
982 */
983
984 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
985 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
986 }
987
988 /* XXX What about PowerFail/PowerManagement??? -DaveM */
989 #define PSYCHO_ECC_CTRL 0x0020
990 #define PSYCHO_ECCCTRL_EE 0x8000000000000000 /* Enable ECC Checking */
991 #define PSYCHO_ECCCTRL_UE 0x4000000000000000 /* Enable UE Interrupts */
992 #define PSYCHO_ECCCTRL_CE 0x2000000000000000 /* Enable CE INterrupts */
993 #define PSYCHO_UE_INO 0x2e
994 #define PSYCHO_CE_INO 0x2f
995 #define PSYCHO_PCIERR_A_INO 0x30
996 #define PSYCHO_PCIERR_B_INO 0x31
997 static void __init psycho_register_error_handlers(struct pci_controller_info *p)
998 {
999 unsigned long base = p->controller_regs;
1000 unsigned int irq, portid = p->portid;
1001 u64 tmp;
1002
1003 /* Build IRQs and register handlers. */
1004 irq = psycho_irq_build(p, NULL, (portid << 6) | PSYCHO_UE_INO);
1005 if (request_irq(irq, psycho_ue_intr,
1006 SA_SHIRQ, "PSYCHO UE", p) < 0) {
1007 prom_printf("PSYCHO%d: Cannot register UE interrupt.\n",
1008 p->index);
1009 prom_halt();
1010 }
1011
1012 irq = psycho_irq_build(p, NULL, (portid << 6) | PSYCHO_CE_INO);
1013 if (request_irq(irq, psycho_ce_intr,
1014 SA_SHIRQ, "PSYCHO CE", p) < 0) {
1015 prom_printf("PSYCHO%d: Cannot register CE interrupt.\n",
1016 p->index);
1017 prom_halt();
1018 }
1019
1020 irq = psycho_irq_build(p, NULL, (portid << 6) | PSYCHO_PCIERR_A_INO);
1021 if (request_irq(irq, psycho_pcierr_intr,
1022 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_A) < 0) {
1023 prom_printf("PSYCHO%d(PBMA): Cannot register PciERR interrupt.\n",
1024 p->index);
1025 prom_halt();
1026 }
1027
1028 irq = psycho_irq_build(p, NULL, (portid << 6) | PSYCHO_PCIERR_B_INO);
1029 if (request_irq(irq, psycho_pcierr_intr,
1030 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_B) < 0) {
1031 prom_printf("PSYCHO%d(PBMB): Cannot register PciERR interrupt.\n",
1032 p->index);
1033 prom_halt();
1034 }
1035
1036 /* Enable UE and CE interrupts for controller. */
1037 psycho_write(base + PSYCHO_ECC_CTRL,
1038 (PSYCHO_ECCCTRL_EE |
1039 PSYCHO_ECCCTRL_UE |
1040 PSYCHO_ECCCTRL_CE));
1041
1042 /* Enable PCI Error interrupts and clear error
1043 * bits for each PBM.
1044 */
1045 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
1046 tmp |= (PSYCHO_PCICTRL_SBH_ERR |
1047 PSYCHO_PCICTRL_SERR |
1048 PSYCHO_PCICTRL_SBH_INT |
1049 PSYCHO_PCICTRL_EEN);
1050 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
1051
1052 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
1053 tmp |= (PSYCHO_PCICTRL_SBH_ERR |
1054 PSYCHO_PCICTRL_SERR |
1055 PSYCHO_PCICTRL_SBH_INT |
1056 PSYCHO_PCICTRL_EEN);
1057 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
1058 }
1059
1060 /* PSYCHO boot time probing and initialization. */
1061 static void __init psycho_resource_adjust(struct pci_dev *pdev,
1062 struct resource *res,
1063 struct resource *root)
1064 {
1065 res->start += root->start;
1066 res->end += root->start;
1067 }
1068
1069 static void __init psycho_base_address_update(struct pci_dev *pdev, int resource)
1070 {
1071 struct pcidev_cookie *pcp = pdev->sysdata;
1072 struct pci_pbm_info *pbm = pcp->pbm;
1073 struct resource *res = &pdev->resource[resource];
1074 struct resource *root;
1075 u32 reg;
1076 int where, size;
1077
1078 if (res->flags & IORESOURCE_IO)
1079 root = &pbm->io_space;
1080 else
1081 root = &pbm->mem_space;
1082
1083 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1084 size = res->end - res->start;
1085 pci_read_config_dword(pdev, where, &reg);
1086 reg = ((reg & size) |
1087 (((u32)(res->start - root->start)) & ~size));
1088 pci_write_config_dword(pdev, where, reg);
1089 }
1090
1091 /* We have to do the config space accesses by hand, thus... */
1092 #define PBM_BRIDGE_BUS 0x40
1093 #define PBM_BRIDGE_SUBORDINATE 0x41
1094 static void __init pbm_renumber(struct pci_pbm_info *pbm, u8 orig_busno)
1095 {
1096 u8 *addr, busno;
1097 int nbus;
1098
1099 busno = pci_highest_busnum;
1100 nbus = pbm->pci_last_busno - pbm->pci_first_busno;
1101
1102 addr = psycho_pci_config_mkaddr(pbm, orig_busno,
1103 0, PBM_BRIDGE_BUS);
1104 pci_config_write8(addr, busno);
1105 addr = psycho_pci_config_mkaddr(pbm, busno,
1106 0, PBM_BRIDGE_SUBORDINATE);
1107 pci_config_write8(addr, busno + nbus);
1108
1109 pbm->pci_first_busno = busno;
1110 pbm->pci_last_busno = busno + nbus;
1111 pci_highest_busnum = busno + nbus + 1;
1112
1113 do {
1114 pci_bus2pbm[busno++] = pbm;
1115 } while (nbus--);
1116 }
1117
1118 /* We have to do the config space accesses by hand here since
1119 * the pci_bus2pbm array is not ready yet.
1120 */
1121 static void __init pbm_pci_bridge_renumber(struct pci_pbm_info *pbm,
1122 u8 busno)
1123 {
1124 u32 devfn, l, class;
1125 u8 hdr_type;
1126 int is_multi = 0;
1127
1128 for(devfn = 0; devfn < 0xff; ++devfn) {
1129 u32 *dwaddr;
1130 u8 *baddr;
1131
1132 if (PCI_FUNC(devfn) != 0 && is_multi == 0)
1133 continue;
1134
1135 /* Anything there? */
1136 dwaddr = psycho_pci_config_mkaddr(pbm, busno, devfn, PCI_VENDOR_ID);
1137 l = 0xffffffff;
1138 pci_config_read32(dwaddr, &l);
1139 if (l == 0xffffffff || l == 0x00000000 ||
1140 l == 0x0000ffff || l == 0xffff0000) {
1141 is_multi = 0;
1142 continue;
1143 }
1144
1145 baddr = psycho_pci_config_mkaddr(pbm, busno, devfn, PCI_HEADER_TYPE);
1146 pci_config_read8(baddr, &hdr_type);
1147 if (PCI_FUNC(devfn) == 0)
1148 is_multi = hdr_type & 0x80;
1149
1150 dwaddr = psycho_pci_config_mkaddr(pbm, busno, devfn, PCI_CLASS_REVISION);
1151 class = 0xffffffff;
1152 pci_config_read32(dwaddr, &class);
1153 if ((class >> 16) == PCI_CLASS_BRIDGE_PCI) {
1154 u32 buses = 0xffffffff;
1155
1156 dwaddr = psycho_pci_config_mkaddr(pbm, busno, devfn,
1157 PCI_PRIMARY_BUS);
1158 pci_config_read32(dwaddr, &buses);
1159 pbm_pci_bridge_renumber(pbm, (buses >> 8) & 0xff);
1160 buses &= 0xff000000;
1161 pci_config_write32(dwaddr, buses);
1162 }
1163 }
1164 }
1165
1166 static void __init pbm_bridge_reconfigure(struct pci_controller_info *p)
1167 {
1168 struct pci_pbm_info *pbm;
1169 u8 *addr;
1170
1171 /* Clear out primary/secondary/subordinate bus numbers on
1172 * all PCI-to-PCI bridges under each PBM. The generic bus
1173 * probing will fix them up.
1174 */
1175 pbm_pci_bridge_renumber(&p->pbm_B, p->pbm_B.pci_first_busno);
1176 pbm_pci_bridge_renumber(&p->pbm_A, p->pbm_A.pci_first_busno);
1177
1178 /* Move PBM A out of the way. */
1179 pbm = &p->pbm_A;
1180 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1181 0, PBM_BRIDGE_BUS);
1182 pci_config_write8(addr, 0xff);
1183 addr = psycho_pci_config_mkaddr(pbm, 0xff,
1184 0, PBM_BRIDGE_SUBORDINATE);
1185 pci_config_write8(addr, 0xff);
1186
1187 /* Now we can safely renumber both PBMs. */
1188 pbm_renumber(&p->pbm_B, p->pbm_B.pci_first_busno);
1189 pbm_renumber(&p->pbm_A, 0xff);
1190 }
1191
1192 static void __init pbm_scan_bus(struct pci_controller_info *p,
1193 struct pci_pbm_info *pbm)
1194 {
1195 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
1196 p->pci_ops,
1197 pbm);
1198 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
1199 pci_record_assignments(pbm, pbm->pci_bus);
1200 pci_assign_unassigned(pbm, pbm->pci_bus);
1201 pci_fixup_irq(pbm, pbm->pci_bus);
1202 }
1203
1204 static void __init psycho_scan_bus(struct pci_controller_info *p)
1205 {
1206 pbm_bridge_reconfigure(p);
1207 pbm_scan_bus(p, &p->pbm_B);
1208 pbm_scan_bus(p, &p->pbm_A);
1209
1210 /* After the PCI bus scan is complete, we can register
1211 * the error interrupt handlers.
1212 */
1213 psycho_register_error_handlers(p);
1214 }
1215
1216 static void __init psycho_iommu_init(struct pci_controller_info *p, int tsbsize)
1217 {
1218 extern int this_is_starfire;
1219 extern void *starfire_hookup(int);
1220 struct linux_mlist_p1275 *mlist;
1221 unsigned long tsbbase, i, n, order;
1222 iopte_t *iopte;
1223 u64 control;
1224
1225 /* Setup initial software IOMMU state. */
1226 spin_lock_init(&p->iommu.lock);
1227 p->iommu.iommu_cur_ctx = 0;
1228
1229 /* PSYCHO's IOMMU lacks ctx flushing. */
1230 p->iommu.iommu_has_ctx_flush = 0;
1231
1232 /* Register addresses. */
1233 p->iommu.iommu_control = p->controller_regs + PSYCHO_IOMMU_CONTROL;
1234 p->iommu.iommu_tsbbase = p->controller_regs + PSYCHO_IOMMU_TSBBASE;
1235 p->iommu.iommu_flush = p->controller_regs + PSYCHO_IOMMU_FLUSH;
1236 p->iommu.iommu_ctxflush = 0;
1237
1238 /* We use the main control register of PSYCHO as the write
1239 * completion register.
1240 */
1241 p->iommu.write_complete_reg = p->controller_regs + PSYCHO_CONTROL;
1242
1243 /*
1244 * Invalidate TLB Entries.
1245 */
1246 control = psycho_read(p->controller_regs + PSYCHO_IOMMU_CONTROL);
1247 control |= PSYCHO_IOMMU_CTRL_DENAB;
1248 psycho_write(p->controller_regs + PSYCHO_IOMMU_CONTROL, control);
1249 for(i = 0; i < 16; i++)
1250 psycho_write(p->controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
1251
1252 control &= ~(PSYCHO_IOMMU_CTRL_DENAB);
1253 psycho_write(p->controller_regs + PSYCHO_IOMMU_CONTROL, control);
1254
1255 for(order = 0;; order++)
1256 if((PAGE_SIZE << order) >= ((tsbsize * 1024) * 8))
1257 break;
1258
1259 tsbbase = __get_free_pages(GFP_DMA, order);
1260 if (!tsbbase) {
1261 prom_printf("PSYCHO_IOMMU: Error, gfp(tsb) failed.\n");
1262 prom_halt();
1263 }
1264 p->iommu.page_table = iopte = (iopte_t *)tsbbase;
1265 p->iommu.page_table_sz = (tsbsize * 1024);
1266
1267 /* Initialize to "none" settings. */
1268 for(i = 0; i < PCI_DVMA_HASHSZ; i++) {
1269 pci_dvma_v2p_hash[i] = PCI_DVMA_HASH_NONE;
1270 pci_dvma_p2v_hash[i] = PCI_DVMA_HASH_NONE;
1271 }
1272
1273 n = 0;
1274 mlist = *prom_meminfo()->p1275_totphys;
1275 while (mlist) {
1276 unsigned long paddr = mlist->start_adr;
1277 unsigned long num_bytes = mlist->num_bytes;
1278
1279 if(paddr >= (((unsigned long) high_memory) - PAGE_OFFSET))
1280 goto next;
1281
1282 if((paddr + num_bytes) >= (((unsigned long) high_memory) - PAGE_OFFSET))
1283 num_bytes = (((unsigned long) high_memory) - PAGE_OFFSET) - paddr;
1284
1285 /* Align base and length so we map whole hash table sized chunks
1286 * at a time (and therefore full 64K IOMMU pages).
1287 */
1288 paddr &= ~((1UL << 24UL) - 1);
1289 num_bytes = (num_bytes + ((1UL << 24UL) - 1)) & ~((1UL << 24) - 1);
1290
1291 /* Move up the base for mappings already created. */
1292 while(pci_dvma_v2p_hash[pci_dvma_ahashfn(paddr)] !=
1293 PCI_DVMA_HASH_NONE) {
1294 paddr += (1UL << 24UL);
1295 num_bytes -= (1UL << 24UL);
1296 if(num_bytes == 0UL)
1297 goto next;
1298 }
1299
1300 /* Move down the size for tail mappings already created. */
1301 while(pci_dvma_v2p_hash[pci_dvma_ahashfn(paddr + num_bytes - (1UL << 24UL))] !=
1302 PCI_DVMA_HASH_NONE) {
1303 num_bytes -= (1UL << 24UL);
1304 if(num_bytes == 0UL)
1305 goto next;
1306 }
1307
1308 /* Now map the rest. */
1309 for (i = 0; i < ((num_bytes + ((1 << 16) - 1)) >> 16); i++) {
1310 iopte_val(*iopte) = ((IOPTE_VALID | IOPTE_64K |
1311 IOPTE_CACHE | IOPTE_WRITE) |
1312 (paddr & IOPTE_PAGE));
1313
1314 if (!(n & 0xff))
1315 set_dvma_hash(0x80000000, paddr, (n << 16));
1316
1317 if (++n > (tsbsize * 1024))
1318 goto out;
1319
1320 paddr += (1 << 16);
1321 iopte++;
1322 }
1323 next:
1324 mlist = mlist->theres_more;
1325 }
1326 out:
1327 if (mlist) {
1328 prom_printf("WARNING: not all physical memory mapped in IOMMU\n");
1329 prom_printf("Try booting with mem=xxxM or similar\n");
1330 prom_halt();
1331 }
1332
1333 psycho_write(p->controller_regs + PSYCHO_IOMMU_TSBBASE, __pa(tsbbase));
1334
1335 control = psycho_read(p->controller_regs + PSYCHO_IOMMU_CONTROL);
1336 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ);
1337 control |= (PSYCHO_IOMMU_CTRL_TBWSZ | PSYCHO_IOMMU_CTRL_ENAB);
1338 switch(tsbsize) {
1339 case 8:
1340 p->iommu.page_table_map_base = 0xe0000000;
1341 control |= PSYCHO_IOMMU_TSBSZ_8K;
1342 break;
1343 case 16:
1344 p->iommu.page_table_map_base = 0xc0000000;
1345 control |= PSYCHO_IOMMU_TSBSZ_16K;
1346 break;
1347 case 32:
1348 p->iommu.page_table_map_base = 0x80000000;
1349 control |= PSYCHO_IOMMU_TSBSZ_32K;
1350 break;
1351 default:
1352 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
1353 prom_halt();
1354 break;
1355 }
1356 psycho_write(p->controller_regs + PSYCHO_IOMMU_CONTROL, control);
1357
1358 /* If necessary, hook us up for starfire IRQ translations. */
1359 if(this_is_starfire)
1360 p->starfire_cookie = starfire_hookup(p->portid);
1361 else
1362 p->starfire_cookie = NULL;
1363 }
1364
1365 #define PSYCHO_IRQ_RETRY 0x1a00UL
1366 #define PSYCHO_PCIA_DIAG 0x2020UL
1367 #define PSYCHO_PCIB_DIAG 0x4020UL
1368 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80 /* Reserved */
1369 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040 /* Disable retry limit */
1370 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020 /* Disable DMA wr / irq sync */
1371 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010 /* Disable DMA wr / PIO rd sync */
1372 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008 /* Invert DMA data parity */
1373 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004 /* Invert PIO data parity */
1374 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002 /* Invert PIO address parity */
1375 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001 /* Enable loopback mode */
1376
1377 static void psycho_controller_hwinit(struct pci_controller_info *p)
1378 {
1379 u64 tmp;
1380
1381 /* PROM sets the IRQ retry value too low, increase it. */
1382 psycho_write(p->controller_regs + PSYCHO_IRQ_RETRY, 0xff);
1383
1384 /* Enable arbiter for all PCI slots. */
1385 tmp = psycho_read(p->controller_regs + PSYCHO_PCIA_CTRL);
1386 tmp |= PSYCHO_PCICTRL_AEN;
1387 psycho_write(p->controller_regs + PSYCHO_PCIA_CTRL, tmp);
1388
1389 tmp = psycho_read(p->controller_regs + PSYCHO_PCIB_CTRL);
1390 tmp |= PSYCHO_PCICTRL_AEN;
1391 psycho_write(p->controller_regs + PSYCHO_PCIB_CTRL, tmp);
1392
1393 /* Disable DMA write / PIO read synchronization on
1394 * both PCI bus segments.
1395 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1396 */
1397 tmp = psycho_read(p->controller_regs + PSYCHO_PCIA_DIAG);
1398 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1399 psycho_write(p->controller_regs + PSYCHO_PCIA_DIAG, tmp);
1400
1401 tmp = psycho_read(p->controller_regs + PSYCHO_PCIB_DIAG);
1402 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1403 psycho_write(p->controller_regs + PSYCHO_PCIB_DIAG, tmp);
1404 }
1405
1406 static void __init pbm_register_toplevel_resources(struct pci_controller_info *p,
1407 struct pci_pbm_info *pbm)
1408 {
1409 char *name = pbm->name;
1410
1411 sprintf(name, "PSYCHO%d PBM%c",
1412 p->index,
1413 (pbm == &p->pbm_A ? 'A' : 'B'));
1414 pbm->io_space.name = pbm->mem_space.name = name;
1415
1416 request_resource(&ioport_resource, &pbm->io_space);
1417 request_resource(&iomem_resource, &pbm->mem_space);
1418 }
1419
1420 static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
1421 struct pci_pbm_info *pbm,
1422 int is_pbm_a)
1423 {
1424 unsigned long base = p->controller_regs;
1425
1426 /* Currently we don't even use it. */
1427 pbm->stc.strbuf_enabled = 0;
1428
1429 /* PSYCHO's streaming buffer lacks ctx flushing. */
1430 pbm->stc.strbuf_has_ctx_flush = 0;
1431
1432 if (is_pbm_a) {
1433 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1434 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1435 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1436 } else {
1437 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1438 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1439 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1440 }
1441 pbm->stc.strbuf_ctxflush = 0;
1442 pbm->stc.strbuf_ctxmatch_base = 0;
1443
1444 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1445 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1446 + 63UL)
1447 & ~63UL);
1448 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1449 __pa(pbm->stc.strbuf_flushflag);
1450
1451 #if 0
1452 /* And when we do enable it, these are the sorts of things
1453 * we'll do.
1454 */
1455 control = psycho_read(pbm->stc.strbuf_control);
1456 control |= PSYCHO_SBUFCTRL_SB_EN;
1457 psycho_write(pbm->stc.strbuf_control, control);
1458 #endif
1459 }
1460
1461 #define PSYCHO_IOSPACE_A 0x002000000UL
1462 #define PSYCHO_IOSPACE_B 0x002010000UL
1463 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1464 #define PSYCHO_MEMSPACE_A 0x100000000UL
1465 #define PSYCHO_MEMSPACE_B 0x180000000UL
1466 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1467
1468 static void psycho_pbm_init(struct pci_controller_info *p,
1469 int prom_node, int is_pbm_a)
1470 {
1471 unsigned int busrange[2];
1472 struct pci_pbm_info *pbm;
1473 int err;
1474
1475 if (is_pbm_a) {
1476 pbm = &p->pbm_A;
1477 pbm->io_space.start = p->controller_regs + PSYCHO_IOSPACE_A;
1478 pbm->mem_space.start = p->controller_regs + PSYCHO_MEMSPACE_A;
1479 } else {
1480 pbm = &p->pbm_B;
1481 pbm->io_space.start = p->controller_regs + PSYCHO_IOSPACE_B;
1482 pbm->mem_space.start = p->controller_regs + PSYCHO_MEMSPACE_B;
1483 }
1484 pbm->io_space.end = pbm->io_space.start + PSYCHO_IOSPACE_SIZE;
1485 pbm->io_space.flags = IORESOURCE_IO;
1486 pbm->mem_space.end = pbm->mem_space.start + PSYCHO_MEMSPACE_SIZE;
1487 pbm->mem_space.flags = IORESOURCE_MEM;
1488 pbm_register_toplevel_resources(p, pbm);
1489
1490 pbm->parent = p;
1491 pbm->prom_node = prom_node;
1492 prom_getstring(prom_node, "name",
1493 pbm->prom_name,
1494 sizeof(pbm->prom_name));
1495
1496 err = prom_getproperty(prom_node, "ranges",
1497 (char *)pbm->pbm_ranges,
1498 sizeof(pbm->pbm_ranges));
1499 if (err != -1)
1500 pbm->num_pbm_ranges =
1501 (err / sizeof(struct linux_prom_pci_ranges));
1502 else
1503 pbm->num_pbm_ranges = 0;
1504
1505 err = prom_getproperty(prom_node, "interrupt-map",
1506 (char *)pbm->pbm_intmap,
1507 sizeof(pbm->pbm_intmap));
1508 if (err != -1) {
1509 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1510 err = prom_getproperty(prom_node, "interrupt-map-mask",
1511 (char *)&pbm->pbm_intmask,
1512 sizeof(pbm->pbm_intmask));
1513 if (err == -1) {
1514 prom_printf("PSYCHO-PBM: Fatal error, no "
1515 "interrupt-map-mask.\n");
1516 prom_halt();
1517 }
1518 } else {
1519 pbm->num_pbm_intmap = 0;
1520 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1521 }
1522
1523 err = prom_getproperty(prom_node, "bus-range",
1524 (char *)&busrange[0],
1525 sizeof(busrange));
1526 if (err == 0 || err == -1) {
1527 prom_printf("PSYCHO-PBM: Fatal error, no bus-range.\n");
1528 prom_halt();
1529 }
1530 pbm->pci_first_busno = busrange[0];
1531 pbm->pci_last_busno = busrange[1];
1532
1533 psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
1534 }
1535
1536 #define PSYCHO_CONFIGSPACE 0x001000000UL
1537
1538 void __init psycho_init(int node)
1539 {
1540 struct linux_prom64_registers pr_regs[3];
1541 struct pci_controller_info *p;
1542 unsigned long flags;
1543 u32 upa_portid;
1544 int is_pbm_a, err;
1545
1546 upa_portid = prom_getintdefault(node, "upa-portid", 0xff);
1547
1548 spin_lock_irqsave(&pci_controller_lock, flags);
1549 for(p = pci_controller_root; p; p = p->next) {
1550 if (p->portid == upa_portid) {
1551 spin_unlock_irqrestore(&pci_controller_lock, flags);
1552 is_pbm_a = (p->pbm_A.prom_node == 0);
1553 psycho_pbm_init(p, node, is_pbm_a);
1554 return;
1555 }
1556 }
1557 spin_unlock_irqrestore(&pci_controller_lock, flags);
1558
1559 p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1560 if (!p) {
1561 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1562 prom_halt();
1563 }
1564 memset(p, 0, sizeof(*p));
1565
1566 spin_lock_irqsave(&pci_controller_lock, flags);
1567 p->next = pci_controller_root;
1568 pci_controller_root = p;
1569 spin_unlock_irqrestore(&pci_controller_lock, flags);
1570
1571 p->portid = upa_portid;
1572 p->index = pci_num_controllers++;
1573 p->scan_bus = psycho_scan_bus;
1574 p->irq_build = psycho_irq_build;
1575 p->base_address_update = psycho_base_address_update;
1576 p->resource_adjust = psycho_resource_adjust;
1577 p->pci_ops = &psycho_ops;
1578
1579 err = prom_getproperty(node, "reg",
1580 (char *)&pr_regs[0],
1581 sizeof(pr_regs));
1582 if (err == 0 || err == -1) {
1583 prom_printf("PSYCHO: Fatal error, no reg property.\n");
1584 prom_halt();
1585 }
1586
1587 p->controller_regs = pr_regs[2].phys_addr;
1588 printk("PCI: Found PSYCHO, control regs at %016lx\n",
1589 p->controller_regs);
1590
1591 p->config_space = pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE;
1592 printk("PSYCHO: PCI config space at %016lx\n", p->config_space);
1593
1594 /*
1595 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1596 * we need to adjust our MEM space mask.
1597 */
1598 pci_memspace_mask = 0x7fffffffUL;
1599
1600 psycho_controller_hwinit(p);
1601
1602 psycho_iommu_init(p, 32);
1603
1604 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1605 psycho_pbm_init(p, node, is_pbm_a);
1606 }
Copy of Dave Jones history.git as used by http://archive.org/details/git-history-of-linux