From 2a786e9e6ae905dc6eebf4357b83552b2448f1cc Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Tue, 1 May 2007 12:59:24 +0000 Subject: [PATCH] gas/config/ 2007-05-01 H.J. Lu * config/tc-i386.c (match_template): Check suffix for crc32 in Intel mdoe. (process_suffix): Default the suffix of 8bit crc32 to BYTE_MNEM_SUFFIX. (check_byte_reg): Skip check for 8bit crc32. gas/testsuite/ 2007-05-01 H.J. Lu * gas/i386/crc32-intel.d: New file. * gas/i386/crc32.d:Likewise. * gas/i386/crc32.s:Likewise. * gas/i386/x86-64-crc32-intel.d:Likewise. * gas/i386/x86-64-crc32.d:Likewise. * gas/i386/x86-64-crc32.s:Likewise. * gas/i386/i386.exp: Run crc32, crc32-intel, x86-64-crc32 and x86-64-crc32-intel. opcodes/ 2007-05-01 H.J. Lu * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and check data size prefix in 16bit mode. * i386-opc.c (i386_optab): Default crc32 to non-8bit and support Intel mode. --- gas/ChangeLog | 8 +++++ gas/config/tc-i386.c | 10 ++++++- gas/testsuite/ChangeLog | 12 ++++++++ gas/testsuite/gas/i386/crc32-intel.d | 32 ++++++++++++++++++++ gas/testsuite/gas/i386/crc32.d | 31 +++++++++++++++++++ gas/testsuite/gas/i386/crc32.s | 31 +++++++++++++++++++ gas/testsuite/gas/i386/i386.exp | 4 +++ gas/testsuite/gas/i386/x86-64-crc32-intel.d | 46 +++++++++++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-crc32.d | 45 ++++++++++++++++++++++++++++ gas/testsuite/gas/i386/x86-64-crc32.s | 45 ++++++++++++++++++++++++++++ opcodes/ChangeLog | 8 +++++ opcodes/i386-dis.c | 12 ++++---- opcodes/i386-opc.c | 6 ++-- 13 files changed, 280 insertions(+), 10 deletions(-) create mode 100644 gas/testsuite/gas/i386/crc32-intel.d create mode 100644 gas/testsuite/gas/i386/crc32.d create mode 100644 gas/testsuite/gas/i386/crc32.s create mode 100644 gas/testsuite/gas/i386/x86-64-crc32-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-crc32.d create mode 100644 gas/testsuite/gas/i386/x86-64-crc32.s diff --git a/gas/ChangeLog b/gas/ChangeLog index f0ebd660b..e5d9b84c4 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2007-05-01 H.J. Lu + + * config/tc-i386.c (match_template): Check suffix for crc32 in + Intel mdoe. + (process_suffix): Default the suffix of 8bit crc32 to + BYTE_MNEM_SUFFIX. + (check_byte_reg): Skip check for 8bit crc32. + 2007-04-30 H.J. Lu * config/tc-i386.c (md_assemble): Use register_prefix in diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index a0dd0ce13..e09132222 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2557,9 +2557,11 @@ match_template (void) if (i.operands != t->operands) continue; - /* Check the suffix, except for some instructions in intel mode. */ + /* Check the suffix, except for some instructions in intel mode. + We do want to check suffix for crc32 even in intel mode. */ if ((t->opcode_modifier & suffix_check) && !(intel_syntax + && t->base_opcode != 0xf20f38f1 && (t->opcode_modifier & IgnoreSize))) continue; @@ -2845,6 +2847,8 @@ process_suffix (void) i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX : LONG_MNEM_SUFFIX); } + else if (i.tm.base_opcode == 0xf20f38f0) + i.suffix = BYTE_MNEM_SUFFIX; if (!i.suffix) { @@ -3040,6 +3044,10 @@ check_byte_reg (void) || i.tm.base_opcode == 0xfbf)) continue; + /* crc32 doesn't generate this warning. */ + if (i.tm.base_opcode == 0xf20f38f0) + continue; + if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4) { /* Prohibit these changes in the 64bit mode, since the diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 0140f97ba..0148bfbf9 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,15 @@ +2007-05-01 H.J. Lu + + * gas/i386/crc32-intel.d: New file. + * gas/i386/crc32.d:Likewise. + * gas/i386/crc32.s:Likewise. + * gas/i386/x86-64-crc32-intel.d:Likewise. + * gas/i386/x86-64-crc32.d:Likewise. + * gas/i386/x86-64-crc32.s:Likewise. + + * gas/i386/i386.exp: Run crc32, crc32-intel, x86-64-crc32 + and x86-64-crc32-intel. + 2007-04-26 H.J. Lu PR binutils/4430 diff --git a/gas/testsuite/gas/i386/crc32-intel.d b/gas/testsuite/gas/i386/crc32-intel.d new file mode 100644 index 000000000..0a6a6432d --- /dev/null +++ b/gas/testsuite/gas/i386/crc32-intel.d @@ -0,0 +1,32 @@ +#objdump: -dwMintel +#name: i386 crc32 (Intel disassembly) +#source: crc32.s + +.*: +file format .* + +Disassembly of section .text: + +0+ : +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[esi\] +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[esi\] +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[esi\] +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax +#pass diff --git a/gas/testsuite/gas/i386/crc32.d b/gas/testsuite/gas/i386/crc32.d new file mode 100644 index 000000000..9dbfdca7d --- /dev/null +++ b/gas/testsuite/gas/i386/crc32.d @@ -0,0 +1,31 @@ +#objdump: -dw +#name: i386 crc32 + +.*: file format .* + +Disassembly of section .text: + +0+ : +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%esi\),%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%esi\),%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%esi\),%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +#pass diff --git a/gas/testsuite/gas/i386/crc32.s b/gas/testsuite/gas/i386/crc32.s new file mode 100644 index 000000000..711fe8ac0 --- /dev/null +++ b/gas/testsuite/gas/i386/crc32.s @@ -0,0 +1,31 @@ +# Check crc32 in SSE4.2 + + .text +foo: + +crc32b (%esi), %eax +crc32w (%esi), %eax +crc32l (%esi), %eax +crc32 (%esi), %eax +crc32 %al, %eax +crc32b %al, %eax +crc32 %ax, %eax +crc32w %ax, %eax +crc32 %eax, %eax +crc32l %eax, %eax + +.intel_syntax noprefix +crc32b eax,byte ptr [esi] +crc32 eax,byte ptr [esi] +crc32w eax, word ptr [esi] +crc32 eax, word ptr [esi] +crc32d eax,dword ptr [esi] +crc32 eax,dword ptr [esi] +crc32 eax,al +crc32b eax,al +crc32 eax, ax +crc32w eax, ax +crc32 eax,eax +crc32d eax,eax + +.p2align 4,0 diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index bda75bdaf..c65a6fc54 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -88,6 +88,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "addr32" run_dump_test "sse4_1" run_dump_test "sse4_2" + run_dump_test "crc32" + run_dump_test "crc32-intel" # These tests require support for 8 and 16 bit relocs, # so we only run them for ELF and COFF targets. @@ -177,6 +179,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-nops-1-merom" run_dump_test "x86-64-sse4_1" run_dump_test "x86-64-sse4_2" + run_dump_test "x86-64-crc32" + run_dump_test "x86-64-crc32-intel" if { ![istarget "*-*-aix*"] && ![istarget "*-*-beos*"] diff --git a/gas/testsuite/gas/i386/x86-64-crc32-intel.d b/gas/testsuite/gas/i386/x86-64-crc32-intel.d new file mode 100644 index 000000000..53c63d17f --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-crc32-intel.d @@ -0,0 +1,46 @@ +#objdump: -drwMintel +#name: x86-64 crc32 (Intel mode) +#source: x86-64-crc32.s + +.*: +file format .* + +Disassembly of section .text: + +0+ : +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[rsi\] +[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b rax,BYTE PTR \[rsi\] +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q rax,QWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b rax,al +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b rax,al +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q rax,rax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q rax,rax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b rax,BYTE PTR \[rsi\] +[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b rax,BYTE PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b eax,BYTE PTR \[rsi\] +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[rsi\] +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w eax,WORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32d eax,DWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q rax,QWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q rax,QWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b eax,al +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b rax,al +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b rax,al +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w eax,ax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32d eax,eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q rax,rax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q rax,rax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-crc32.d b/gas/testsuite/gas/i386/x86-64-crc32.d new file mode 100644 index 000000000..e6a955af6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-crc32.d @@ -0,0 +1,45 @@ +#objdump: -dw +#name: x86-64 crc32 + +.*: file format .* + +Disassembly of section .text: + +0+ : +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b \(%rsi\),%rax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q \(%rsi\),%rax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b \(%rsi\),%rax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b \(%rsi\),%rax +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%rsi\),%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%rsi\),%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q \(%rsi\),%rax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q \(%rsi\),%rax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-crc32.s b/gas/testsuite/gas/i386/x86-64-crc32.s new file mode 100644 index 000000000..069f7bab6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-crc32.s @@ -0,0 +1,45 @@ +# crc32 in SSE4.2 + + .text +foo: + +crc32b (%rsi), %eax +crc32b (%rsi), %rax +crc32w (%rsi), %eax +crc32l (%rsi), %eax +crc32q (%rsi), %rax +crc32 (%rsi), %eax +crc32 %al, %eax +crc32b %al, %eax +crc32 %al, %rax +crc32b %al, %rax +crc32 %ax, %eax +crc32w %ax, %eax +crc32 %eax, %eax +crc32l %eax, %eax +crc32 %rax, %rax +crc32q %rax, %rax + +.intel_syntax noprefix +crc32b rax,byte ptr [rsi] +crc32 rax,byte ptr [rsi] +crc32b eax,byte ptr [rsi] +crc32 eax,byte ptr [rsi] +crc32w eax, word ptr [rsi] +crc32 eax, word ptr [rsi] +crc32d eax,dword ptr [rsi] +crc32 eax,dword ptr [rsi] +crc32q rax,qword ptr [rsi] +crc32 rax,qword ptr [rsi] +crc32 eax,al +crc32b eax,al +crc32 rax,al +crc32b rax,al +crc32 eax, ax +crc32w eax, ax +crc32 eax,eax +crc32d eax,eax +crc32 rax,rax +crc32q rax,rax + +.p2align 4,0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e751f9f94..afdba1370 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2007-05-01 H.J. Lu + + * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and + check data size prefix in 16bit mode. + + * i386-opc.c (i386_optab): Default crc32 to non-8bit and + support Intel mode. + 2007-04-30 Mark Salter * frv-desc.c: Regenerate. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index aebb71e55..2f26e0619 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -6390,13 +6390,11 @@ CRC32_Fixup (int bytemode, int sizeflag) USED_REX (REX_W); if (rex & REX_W) *p++ = 'q'; - else if ((prefixes & PREFIX_DATA)) - { - *p++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); - } + else if (sizeflag & DFLAG) + *p++ = intel_syntax ? 'd' : 'l'; else - *p++ = 'l'; + *p++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); break; default: oappend (INTERNAL_DISASSEMBLER_ERROR); @@ -6434,5 +6432,5 @@ CRC32_Fixup (int bytemode, int sizeflag) } } else - OP_E (v_mode, sizeflag); + OP_E (bytemode, sizeflag); } diff --git a/opcodes/i386-opc.c b/opcodes/i386-opc.c index a374b654e..e03152cca 100644 --- a/opcodes/i386-opc.c +++ b/opcodes/i386-opc.c @@ -1442,10 +1442,12 @@ const template i386_optab[] = {"pcmpestrm", 3, 0x660f3a60,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, {"pcmpistri", 3, 0x660f3a63,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, {"pcmpistrm", 3, 0x660f3a62,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"crc32b", 2, 0xf20f38f0,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Reg8|ByteMem, Reg32|Reg64, 0 } }, -{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Reg8, Reg32|Reg64, 0 } }, +/* We put non-8bit version before 8bit so that crc32 with memory operand + defaults to non-8bit. */ {"crc32", 2, 0xf20f38f1,X, CpuSSE4_2, wl_Suf|Modrm, { WordReg|WordMem, Reg32, 0 } }, {"crc32", 2, 0xf20f38f1,X, CpuSSE4_2|Cpu64, q_Suf|IgnoreSize|Modrm|Rex64, { Reg64|LLongMem, Reg64, 0 } }, +{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2, b_Suf|Modrm, { Reg8|ByteMem, Reg32, 0 } }, +{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2|Cpu64, b_Suf|IgnoreSize|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0 } }, /* AMD 3DNow! instructions. */ -- 2.11.4.GIT