From c992347469253cfda59c3057763f20b26d89818b Mon Sep 17 00:00:00 2001 From: Mustafa Sakarya Date: Sat, 26 Jun 2010 15:58:53 +0300 Subject: [PATCH] simple-FreeRTOS-demo application is created FreeRTOS' ARM7_LPC2106_GCC port is modified to work in lpc2138 --- simple-FreeRTOS-demo/FreeRTOSConfig.h | 102 +++++++ simple-FreeRTOS-demo/LPC2000.h | 42 +++ simple-FreeRTOS-demo/LPC214x.h | 399 +++++++++++++++++++++++++ simple-FreeRTOS-demo/Makefile | 144 ++++++++++ simple-FreeRTOS-demo/ParTest/ParTest.c | 127 ++++++++ simple-FreeRTOS-demo/boot.s | 157 ++++++++++ simple-FreeRTOS-demo/lpc2138-ram.ld | 64 +++++ simple-FreeRTOS-demo/lpc2138-rom.ld | 64 +++++ simple-FreeRTOS-demo/main.c | 496 ++++++++++++++++++++++++++++++++ simple-FreeRTOS-demo/serial/serial.c | 284 ++++++++++++++++++ simple-FreeRTOS-demo/serial/serialISR.c | 192 +++++++++++++ 11 files changed, 2071 insertions(+) create mode 100644 simple-FreeRTOS-demo/FreeRTOSConfig.h create mode 100644 simple-FreeRTOS-demo/LPC2000.h create mode 100644 simple-FreeRTOS-demo/LPC214x.h create mode 100644 simple-FreeRTOS-demo/Makefile create mode 100644 simple-FreeRTOS-demo/ParTest/ParTest.c create mode 100644 simple-FreeRTOS-demo/boot.s create mode 100644 simple-FreeRTOS-demo/lpc2138-ram.ld create mode 100644 simple-FreeRTOS-demo/lpc2138-rom.ld create mode 100644 simple-FreeRTOS-demo/main.c create mode 100644 simple-FreeRTOS-demo/serial/serial.c create mode 100644 simple-FreeRTOS-demo/serial/serialISR.c diff --git a/simple-FreeRTOS-demo/FreeRTOSConfig.h b/simple-FreeRTOS-demo/FreeRTOSConfig.h new file mode 100644 index 0000000..7af0764 --- /dev/null +++ b/simple-FreeRTOS-demo/FreeRTOSConfig.h @@ -0,0 +1,102 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( ( unsigned long ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */ +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 23 * 1024 ) ) /* 24 */ +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configQUEUE_REGISTRY_SIZE 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/simple-FreeRTOS-demo/LPC2000.h b/simple-FreeRTOS-demo/LPC2000.h new file mode 100644 index 0000000..5ab8729 --- /dev/null +++ b/simple-FreeRTOS-demo/LPC2000.h @@ -0,0 +1,42 @@ +#ifndef LPC2000_h_ +#define LPC2000_h_ + +#include "LPC214x.h" + +/* + convert "official" Philips definitions to definitions + used in FreeRTOS +*/ +#define T0_IR T0IR +#define T0_PR T0PR +#define T0_MR0 T0MR0 +#define T0_MCR T0MCR +#define T0_TCR T0TCR + +#define UART0_IIR U0IIR +#define UART0_LSR U0LSR +#define UART0_THR U0THR +#define UART0_RBR U0RBR +#define UART0_LCR U0LCR +#define UART0_DLL U0DLL +#define UART0_DLM U0DLM +#define UART0_FCR U0FCR +#define UART0_IER U0IER + +#define PCB_PINSEL0 PINSEL0 + +#define SCB_PLLCFG PLLCFG +#define SCB_PLLCON PLLCON +#define SCB_PLLFEED PLLFEED +#define SCB_PLLSTAT PLLSTAT +#define SCB_VPBDIV VPBDIV + +#define MAM_TIM MAMTIM +#define MAM_CR MAMCR + +#define GPIO0_IOPIN IOPIN0 +#define GPIO_IOSET IOSET0 +#define GPIO_IOCLR IOCLR0 +#define GPIO_IODIR IODIR0 + +#endif diff --git a/simple-FreeRTOS-demo/LPC214x.h b/simple-FreeRTOS-demo/LPC214x.h new file mode 100644 index 0000000..b648a45 --- /dev/null +++ b/simple-FreeRTOS-demo/LPC214x.h @@ -0,0 +1,399 @@ +/****************************************************************************** + * LPC214X.h: Header file for Philips LPC214x Family Microprocessors + * The header file is the super set of all hardware definition of the + * peripherals for the LPC214x family microprocessor. + * + * Copyright(C) 2006, Philips Semiconductor + * All rights reserved. + + * History + * 2005.10.01 ver 1.00 Prelimnary version, first Release + * 2005.10.13 ver 1.01 Removed CSPR and DC_REVISION register. + * CSPR can not be accessed at the user level, + * DC_REVISION is no long available. + * All registers use "volatile unsigned long". +******************************************************************************/ + +#ifndef __LPC214x_H +#define __LPC214x_H + +/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 + +#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) +#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) +#define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x030)) +#define VICDefVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x034)) +#define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100)) +#define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104)) +#define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108)) +#define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C)) +#define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110)) +#define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114)) +#define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118)) +#define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C)) +#define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120)) +#define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124)) +#define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128)) +#define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C)) +#define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130)) +#define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134)) +#define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138)) +#define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C)) +#define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200)) +#define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204)) +#define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208)) +#define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C)) +#define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210)) +#define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214)) +#define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218)) +#define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C)) +#define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220)) +#define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224)) +#define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228)) +#define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C)) +#define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230)) +#define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234)) +#define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238)) +#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C)) + +/* Pin Connect Block */ +#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) +#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) +#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14)) + +/* General Purpose Input/Output (GPIO) */ +#define GPIO_BASE_ADDR 0xE0028000 +#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) +#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) +#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) +#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C)) +#define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10)) +#define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14)) +#define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18)) +#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) + +/* Fast I/O setup */ +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) +#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) +#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) +#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) +#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) +#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) +#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) +#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) +#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) + +/* System Control Block(SCB) modules include Memory Accelerator Module, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Reset, and Code Security/Debugging */ + +#define SCB_BASE_ADDR 0xE01FC000 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) +#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004)) +#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080)) +#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084)) +#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088)) +#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C)) + +/* PLL48 Registers */ +#define PLL48CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A0)) +#define PLL48CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A4)) +#define PLL48STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A8)) +#define PLL48FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0AC)) + +/* Power Control */ +#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0)) +#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4)) + +/* VPB Divider */ +#define VPBDIV (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100)) + +/* External Interrupts */ +#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) +#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) +#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148)) +#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C)) + +/* Reset */ +#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180)) + +/* System Controls and Status */ +#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) + +/* Timer 0 */ +#define TMR0_BASE_ADDR 0xE0004000 +#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) +#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) +#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) +#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C)) +#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10)) +#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14)) +#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18)) +#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C)) +#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20)) +#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24)) +#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28)) +#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C)) +#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30)) +#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34)) +#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38)) +#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C)) +#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) + +/* Timer 1 */ +#define TMR1_BASE_ADDR 0xE0008000 +#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) +#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) +#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) +#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C)) +#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10)) +#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14)) +#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18)) +#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C)) +#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20)) +#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24)) +#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28)) +#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C)) +#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30)) +#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34)) +#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38)) +#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C)) +#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) + +/* Pulse Width Modulator (PWM) */ +#define PWM_BASE_ADDR 0xE0014000 +#define PWMIR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x00)) +#define PWMTCR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x04)) +#define PWMTC (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x08)) +#define PWMPR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x0C)) +#define PWMPC (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x10)) +#define PWMMCR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x14)) +#define PWMMR0 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x18)) +#define PWMMR1 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x1C)) +#define PWMMR2 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x20)) +#define PWMMR3 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x24)) +#define PWMMR4 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x40)) +#define PWMMR5 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x44)) +#define PWMMR6 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x48)) +#define PWMEMR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x3C)) +#define PWMPCR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x4C)) +#define PWMLER (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x50)) + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define UART0_BASE_ADDR 0xE000C000 +#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) +#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) +#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) +#define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) +#define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C)) +#define U0MCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x10)) +#define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14)) +#define U0MSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x18)) +#define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C)) +#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20)) +#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28)) +#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define UART1_BASE_ADDR 0xE0010000 +#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) +#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) +#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) +#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) +#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C)) +#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10)) +#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14)) +#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18)) +#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C)) +#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20)) +#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28)) +#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) + +/* I2C Interface 0 */ +#define I2C0_BASE_ADDR 0xE001C000 +#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) +#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) +#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) +#define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C)) +#define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10)) +#define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14)) +#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) + +/* I2C Interface 1 */ +#define I2C1_BASE_ADDR 0xE005C000 +#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) +#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) +#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) +#define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C)) +#define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10)) +#define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14)) +#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) +#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) +#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) +#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C)) +#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) + +/* SSP Controller */ +#define SSP_BASE_ADDR 0xE0068000 +#define SSPCR0 (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x00)) +#define SSPCR1 (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x04)) +#define SSPDR (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x08)) +#define SSPSR (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x0C)) +#define SSPCPSR (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x10)) +#define SSPIMSC (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x14)) +#define SSPRIS (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x18)) +#define SSPMIS (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x1C)) +#define SSPICR (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x20)) + +/* Real Time Clock */ +#define RTC_BASE_ADDR 0xE0024000 +#define ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) +#define CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) +#define CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) +#define CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C)) +#define AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10)) +#define CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14)) +#define CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18)) +#define CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C)) +#define SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20)) +#define MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24)) +#define HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28)) +#define DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C)) +#define DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30)) +#define DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34)) +#define MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38)) +#define YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C)) +#define ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60)) +#define ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64)) +#define ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68)) +#define ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C)) +#define ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70)) +#define ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74)) +#define ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78)) +#define ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C)) +#define PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80)) +#define PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84)) + +/* A/D Converter 0 (AD0) */ +#define AD0_BASE_ADDR 0xE0034000 +#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) +#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) +#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30)) +#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) +#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10)) +#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14)) +#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18)) +#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C)) +#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20)) +#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24)) +#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28)) +#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C)) + +#define ADGSR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x08)) +/* A/D Converter 1 (AD1) */ +#define AD1_BASE_ADDR 0xE0060000 +#define AD1CR (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x00)) +#define AD1GDR (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x04)) +#define AD1STAT (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x30)) +#define AD1INTEN (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x0C)) +#define AD1DR0 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x10)) +#define AD1DR1 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x14)) +#define AD1DR2 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x18)) +#define AD1DR3 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x1C)) +#define AD1DR4 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x20)) +#define AD1DR5 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x24)) +#define AD1DR6 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x28)) +#define AD1DR7 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x2C)) + +/* D/A Converter */ +#define DAC_BASE_ADDR 0xE006C000 +#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) + +/* Watchdog */ +#define WDG_BASE_ADDR 0xE0000000 +#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) +#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) +#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) +#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C)) + +/* USB Controller */ +#define USB_BASE_ADDR 0xE0090000 /* USB Base Address */ +/* Device Interrupt Registers */ +#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00)) +#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04)) +#define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08)) +#define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C)) +#define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C)) + +/* Endpoint Interrupt Registers */ +#define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30)) +#define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34)) +#define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38)) +#define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C)) +#define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40)) + +/* Endpoint Realization Registers */ +#define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44)) +#define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48)) +#define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C)) + +/* Command Reagisters */ +#define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10)) +#define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14)) + +/* Data Transfer Registers */ +#define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18)) +#define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C)) +#define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20)) +#define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24)) +#define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28)) + +/* DMA Registers */ +#define DMA_REQ_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0x50)) +#define DMA_REQ_CLR (*((volatile unsigned long *)USB_BASE_ADDR + 0x54)) +#define DMA_REQ_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0x58)) +#define UDCA_HEAD (*((volatile unsigned long *)USB_BASE_ADDR + 0x80)) +#define EP_DMA_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0x84)) +#define EP_DMA_EN (*((volatile unsigned long *)USB_BASE_ADDR + 0x88)) +#define EP_DMA_DIS (*((volatile unsigned long *)USB_BASE_ADDR + 0x8C)) +#define DMA_INT_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0x90)) +#define DMA_INT_EN (*((volatile unsigned long *)USB_BASE_ADDR + 0x94)) +#define EOT_INT_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0xA0)) +#define EOT_INT_CLR (*((volatile unsigned long *)USB_BASE_ADDR + 0xA4)) +#define EOT_INT_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0xA8)) +#define NDD_REQ_INT_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0xAC)) +#define NDD_REQ_INT_CLR (*((volatile unsigned long *)USB_BASE_ADDR + 0xB0)) +#define NDD_REQ_INT_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0xB4)) +#define SYS_ERR_INT_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0xB8)) +#define SYS_ERR_INT_CLR (*((volatile unsigned long *)USB_BASE_ADDR + 0xBC)) +#define SYS_ERR_INT_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0xC0)) +#define MODULE_ID (*((volatile unsigned long *)USB_BASE_ADDR + 0xFC)) + +#endif // __LPC214x_H + diff --git a/simple-FreeRTOS-demo/Makefile b/simple-FreeRTOS-demo/Makefile new file mode 100644 index 0000000..3ce77c2 --- /dev/null +++ b/simple-FreeRTOS-demo/Makefile @@ -0,0 +1,144 @@ +#/* +# FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. +# +# *************************************************************************** +# * * +# * If you are: * +# * * +# * + New to FreeRTOS, * +# * + Wanting to learn FreeRTOS or multitasking in general quickly * +# * + Looking for basic training, * +# * + Wanting to improve your FreeRTOS skills and productivity * +# * * +# * then take a look at the FreeRTOS eBook * +# * * +# * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * +# * http://www.FreeRTOS.org/Documentation * +# * * +# * A pdf reference manual is also available. Both are usually delivered * +# * to your inbox within 20 minutes to two hours when purchased between 8am * +# * and 8pm GMT (although please allow up to 24 hours in case of * +# * exceptional circumstances). Thank you for your support! * +# * * +# *************************************************************************** +# +# This file is part of the FreeRTOS distribution. +# +# FreeRTOS is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License (version 2) as published by the +# Free Software Foundation AND MODIFIED BY the FreeRTOS exception. +# ***NOTE*** The exception to the GPL is included to allow you to distribute +# a combined work that includes FreeRTOS without being obliged to provide the +# source code for proprietary components outside of the FreeRTOS kernel. +# FreeRTOS is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. You should have received a copy of the GNU General Public +# License and the FreeRTOS license exception along with FreeRTOS; if not it +# can be viewed here: http://www.freertos.org/a00114.html and also obtained +# by writing to Richard Barry, contact details for whom are available on the +# FreeRTOS WEB site. +# +# 1 tab == 4 spaces! +# +# http://www.FreeRTOS.org - Documentation, latest information, license and +# contact details. +# +# http://www.SafeRTOS.com - A version that is certified for use in safety +# critical systems. +# +# http://www.OpenRTOS.com - Commercial support, development, porting, +# licensing and training services. +#*/ + +USE_THUMB_MODE=NO +DEBUG= +OPTIM=-O3 +RUN_MODE=RUN_FROM_ROM +LDSCRIPT=lpc2138-rom.ld + +CC=arm-elf-gcc +OBJCOPY=arm-elf-objcopy +ARCH=arm-elf-ar +CRT0=boot.s +WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \ + -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused + +# +# CFLAGS common to both the THUMB and ARM mode builds +# +CFLAGS=$(WARNINGS) -D $(RUN_MODE) -D GCC_ARM7 -I. -I ../FreeRTOS/Source/include \ + -I ../FreeRTOS/Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \ + $(OPTIM) -fomit-frame-pointer -fno-strict-aliasing #-fno-dwarf2-cfi-asm + +ifeq ($(USE_THUMB_MODE),YES) + CFLAGS += -mthumb-interwork -D THUMB_INTERWORK + THUMB_FLAGS=-mthumb +endif + + +LINKER_FLAGS=-Xlinker -ooutput.elf -Xlinker -M -Xlinker -Map=output.map + +RTOS_SOURCE_DIR=../FreeRTOS/Source +DEMO_SOURCE_DIR=../FreeRTOS/Common/Minimal +# +# Source files that can be built to THUMB mode. +# +THUMB_SRC = \ +main.c \ +serial/serial.c \ +ParTest/ParTest.c \ +$(DEMO_SOURCE_DIR)/integer.c \ +$(DEMO_SOURCE_DIR)/flash.c \ +$(DEMO_SOURCE_DIR)/PollQ.c \ +$(DEMO_SOURCE_DIR)/comtest.c \ +$(DEMO_SOURCE_DIR)/flop.c \ +$(DEMO_SOURCE_DIR)/semtest.c \ +$(DEMO_SOURCE_DIR)/dynamic.c \ +$(DEMO_SOURCE_DIR)/BlockQ.c \ +$(RTOS_SOURCE_DIR)/tasks.c \ +$(RTOS_SOURCE_DIR)/queue.c \ +$(RTOS_SOURCE_DIR)/list.c \ +$(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c \ +$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/port.c + +# +# Source files that must be built to ARM mode. +# +ARM_SRC = \ +$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/portISR.c \ +serial/serialISR.c + +# +# Define all object files. +# +ARM_OBJ = $(ARM_SRC:.c=.o) +THUMB_OBJ = $(THUMB_SRC:.c=.o) + +output.hex : output.elf + $(OBJCOPY) output.elf -O ihex output.hex + +output.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile + $(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS) + +$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@ + +$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile + $(CC) -c $(CFLAGS) $< -o $@ + +clean : + rm -rf $(ARM_OBJ) $(THUMB_OBJ) output.* + touch Makefile + + + + + + + + + + + + diff --git a/simple-FreeRTOS-demo/ParTest/ParTest.c b/simple-FreeRTOS-demo/ParTest/ParTest.c new file mode 100644 index 0000000..246ea71 --- /dev/null +++ b/simple-FreeRTOS-demo/ParTest/ParTest.c @@ -0,0 +1,127 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + Changes from V2.5.2 + + + All LED's are turned off to start. +*/ + + +#include "FreeRTOS.h" +#include "partest.h" + +#define partstFIRST_IO ( ( unsigned long ) 0x400 ) +#define partstNUM_LEDS ( 4 ) +#define partstALL_OUTPUTS_OFF ( ( unsigned long ) 0xffffffff ) + +/*----------------------------------------------------------- + * Simple parallel port IO routines. + *-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* This is performed from main() as the io bits are shared with other setup + functions. */ + + /* Turn all outputs off. */ + GPIO_IOSET = partstALL_OUTPUTS_OFF; +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned long ulLED = partstFIRST_IO; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned long ) uxLED; + + /* Set of clear the output. */ + if( xValue ) + { + GPIO_IOCLR = ulLED; + } + else + { + GPIO_IOSET = ulLED; + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned long ulLED = partstFIRST_IO, ulCurrentState; + + if( uxLED < partstNUM_LEDS ) + { + /* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED + attached. */ + ulLED <<= ( unsigned long ) uxLED; + + /* If this bit is already set, clear it, and visa versa. */ + ulCurrentState = GPIO0_IOPIN; + if( ulCurrentState & ulLED ) + { + GPIO_IOCLR = ulLED; + } + else + { + GPIO_IOSET = ulLED; + } + } +} + diff --git a/simple-FreeRTOS-demo/boot.s b/simple-FreeRTOS-demo/boot.s new file mode 100644 index 0000000..480c8e4 --- /dev/null +++ b/simple-FreeRTOS-demo/boot.s @@ -0,0 +1,157 @@ + /* Sample initialization file */ + + .extern main + .extern exit + + .text + .code 32 + + + .align 0 + + .extern __bss_beg__ + .extern __bss_end__ + .extern __stack_end__ + .extern __data_beg__ + .extern __data_end__ + .extern __data+beg_src__ + + .global start + .global endless_loop + + /* Stack Sizes */ + .set UND_STACK_SIZE, 0x00000004 + .set ABT_STACK_SIZE, 0x00000004 + .set FIQ_STACK_SIZE, 0x00000004 + .set IRQ_STACK_SIZE, 0X00000400 + .set SVC_STACK_SIZE, 0x00000400 + + /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + .set MODE_USR, 0x10 /* User Mode */ + .set MODE_FIQ, 0x11 /* FIQ Mode */ + .set MODE_IRQ, 0x12 /* IRQ Mode */ + .set MODE_SVC, 0x13 /* Supervisor Mode */ + .set MODE_ABT, 0x17 /* Abort Mode */ + .set MODE_UND, 0x1B /* Undefined Mode */ + .set MODE_SYS, 0x1F /* System Mode */ + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + +start: +_start: +_mainCRTStartup: + + /* Setup a stack for each mode - note that this only sets up a usable stack + for system/user, SWI and IRQ modes. Also each mode is setup with + interrupts initially disabled. */ + ldr r0, .LC6 + msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ + mov sp, r0 + sub r0, r0, #UND_STACK_SIZE + msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ + mov sp, r0 + sub r0, r0, #ABT_STACK_SIZE + msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ + mov sp, r0 + sub r0, r0, #FIQ_STACK_SIZE + msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ + mov sp, r0 + sub r0, r0, #IRQ_STACK_SIZE + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ + mov sp, r0 + sub r0, r0, #SVC_STACK_SIZE + msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */ + mov sp, r0 + + /* We want to start in supervisor mode. Operation will switch to system + mode when the first task starts. */ + msr CPSR_c, #MODE_SVC|I_BIT|F_BIT + + /* Clear BSS. */ + + mov a2, #0 /* Fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr r1, .LC1 /* Start of memory block */ + ldr r3, .LC2 /* End of memory block */ + subs r3, r3, r1 /* Length of block */ + beq .end_clear_loop + mov r2, #0 + +.clear_loop: + strb r2, [r1], #1 + subs r3, r3, #1 + bgt .clear_loop + +.end_clear_loop: + + /* Initialise data. */ + + ldr r1, .LC3 /* Start of memory block */ + ldr r2, .LC4 /* End of memory block */ + ldr r3, .LC5 + subs r3, r3, r1 /* Length of block */ + beq .end_set_loop + +.set_loop: + ldrb r4, [r2], #1 + strb r4, [r1], #1 + subs r3, r3, #1 + bgt .set_loop + +.end_set_loop: + + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ + + bl main + +endless_loop: + b endless_loop + + + .align 0 + + .LC1: + .word __bss_beg__ + .LC2: + .word __bss_end__ + .LC3: + .word __data_beg__ + .LC4: + .word __data_beg_src__ + .LC5: + .word __data_end__ + .LC6: + .word __stack_end__ + + + /* Setup vector table. Note that undf, pabt, dabt, fiq just execute + a null loop. */ + +.section .startup,"ax" + .code 32 + .align 0 + + b _start /* reset - _start */ + ldr pc, _undf /* undefined - _undf */ + ldr pc, _swi /* SWI - _swi */ + ldr pc, _pabt /* program abort - _pabt */ + ldr pc, _dabt /* data abort - _dabt */ + nop /* reserved */ + ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */ + ldr pc, _fiq /* FIQ - _fiq */ + +_undf: .word __undf /* undefined */ +_swi: .word vPortYieldProcessor /* SWI */ +_pabt: .word __pabt /* program abort */ +_dabt: .word __dabt /* data abort */ +_fiq: .word __fiq /* FIQ */ + +__undf: b . /* undefined */ +__pabt: b . /* program abort */ +__dabt: b . /* data abort */ +__fiq: b . /* FIQ */ diff --git a/simple-FreeRTOS-demo/lpc2138-ram.ld b/simple-FreeRTOS-demo/lpc2138-ram.ld new file mode 100644 index 0000000..a774831 --- /dev/null +++ b/simple-FreeRTOS-demo/lpc2138-ram.ld @@ -0,0 +1,64 @@ +/* +MEMORY +{ + flash : ORIGIN = 0, LENGTH = 120K + ram : ORIGIN = 0x40000000, LENGTH = 64K +} + +__stack_end__ = 0x40000000 + 64K - 4; +*/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 500k + ram (rw) : ORIGIN = 0x40000000, LENGTH = 32k +} +__stack_end__ = ORIGIN(ram) + LENGTH(ram) -4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >ram + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >ram + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + . = ALIGN(4); + .eh_frame : + { + KEEP (*(.eh_frame)) + } > ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/simple-FreeRTOS-demo/lpc2138-rom.ld b/simple-FreeRTOS-demo/lpc2138-rom.ld new file mode 100644 index 0000000..aa5f26b --- /dev/null +++ b/simple-FreeRTOS-demo/lpc2138-rom.ld @@ -0,0 +1,64 @@ +/* +MEMORY +{ + flash : ORIGIN = 0, LENGTH = 120K + ram : ORIGIN = 0x40000000, LENGTH = 64K +} + +__stack_end__ = 0x40000000 + 64K - 4; +*/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 500k + ram (rw) : ORIGIN = 0x40000000, LENGTH = 32k +} +__stack_end__ = ORIGIN(ram) + LENGTH(ram) -4; + +SECTIONS +{ + . = 0; + startup : { *(.startup)} >flash + + prog : + { + *(.text) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } >flash + + __end_of_text__ = .; + + .data : + { + __data_beg__ = .; + __data_beg_src__ = __end_of_text__; + *(.data) + __data_end__ = .; + } >ram AT>flash + + .bss : + { + __bss_beg__ = .; + *(.bss) + } >ram + + . = ALIGN(4); + .eh_frame : + { + KEEP (*(.eh_frame)) + } > ram + + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); +} + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + + diff --git a/simple-FreeRTOS-demo/main.c b/simple-FreeRTOS-demo/main.c new file mode 100644 index 0000000..fb24447 --- /dev/null +++ b/simple-FreeRTOS-demo/main.c @@ -0,0 +1,496 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used. +*/ + + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * Main.c also creates a task called "Check". This only executes every three + * seconds but has the highest priority so is guaranteed to get processor time. + * Its main function is to check that all the other tasks are still operational. + * Each task (other than the "flash" tasks) maintains a unique count that is + * incremented each time the task successfully completes its function. Should + * any error occur within such a task the count is permanently halted. The + * check task inspects the count of each task to ensure it has changed since + * the last time the check task executed. If all the count variables have + * changed all the tasks are still executing error free, and the check task + * toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * To check the operation of the memory allocator the check task also + * dynamically creates a task before delaying, and deletes it again when it + * wakes. If memory cannot be allocated for the new task the call to xTaskCreate + * will fail and an error is signalled. The dynamically created task itself + * allocates and frees memory just to give the allocator a bit more exercise. + * + */ + +/* + Changes from V2.4.2 + + + The vErrorChecks() task now dynamically creates then deletes a task each + cycle. This tests the operation of the memory allocator. + + Changes from V2.5.2 + + + vParTestInitialise() is called during initialisation to ensure all the + LED's start off. +*/ + + +/* Standard includes. */ +#include +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo application includes. */ +#include "partest.h" +#include "flash.h" +#include "integer.h" +#include "PollQ.h" +#include "comtest2.h" +#include "semtest.h" +#include "flop.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup I/O. */ +#define mainTX_ENABLE ( ( unsigned long ) 0x0001 ) +#define mainRX_ENABLE ( ( unsigned long ) 0x0004 ) +#define mainP0_14 ( ( unsigned long ) 0x4000 ) +#define mainJTAG_PORT ( ( unsigned long ) 0x3E0000UL ) + +/* Constants to setup the PLL. */ +#define mainPLL_MUL_4 ( ( unsigned char ) 0x0003 ) +#define mainPLL_DIV_1 ( ( unsigned char ) 0x0000 ) +#define mainPLL_ENABLE ( ( unsigned char ) 0x0001 ) +#define mainPLL_CONNECT ( ( unsigned char ) 0x0003 ) +#define mainPLL_FEED_BYTE1 ( ( unsigned char ) 0xaa ) +#define mainPLL_FEED_BYTE2 ( ( unsigned char ) 0x55 ) +#define mainPLL_LOCK ( ( unsigned long ) 0x0400 ) + +/* Constants to setup the MAM. */ +#define mainMAM_TIM_3 ( ( unsigned char ) 0x03 ) +#define mainMAM_MODE_FULL ( ( unsigned char ) 0x02 ) + +/* Constants to setup the peripheral bus. */ +#define mainBUS_CLK_FULL ( ( unsigned char ) 0x01 ) + +/* Constants for the ComTest tasks. */ +#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 115200 ) +#define mainCOM_TEST_LED ( 3 ) + +/* Priorities for the demo application tasks. */ +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 0 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/* The rate at which the on board LED will toggle when there is/is not an +error. */ +#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS ) +#define mainON_BOARD_LED_BIT ( ( unsigned long ) 0x80 ) + +/* Constants used by the vMemCheckTask() task. */ +#define mainCOUNT_INITIAL_VALUE ( ( unsigned long ) 0 ) +#define mainNO_TASK ( 0 ) + +/* The size of the memory blocks allocated by the vMemCheckTask() task. */ +#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 ) +#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 ) +#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 ) + +/*-----------------------------------------------------------*/ + +/* + * The Olimex demo board has a single built in LED. This function simply + * toggles its state. + */ +void prvToggleOnBoardLED( void ); + +/* + * Checks that all the demo application tasks are still executing without error + * - as described at the top of the file. + */ +static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount ); + +/* + * The task that executes at the highest priority and calls + * prvCheckOtherTasksAreStillRunning(). See the description at the top + * of the file. + */ +static void vErrorChecks( void *pvParameters ); + +/* + * Dynamically created and deleted during each cycle of the vErrorChecks() + * task. This is done to check the operation of the memory allocator. + * See the top of vErrorChecks for more details. + */ +static void vMemCheckTask( void *pvParameters ); + +/* + * Configure the processor for use with the Olimex demo board. This includes + * setup for the I/O, system clock, and access timings. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* + * Starts all the other tasks, then starts the scheduler. + */ +int main( void ) +{ + /* Setup the hardware for use with the Olimex demo board. */ + prvSetupHardware(); + + /* Start the demo/test application tasks. */ + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED ); + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); + vStartMathTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + + /* Start the check task - which is defined in this file. */ + xTaskCreate( vErrorChecks, ( signed char * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Now all the tasks have been started - start the scheduler. + + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. + The processor MUST be in supervisor mode when vTaskStartScheduler is + called. The demo applications included in the FreeRTOS.org download switch + to supervisor mode prior to main being called. If you are not using one of + these demo application projects then ensure Supervisor mode is used here. */ + vTaskStartScheduler(); + + /* Should never reach here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void vErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD; +unsigned long ulMemCheckTaskRunningCount; +xTaskHandle xCreatedTask; + + /* The parameters are not used in this function. */ + ( void ) pvParameters; + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. If an error is detected then the delay period + is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so + the on board LED flash rate will increase. + + In addition to the standard tests the memory allocator is tested through + the dynamic creation and deletion of a task each cycle. Each time the + task is created memory must be allocated for its stack. When the task is + deleted this memory is returned to the heap. If the task cannot be created + then it is likely that the memory allocation failed. */ + + for( ;; ) + { + /* Dynamically create a task - passing ulMemCheckTaskRunningCount as a + parameter. */ + ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE; + xCreatedTask = mainNO_TASK; + + if( xTaskCreate( vMemCheckTask, ( signed char * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS ) + { + /* Could not create the task - we have probably run out of heap. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + /* Delay until it is time to execute again. */ + vTaskDelay( xDelayPeriod ); + + /* Delete the dynamically created task. */ + if( xCreatedTask != mainNO_TASK ) + { + vTaskDelete( xCreatedTask ); + } + + /* Check all the standard demo application tasks are executing without + error. ulMemCheckTaskRunningCount is checked to ensure it was + modified by the task just deleted. */ + if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS ) + { + /* An error has been detected in one of the tasks - flash faster. */ + xDelayPeriod = mainERROR_FLASH_PERIOD; + } + + prvToggleOnBoardLED(); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + #ifdef RUN_FROM_RAM + /* Remap the interrupt vectors to RAM if we are are running from RAM. */ + SCB_MEMMAP = 2; + #endif + + /* Configure the RS2332 pins. All other pins remain at their default of 0. */ + PCB_PINSEL0 |= mainTX_ENABLE; + PCB_PINSEL0 |= mainRX_ENABLE; + + /* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins. + The JTAG pins are left as input as I'm not sure what will happen if the + Wiggler is connected after powerup - not that it would be a good idea to + do that anyway. */ + GPIO_IODIR = ~( mainP0_14 + mainJTAG_PORT ); + + /* Setup the PLL to multiply the XTAL input by 4. */ + SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 ); + + /* Activate the PLL by turning it on then feeding the correct sequence of + bytes. */ + SCB_PLLCON = mainPLL_ENABLE; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Wait for the PLL to lock... */ + while( !( SCB_PLLSTAT & mainPLL_LOCK ) ); + + /* ...before connecting it using the feed sequence again. */ + SCB_PLLCON = mainPLL_CONNECT; + SCB_PLLFEED = mainPLL_FEED_BYTE1; + SCB_PLLFEED = mainPLL_FEED_BYTE2; + + /* Setup and turn on the MAM. Three cycle access is used due to the fast + PLL used. It is possible faster overall performance could be obtained by + tuning the MAM and PLL settings. */ + MAM_TIM = mainMAM_TIM_3; + MAM_CR = mainMAM_MODE_FULL; + + /* Setup the peripheral bus to be the same as the PLL output. */ + SCB_VPBDIV = mainBUS_CLK_FULL; + + /* Initialise LED outputs. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void prvToggleOnBoardLED( void ) +{ +unsigned long ulState; + + ulState = GPIO0_IOPIN; + if( ulState & mainON_BOARD_LED_BIT ) + { + GPIO_IOCLR = mainON_BOARD_LED_BIT; + } + else + { + GPIO_IOSET = mainON_BOARD_LED_BIT; + } +} +/*-----------------------------------------------------------*/ + +static long prvCheckOtherTasksAreStillRunning( unsigned long ulMemCheckTaskCount ) +{ +long lReturn = ( long ) pdPASS; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none of them have detected + an error. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xArePollingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = ( long ) pdFAIL; + } + + if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE ) + { + /* The vMemCheckTask did not increment the counter - it must + have failed. */ + lReturn = ( long ) pdFAIL; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static void vMemCheckTask( void *pvParameters ) +{ +unsigned long *pulMemCheckTaskRunningCounter; +void *pvMem1, *pvMem2, *pvMem3; +static long lErrorOccurred = pdFALSE; + + /* This task is dynamically created then deleted during each cycle of the + vErrorChecks task to check the operation of the memory allocator. Each time + the task is created memory is allocated for the stack and TCB. Each time + the task is deleted this memory is returned to the heap. This task itself + exercises the allocator by allocating and freeing blocks. + + The task executes at the idle priority so does not require a delay. + + pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the + vErrorChecks() task that this task is still executing without error. */ + + pulMemCheckTaskRunningCounter = ( unsigned long * ) pvParameters; + + for( ;; ) + { + if( lErrorOccurred == pdFALSE ) + { + /* We have never seen an error so increment the counter. */ + ( *pulMemCheckTaskRunningCounter )++; + } + + /* Allocate some memory - just to give the allocator some extra + exercise. This has to be in a critical section to ensure the + task does not get deleted while it has memory allocated. */ + vTaskSuspendAll(); + { + pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 ); + if( pvMem1 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 ); + vPortFree( pvMem1 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 ); + if( pvMem2 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 ); + vPortFree( pvMem2 ); + } + } + xTaskResumeAll(); + + /* Again - with a different size block. */ + vTaskSuspendAll(); + { + pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 ); + if( pvMem3 == NULL ) + { + lErrorOccurred = pdTRUE; + } + else + { + memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 ); + vPortFree( pvMem3 ); + } + } + xTaskResumeAll(); + } +} + + + diff --git a/simple-FreeRTOS-demo/serial/serial.c b/simple-FreeRTOS-demo/serial/serial.c new file mode 100644 index 0000000..706d886 --- /dev/null +++ b/simple-FreeRTOS-demo/serial/serial.c @@ -0,0 +1,284 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + Changes from V2.4.0 + + + Made serial ISR handling more complete and robust. + + Changes from V2.4.1 + + + Split serial.c into serial.c and serialISR.c. serial.c can be + compiled using ARM or THUMB modes. serialISR.c must always be + compiled in ARM mode. + + Another small change to cSerialPutChar(). + + Changed from V2.5.1 + + + In cSerialPutChar() an extra check is made to ensure the post to + the queue was successful if then attempting to retrieve the posted + character. + +*/ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. + + This file contains all the serial port components that can be compiled to + either ARM or THUMB mode. Components that must be compiled to ARM mode are + contained in serialISR.c. +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constants to setup and access the UART. */ +#define serDLAB ( ( unsigned char ) 0x80 ) +#define serENABLE_INTERRUPTS ( ( unsigned char ) 0x03 ) +#define serNO_PARITY ( ( unsigned char ) 0x00 ) +#define ser1_STOP_BIT ( ( unsigned char ) 0x00 ) +#define ser8_BIT_CHARS ( ( unsigned char ) 0x03 ) +#define serFIFO_ON ( ( unsigned char ) 0x01 ) +#define serCLEAR_FIFO ( ( unsigned char ) 0x06 ) +#define serWANTED_CLOCK_SCALING ( ( unsigned long ) 16 ) + +/* Constants to setup and access the VIC. */ +#define serUART0_VIC_CHANNEL ( ( unsigned long ) 0x0006 ) +#define serUART0_VIC_CHANNEL_BIT ( ( unsigned long ) 0x0040 ) +#define serUART0_VIC_ENABLE ( ( unsigned long ) 0x0020 ) +#define serCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 ) + +#define serINVALID_QUEUE ( ( xQueueHandle ) 0 ) +#define serHANDLE ( ( xComPortHandle ) 1 ) +#define serNO_BLOCK ( ( portTickType ) 0 ) + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/*-----------------------------------------------------------*/ + +/* Communication flag between the interrupt service routine and serial API. */ +static volatile long *plTHREEmpty; + +/* + * The queues are created in serialISR.c as they are used from the ISR. + * Obtain references to the queues and THRE Empty flag. + */ +extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, long volatile **pplTHREEmptyFlag ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ +unsigned long ulDivisor, ulWantedClock; +xComPortHandle xReturn = serHANDLE; +extern void ( vUART_ISR_Wrapper )( void ); + + /* The queues are used in the serial ISR routine, so are created from + serialISR.c (which is always compiled to ARM mode. */ + vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty ); + + if( + ( xRxedChars != serINVALID_QUEUE ) && + ( xCharsForTx != serINVALID_QUEUE ) && + ( ulWantedBaud != ( unsigned long ) 0 ) + ) + { + portENTER_CRITICAL(); + { + /* Setup the baud rate: Calculate the divisor value. */ + ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING; + ulDivisor = configCPU_CLOCK_HZ / ulWantedClock; + + /* Set the DLAB bit so we can access the divisor. */ + UART0_LCR |= serDLAB; + + /* Setup the divisor. */ + UART0_DLL = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff ); + ulDivisor >>= 8; + UART0_DLM = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff ); + + /* Turn on the FIFO's and clear the buffers. */ + UART0_FCR = ( serFIFO_ON | serCLEAR_FIFO ); + + /* Setup transmission format. */ + UART0_LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS; + + /* Setup the VIC for the UART. */ + VICIntSelect &= ~( serUART0_VIC_CHANNEL_BIT ); + VICIntEnable |= serUART0_VIC_CHANNEL_BIT; + VICVectAddr1 = ( long ) vUART_ISR_Wrapper; + VICVectCntl1 = serUART0_VIC_CHANNEL | serUART0_VIC_ENABLE; + + /* Enable UART0 interrupts. */ + UART0_IER |= serENABLE_INTERRUPTS; + } + portEXIT_CRITICAL(); + } + else + { + xReturn = ( xComPortHandle ) 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength ) +{ +signed char *pxNext; + + /* NOTE: This implementation does not handle the queue being full as no + block time is used! */ + + /* The port handle is not required as this driver only supports UART0. */ + ( void ) pxPort; + ( void ) usStringLength; + + /* Send each character in the string, one at a time. */ + pxNext = ( signed char * ) pcString; + while( *pxNext ) + { + xSerialPutChar( pxPort, *pxNext, serNO_BLOCK ); + pxNext++; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime ) +{ +signed portBASE_TYPE xReturn; + + /* This demo driver only supports one port so the parameter is not used. */ + ( void ) pxPort; + + portENTER_CRITICAL(); + { + /* Is there space to write directly to the UART? */ + if( *plTHREEmpty == ( long ) pdTRUE ) + { + /* We wrote the character directly to the UART, so was + successful. */ + *plTHREEmpty = pdFALSE; + UART0_THR = cOutChar; + xReturn = pdPASS; + } + else + { + /* We cannot write directly to the UART, so queue the character. + Block for a maximum of xBlockTime if there is no space in the + queue. */ + xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime ); + + /* Depending on queue sizing and task prioritisation: While we + were blocked waiting to post interrupts were not disabled. It is + possible that the serial ISR has emptied the Tx queue, in which + case we need to start the Tx off again. */ + if( ( *plTHREEmpty == ( long ) pdTRUE ) && ( xReturn == pdPASS ) ) + { + xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK ); + *plTHREEmpty = pdFALSE; + UART0_THR = cOutChar; + } + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/simple-FreeRTOS-demo/serial/serialISR.c b/simple-FreeRTOS-demo/serial/serialISR.c new file mode 100644 index 0000000..36a90c4 --- /dev/null +++ b/simple-FreeRTOS-demo/serial/serialISR.c @@ -0,0 +1,192 @@ +/* + FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd. + + *************************************************************************** + * * + * If you are: * + * * + * + New to FreeRTOS, * + * + Wanting to learn FreeRTOS or multitasking in general quickly * + * + Looking for basic training, * + * + Wanting to improve your FreeRTOS skills and productivity * + * * + * then take a look at the FreeRTOS eBook * + * * + * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * + * http://www.FreeRTOS.org/Documentation * + * * + * A pdf reference manual is also available. Both are usually delivered * + * to your inbox within 20 minutes to two hours when purchased between 8am * + * and 8pm GMT (although please allow up to 24 hours in case of * + * exceptional circumstances). Thank you for your support! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + ***NOTE*** The exception to the GPL is included to allow you to distribute + a combined work that includes FreeRTOS without being obliged to provide the + source code for proprietary components outside of the FreeRTOS kernel. + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0. + + This file contains all the serial port components that must be compiled + to ARM mode. The components that can be compiled to either ARM or THUMB + mode are contained in serial.c. + +*/ + +/* Standard includes. */ +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/*-----------------------------------------------------------*/ + +/* Constant to access the VIC. */ +#define serCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 ) + +/* Constants to determine the ISR source. */ +#define serSOURCE_THRE ( ( unsigned char ) 0x02 ) +#define serSOURCE_RX_TIMEOUT ( ( unsigned char ) 0x0c ) +#define serSOURCE_ERROR ( ( unsigned char ) 0x06 ) +#define serSOURCE_RX ( ( unsigned char ) 0x04 ) +#define serINTERRUPT_SOURCE_MASK ( ( unsigned char ) 0x0f ) + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; +static volatile long lTHREEmpty; + +/*-----------------------------------------------------------*/ + +/* + * The queues are created in serialISR.c as they are used from the ISR. + * Obtain references to the queues and THRE Empty flag. + */ +void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, long volatile **pplTHREEmptyFlag ); + +/* UART0 interrupt service routine entry point. */ +void vUART_ISR_Wrapper( void ) __attribute__ ((naked)); + +/* UART0 interrupt service routine handler. */ +void vUART_ISR_Handler( void ) __attribute__ ((noinline)); + +/*-----------------------------------------------------------*/ +void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, + xQueueHandle *pxCharsForTx, long volatile **pplTHREEmptyFlag ) +{ + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) ); + + /* Pass back a reference to the queues so the serial API file can + post/receive characters. */ + *pxRxedChars = xRxedChars; + *pxCharsForTx = xCharsForTx; + + /* Initialise the THRE empty flag - and pass back a reference. */ + lTHREEmpty = ( long ) pdTRUE; + *pplTHREEmptyFlag = &lTHREEmpty; +} +/*-----------------------------------------------------------*/ + +void vUART_ISR_Wrapper( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT(); + + /* Call the handler. This must be a separate function from the wrapper + to ensure the correct stack frame is set up. */ + __asm volatile ("bl vUART_ISR_Handler"); + + /* Restore the context of whichever task is going to run next. */ + portRESTORE_CONTEXT(); +} +/*-----------------------------------------------------------*/ + +void vUART_ISR_Handler( void ) +{ +signed char cChar; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + /* What caused the interrupt? */ + switch( UART0_IIR & serINTERRUPT_SOURCE_MASK ) + { + case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */ + cChar = UART0_LSR; + break; + + case serSOURCE_THRE : /* The THRE is empty. If there is another + character in the Tx queue, send it now. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE ) + { + UART0_THR = cChar; + } + else + { + /* There are no further characters + queued to send so we can indicate + that the THRE is available. */ + lTHREEmpty = pdTRUE; + } + break; + + case serSOURCE_RX_TIMEOUT : + case serSOURCE_RX : /* A character was received. Place it in + the queue of received characters. */ + cChar = UART0_RBR; + xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken ); + break; + + default : /* There is nothing to do, leave the ISR. */ + break; + } + + if( xHigherPriorityTaskWoken ) + { + portYIELD_FROM_ISR(); + } + + /* Clear the ISR in the VIC. */ + VICVectAddr = serCLEAR_VIC_INTERRUPT; +} + + + + + + + -- 2.11.4.GIT