From 46327c66750cfd597dbb3c2a1d4b7dea7170da4f Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Mon, 16 Jan 2012 11:01:51 +0100 Subject: [PATCH] ethernetgmii: used ethernetlite design, added dma, ethernet, removed ethernetlite, gpio stuff --- .../ethernetgmii/data/DDR3_SDRAM_mig_saved.prj | 119 ++---- microblaze/ethernetgmii/data/system.ucf | 419 ++++++------------ microblaze/ethernetgmii/misc/xilinx.dts | 42 +- microblaze/ethernetgmii/system.mhs | 466 ++++++++++++--------- microblaze/ethernetgmii/system.xmp | 2 + 5 files changed, 444 insertions(+), 604 deletions(-) rewrite microblaze/ethernetgmii/data/system.ucf (86%) diff --git a/microblaze/ethernetgmii/data/DDR3_SDRAM_mig_saved.prj b/microblaze/ethernetgmii/data/DDR3_SDRAM_mig_saved.prj index a2d50c7..c1895b9 100644 --- a/microblaze/ethernetgmii/data/DDR3_SDRAM_mig_saved.prj +++ b/microblaze/ethernetgmii/data/DDR3_SDRAM_mig_saved.prj @@ -1,19 +1,20 @@ - axi_v6_ddrx_0 + DDR3_SDRAM 1 0 OFF xc6vlx240t-ff1156/-1 - 3.6 + 3.8 Differential TRUE HIGH 0 + IODELAY_MIG - DDR3_SDRAM/SODIMMs/MT4JSF6464HY-1G1 + DDR3_SDRAM/Components/MT41J64M16XX-15E 2500 - 64 + 8 1 1 FALSE @@ -21,25 +22,18 @@ 13 10 3 - 26,36 + 36 - + Disabled 1 36 + ROW_BANK_COLUMN Normal - - - - - - - - @@ -62,101 +56,22 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -179,5 +94,23 @@ Normal Dynamic ODT off AXI + + AUTOMATIC + AUTOMATIC + AUTOMATIC + microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC + 4 + 0 + AUTOMATIC + 0 + 4 + 0 + AUTOMATIC + 32 + 0xc0000000 + 32 + 0xcfffffff + Auto + diff --git a/microblaze/ethernetgmii/data/system.ucf b/microblaze/ethernetgmii/data/system.ucf dissimilarity index 86% index 12d9867..1bca7fe 100644 --- a/microblaze/ethernetgmii/data/system.ucf +++ b/microblaze/ethernetgmii/data/system.ucf @@ -1,289 +1,130 @@ -# -# pin constraints -# -NET CLK_N LOC = "H9" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; -NET CLK_P LOC = "J9" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; -NET DIP_Switches_8Bits_TRI_I[0] LOC = "D22" | IOSTANDARD = "LVCMOS15"; -NET DIP_Switches_8Bits_TRI_I[1] LOC = "C22" | IOSTANDARD = "LVCMOS15"; -NET DIP_Switches_8Bits_TRI_I[2] LOC = "L21" | IOSTANDARD = "LVCMOS15"; -NET DIP_Switches_8Bits_TRI_I[3] LOC = "L20" | IOSTANDARD = "LVCMOS15"; -NET DIP_Switches_8Bits_TRI_I[4] LOC = "C18" | IOSTANDARD = "LVCMOS15"; -NET DIP_Switches_8Bits_TRI_I[5] LOC = "B18" | IOSTANDARD = "LVCMOS15"; -NET DIP_Switches_8Bits_TRI_I[6] LOC = "K22" | IOSTANDARD = "LVCMOS15"; -NET DIP_Switches_8Bits_TRI_I[7] LOC = "K21" | IOSTANDARD = "LVCMOS15"; -NET ETHERNET_MDC LOC = "AP14" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_MDIO LOC = "AN14" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_MII_TX_CLK LOC = "AD12" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_PHY_RST_N LOC = "AH13" | IOSTANDARD = "LVCMOS25" | TIG; -NET ETHERNET_RXD[0] LOC = "AN13" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[1] LOC = "AF14" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[2] LOC = "AE14" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[3] LOC = "AN12" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[4] LOC = "AM12" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[5] LOC = "AD11" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[6] LOC = "AC12" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RXD[7] LOC = "AC13" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RX_CLK LOC = "AP11" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RX_DV LOC = "AM13" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_RX_ER LOC = "AG12" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[0] LOC = "AM11" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[1] LOC = "AL11" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[2] LOC = "AG10" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[3] LOC = "AG11" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[4] LOC = "AL10" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[5] LOC = "AM10" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[6] LOC = "AE11" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TXD[7] LOC = "AF11" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TX_CLK LOC = "AH12" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TX_EN LOC = "AJ10" | IOSTANDARD = "LVCMOS25"; -NET ETHERNET_TX_ER LOC = "AH10" | IOSTANDARD = "LVCMOS25"; -NET LEDs_8Bits_TRI_O[0] LOC = "AC22" | IOSTANDARD = "LVCMOS25"; -NET LEDs_8Bits_TRI_O[1] LOC = "AC24" | IOSTANDARD = "LVCMOS25"; -NET LEDs_8Bits_TRI_O[2] LOC = "AE22" | IOSTANDARD = "LVCMOS25"; -NET LEDs_8Bits_TRI_O[3] LOC = "AE23" | IOSTANDARD = "LVCMOS25"; -NET LEDs_8Bits_TRI_O[4] LOC = "AB23" | IOSTANDARD = "LVCMOS25"; -NET LEDs_8Bits_TRI_O[5] LOC = "AG23" | IOSTANDARD = "LVCMOS25"; -NET LEDs_8Bits_TRI_O[6] LOC = "AE24" | IOSTANDARD = "LVCMOS25"; -NET LEDs_8Bits_TRI_O[7] LOC = "AD24" | IOSTANDARD = "LVCMOS25"; -NET LEDs_Positions_TRI_O[0] LOC = "AP24" | IOSTANDARD = "LVCMOS25"; -NET LEDs_Positions_TRI_O[1] LOC = "AE21" | IOSTANDARD = "LVCMOS25"; -NET LEDs_Positions_TRI_O[2] LOC = "AH27" | IOSTANDARD = "LVCMOS25"; -NET LEDs_Positions_TRI_O[3] LOC = "AH28" | IOSTANDARD = "LVCMOS25"; -NET LEDs_Positions_TRI_O[4] LOC = "AD21" | IOSTANDARD = "LVCMOS25"; -NET Push_Buttons_5Bits_TRI_I[0] LOC = "G26" | IOSTANDARD = "LVCMOS15"; -NET Push_Buttons_5Bits_TRI_I[1] LOC = "A19" | IOSTANDARD = "LVCMOS15"; -NET Push_Buttons_5Bits_TRI_I[2] LOC = "G17" | IOSTANDARD = "LVCMOS15"; -NET Push_Buttons_5Bits_TRI_I[3] LOC = "A18" | IOSTANDARD = "LVCMOS15"; -NET Push_Buttons_5Bits_TRI_I[4] LOC = "H17" | IOSTANDARD = "LVCMOS15"; -NET RESET LOC = "H10" | IOSTANDARD = "SSTL15" | TIG; -NET RS232_Uart_1_sin LOC = "J24" | IOSTANDARD = "LVCMOS25"; -NET RS232_Uart_1_sout LOC = "J25" | IOSTANDARD = "LVCMOS25"; -# -# additional constraints -# - -NET "CLK" TNM_NET = sys_clk_pin; -TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz; - -###### Hard Ethernet -# This is a GMII system -# AXI_STR_*_ACLK is not the same as S_AXI_ACLK (AXI-Lite) from clock generator -# Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods -# Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency -# allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB, -# the constraints are over constrained. Relaxing them for your system may reduce build time. - -NET "*ETHERNET*/S_AXI_ACLK" TNM_NET = "axi4lite_clk"; -NET "*ETHERNET*/AXI_STR_TXD_ACLK" TNM_NET = "axistream_clk"; -NET "*ETHERNET*/AXI_STR_TXC_ACLK" TNM_NET = "axistream_clk"; -NET "*ETHERNET*/AXI_STR_RXD_ACLK" TNM_NET = "axistream_clk"; -NET "*ETHERNET*/AXI_STR_RXS_ACLK" TNM_NET = "axistream_clk"; - -############################################################################### -# CLOCK CONSTRAINTS -# The following constraints are required. If you choose to not use the example -# design level of wrapper hierarchy, the net names should be translated to -# match your design. -############################################################################### - -############################################################ -# RX Clock period Constraints # -############################################################ -# Ethernet GMII PHY-side receive clock -# __________ -# | | -# --- GMII_RX_CLK-----| BUFR |---Rx_Client_Clk -# |__________| -# -# Changed NET name -# NET "GMII_RX_CLK" TNM_NET = "phy_clk_rx"; -NET "*/rx_client_clk" TNM_NET = "phy_clk_rx"; -TIMEGRP "v6_emac_v1_3_clk_phy_rx" = "phy_clk_rx"; -TIMESPEC "TS_v6_emac_v1_3_clk_phy_rx" = PERIOD "v6_emac_v1_3_clk_phy_rx" 7.5 ns HIGH 50 %; - -############################################################ -# TX Clock period Constraints # -############################################################ -############################################################################### -# The following two TimeSpecs are from CoreGen Ethernet Core Example Design UCF -# file. In systems GTX_CLK is driven by clock generator core, then the derived -# period constraint will override these TimeSpecs. -############################################################################### -# Ethernet GTX_CLK high quality 125 MHz reference clock -# __________ -# -GTX_CLK------------| | -# | BUFGMUX |---Tx_Client_Clk -# -MII_TX_CLK---------|__________| -# -# Depending on system configuration, the analysis tool may use either gtx_clk -# or tx_client_clk so both nets are used in defining PERIOD constraint and -# TNM_NETS for subsequent constraints. -# The PERIOD constraints may not be analyzed if inferred clock generator -# constraints are generated for the system. - -# Transmitter clock period constraints: please do not relax -# Changed NET -# NET "GTX_CLK" TNM_NET = "ref_gtx_clk"; -NET "*/GTX_CLK" TNM_NET = "clk_gtx"; #name of signal connected to ETHERNET GTX_CLK_0 input -TIMEGRP "v6_emac_v1_3_clk_ref_gtx" = "clk_gtx"; -TIMESPEC "TS_v6_emac_v1_3_clk_ref_gtx" = PERIOD "v6_emac_v1_3_clk_ref_gtx" 8 ns HIGH 50 %; - -# Multiplexed 1 Gbps, 10/100 Mbps output inherits constraint from GTX_CLK -# Changed NET name -# NET "tx_clk" TNM_NET = "ref_mux_clk"; -# Changed TMN_NET name for tx_clk to keep time domain crossing constraints consistent in EDK core UCF files -NET "*/tx_client_clk" TNM_NET = "phy_clk_tx"; -TIMEGRP "v6_emac_v1_3_clk_ref_mux" = "phy_clk_tx"; -TIMESPEC "TS_v6_emac_v1_3_clk_ref_mux" = PERIOD "v6_emac_v1_3_clk_ref_mux" TS_v6_emac_v1_3_clk_ref_gtx HIGH 50%; - -# IDELAYCTRL 200 MHz reference clock -# Changed NET name -# There are no clocked components on this clock so there will be no analyzed paths -# NET "REFCLK" TNM_NET = "clk_ref_clk"; -NET "*/REF_CLK" TNM_NET = "clk_ref_clk"; -TIMEGRP "ref_clk" = "clk_ref_clk"; -TIMESPEC "TS_ref_clk" = PERIOD "ref_clk" 5 ns HIGH 50 %; - -############################################################ -# Host Clock period Constraint # -############################################################ -# In systems using hard ETHERNET cores these TimeSpecs will not be analyzed -# Constraint the host interface clock to an example frequency of 100 MHz -# NET "HOSTCLK" TNM_NET = "host_clock"; -# TIMEGRP "clk_host" = "host_clock"; -# TIMESPEC "TS_clk_host" = PERIOD "clk_host" 10 ns HIGH 50 %; - -############################################################################### -# PHYSICAL INTERFACE CONSTRAINTS -# The following constraints are necessary for proper operation, and are tuned -# for this example design. They should be modified to suit your design. -############################################################################### - -# GMII physical interface constraints -# ----------------------------------------------------------------------------- - -# Set the IDELAY values on the PHY inputs, tuned for this example design. -# These values should be modified to suit your design. -INST "*gmii*ideldv" IDELAY_VALUE = 30; -INST "*gmii*ideld0" IDELAY_VALUE = 25; -INST "*gmii*ideld1" IDELAY_VALUE = 31; -INST "*gmii*ideld2" IDELAY_VALUE = 31; -INST "*gmii*ideld3" IDELAY_VALUE = 27; -INST "*gmii*ideld4" IDELAY_VALUE = 29; -INST "*gmii*ideld5" IDELAY_VALUE = 31; -INST "*gmii*ideld6" IDELAY_VALUE = 31; -INST "*gmii*ideld7" IDELAY_VALUE = 31; -INST "*gmii*ideler" IDELAY_VALUE = 22; -INST "*gmii_rxc_delay" IDELAY_VALUE = 0; -INST "*gmii_rxc_delay" SIGNAL_PATTERN = CLOCK; - -# Signal trace properties for ML605 Board used in offset in constraints below - -# This signal trace is longer than the clock trace, and arrives at the FPGA pin ~65 ps after the clock -# Therefore the offset in constraint must have less setup time than nominal -NET ETHERNET_RXD[0] OFFSET = IN 2.435 ns VALID 3 ns BEFORE "ETHERNET_RX_CLK"; - -# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~375 ps before the clock -# Therefore the offset in constraint must have more setup time than nominal -NET ETHERNET_RXD[1] OFFSET = IN 2.875 ns VALID 3 ns BEFORE "ETHERNET_RX_CLK"; - -# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~372 ps before the clock -# Therefore the offset in constraint must have more setup time than nominal -NET ETHERNET_RXD[2] OFFSET = IN 2.872 ns VALID 3 ns BEFORE "ETHERNET_RX_CLK"; - -# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~115 ps before the clock -# Therefore the offset in constraint must have more setup time than nominal -NET ETHERNET_RXD[3] OFFSET = IN 2.615 ns VALID 3 ns BEFORE "ETHERNET_RX_CLK"; - -# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~244 ps before the clock -# Therefore the offset in constraint must have more setup time than nominal -NET ETHERNET_RXD[4] OFFSET = IN 2.744 ns VALID 3 ns BEFORE "ETHERNET_RX_CLK"; - -# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~404 ps before the clock -# Therefore the offset in constraint must have more setup time than nominal -NET ETHERNET_RXD[5] OFFSET = IN 2.904 ns VALID 3 ns BEFORE "ETHERNET_RX_CLK"; - -# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~498 ps before the clock -# Therefore the offset in constraint must have more setup time than nominal -NET ETHERNET_RXD[6] OFFSET = IN 2.998 ns VALID 3 ns BEFORE "ETHERNET_RX_CLK"; - -# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~485 ps before the clock -# Therefore the offset in constraint must have more setup time than nominal -NET ETHERNET_RXD[7] OFFSET = IN 2.985 ns VALID 3 ns BEFORE "ETHERNET_RX_CLK"; - -# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~291 ps before the clock -# Therefore the offset in constraint must have more setup time than nominal -NET ETHERNET_RX_DV OFFSET = IN 2.791 ns VALID 3 ns BEFORE "ETHERNET_RX_CLK"; - -# This signal trace is longer than the clock trace, and arrives at the FPGA pin ~308 ps after the clock -# Therefore the offset in constraint must have less setup time than nominal -NET ETHERNET_RX_ER OFFSET = IN 2.192 ns VALID 3 ns BEFORE "ETHERNET_RX_CLK"; - -# Constrain the GMII physical interface flip-flops to IOBs -# Changed from 'true' to 'force' -# INST "*gmii?RXD_TO_MAC*" IOB = true; -# INST "*gmii?RX_DV_TO_MAC" IOB = true; -# INST "*gmii?RX_ER_TO_MAC" IOB = true; -# INST "*gmii?GMII_TXD_?" IOB = true; -# INST "*gmii?GMII_TX_EN" IOB = true; -# INST "*gmii?GMII_TX_ER" IOB = true; -INST "*gmii?RXD_TO_MAC*" IOB = force; -INST "*gmii?RX_DV_TO_MAC" IOB = force; -INST "*gmii?RX_ER_TO_MAC" IOB = force; -INST "*gmii?GMII_TXD_?" IOB = force; -INST "*gmii?GMII_TX_EN" IOB = force; -INST "*gmii?GMII_TX_ER" IOB = force; - -############################################################ -# Crossing of Clock Domain Constraints: please do not edit # -# In addition to CoreGen constraints # -############################################################ - -# The following TimeSpecs are required only when AXILite clock differs from AXI-Stream clock -# Data path timing depends on the destination clock period -TIMESPEC "TS_axistreamclks_2_axi4liteclks" = FROM axistream_clk TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz -TIMESPEC "TS_axi4liteclks_2_axistreamclks" = FROM axi4lite_clk TO axistream_clk 6667 ps DATAPATHONLY; #assumes axistream_clk <= 150 MHz - -# TNM_NET phy_clk_rx is rx_client_clk -# TIMESPECs for AXI streaming clock crossing to/from rx_client_clk -TIMESPEC "TS_axistreamclks_2_RX_CLIENT_CLK" = FROM axistream_clk TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz -TIMESPEC "TS_RX_CLIENT_CLK_2_axistreamclks" = FROM phy_clk_rx TO axistream_clk 6667 ps DATAPATHONLY; #assumes axistream_clk <= 150 MHz -# TIMESPECs for AXI-Lite clock crossing to/from tx_client_clk -TIMESPEC "TS_axi4liteclks_2_RX_CLIENT_CLK" = FROM axi4lite_clk TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz -TIMESPEC "TS_RX_CLIENT_CLK_2_axi4liteclks" = FROM phy_clk_rx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz - -# Depending on system configuration, the analysis tool may use either TNM_NET clk_gtx -# or TNM_NET phy_clk_tx so only one set will be analyzed -# TNM_NET phy_clk_tx is tx_client_clk -# TIMESPECs for AXI streaming clock crossing to/from tx_client_clk -TIMESPEC "TS_axistreamclks_2_TX_CLIENT_CLK" = FROM axistream_clk TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz -TIMESPEC "TS_TX_CLIENT_CLK_2_axistreamclks" = FROM phy_clk_tx TO axistream_clk 6667 ps DATAPATHONLY; #assumes axistream_clk <= 150 MHz -# TIMESPECs for AXI-Lite clock crossing to/from tx_client_clk -TIMESPEC "TS_axi4liteclks_2_TX_CLIENT_CLK" = FROM axi4lite_clk TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz -TIMESPEC "TS_TX_CLIENT_CLK_2_axi4liteclks" = FROM phy_clk_tx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz - -# TNM_NET clk_gtx is */GTX_CLK -# TIMESPECs for AXI Streaming clock crossing to/from GTX_CLK -TIMESPEC "TS_axistreamclks_2_GTX_CLK" = FROM axistream_clk TO clk_gtx 8000 ps DATAPATHONLY; #assumes clk_gtx <= 125 MHz -TIMESPEC "TS_GTX_CLK_2_axistreamclks" = FROM clk_gtx TO axistream_clk 6667 ps DATAPATHONLY; #assumes axistream_clk <= 150 MHz -# TIMESPECs for AXI-Lite clock crossing to/from GTX_CLK -TIMESPEC "TS_axi4lite_clk_2_GTX_CLK" = FROM axi4lite_clk TO clk_gtx 8000 ps DATAPATHONLY; #assumes clk_gtx <= 125 MHz -TIMESPEC "TS_GTX_CLK_2_axi4lite_clk" = FROM clk_gtx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz - -# Depending on system configuration, the analysis tool may use either TNM_NET clk_gtx -# or TNM_NET phy_clk_tx so only one set will be analyzed -# Rx Clock crossings - Some paths are analyzed by the TS_flow_rx_to_tx constraint also -# Needed since ts_resync_flops is commented out -TIMESPEC "TS_RX_CLIENT_CLK_2_TX_CLIENT_CLK" = FROM phy_clk_rx TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz -TIMESPEC "TS_TX_CLIENT_CLK_2_RX_CLIENT_CLK" = FROM phy_clk_tx TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz -TIMESPEC "TS_RX_CLIENT_CLK_2_GTX_CLK" = FROM phy_clk_rx TO clk_gtx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz -TIMESPEC "TS_GTX_CLK_2_RX_CLIENT_CLK" = FROM clk_gtx TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz - -# TIMESPECs for AXI-Lite/AXI Streaming clock crossing to/from REF_CLK -# These constraints are added so trace does not analyze an asynchronous reset to idelayctrls with a contrived clock relationship -# as a warning that a asynchronous signal exists -TIMESPEC "TS_axistreamclks_2_REF_CLK" = FROM axistream_clk TO clk_ref_clk 5000 ps DATAPATHONLY; #assumes clk_ref_clk <= 200 MHz -TIMESPEC "TS_REF_CLK_2_axistreamclks" = FROM clk_ref_clk TO axistream_clk 6667 ps DATAPATHONLY; #assumes axistream_clk <= 150 MHz -TIMESPEC "TS_axi4lite_clk_2_REF_CLK" = FROM axi4lite_clk TO clk_ref_clk 5000 ps DATAPATHONLY; #assumes clk_ref_clk <= 200 MHz -TIMESPEC "TS_REF_CLK_2_axi4lite_clk" = FROM clk_ref_clk TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz - +# +# pin constraints +# +NET CLK_N LOC = "H9" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; +NET CLK_P LOC = "J9" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; +NET DIP_Switches_8Bits_TRI_I[0] LOC = "D22" | IOSTANDARD = "LVCMOS15"; +NET DIP_Switches_8Bits_TRI_I[1] LOC = "C22" | IOSTANDARD = "LVCMOS15"; +NET DIP_Switches_8Bits_TRI_I[2] LOC = "L21" | IOSTANDARD = "LVCMOS15"; +NET DIP_Switches_8Bits_TRI_I[3] LOC = "L20" | IOSTANDARD = "LVCMOS15"; +NET DIP_Switches_8Bits_TRI_I[4] LOC = "C18" | IOSTANDARD = "LVCMOS15"; +NET DIP_Switches_8Bits_TRI_I[5] LOC = "B18" | IOSTANDARD = "LVCMOS15"; +NET DIP_Switches_8Bits_TRI_I[6] LOC = "K22" | IOSTANDARD = "LVCMOS15"; +NET DIP_Switches_8Bits_TRI_I[7] LOC = "K21" | IOSTANDARD = "LVCMOS15"; +NET Ethernet_Lite_COL LOC = "AK13" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_CRS LOC = "AL13" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_MDC LOC = "AP14" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_MDIO LOC = "AN14" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_PHY_RST_N LOC = "AH13" | IOSTANDARD = "LVCMOS25" | TIG; +NET Ethernet_Lite_RXD[0] LOC = "AN13" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[1] LOC = "AF14" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[2] LOC = "AE14" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[3] LOC = "AN12" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_CLK LOC = "AP11" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_DV LOC = "AM13" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_ER LOC = "AG12" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[0] LOC = "AM11" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[1] LOC = "AL11" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[2] LOC = "AG10" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[3] LOC = "AG11" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TX_CLK LOC = "AD12" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TX_EN LOC = "AJ10" | IOSTANDARD = "LVCMOS25"; +NET IIC_DVI_SCL LOC = "AN10" | DRIVE = "6" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW"; +NET IIC_DVI_SDA LOC = "AP10" | DRIVE = "6" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW"; +NET IIC_EEPROM_SCL LOC = "AK9" | DRIVE = "6" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW"; +NET IIC_EEPROM_SDA LOC = "AE9" | DRIVE = "6" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW"; +NET IIC_FMC_SCL LOC = "AF13" | DRIVE = "6" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW"; +NET IIC_FMC_SDA LOC = "AG13" | DRIVE = "6" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW"; +NET IIC_SFP_SCL LOC = "AA34" | DRIVE = "6" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW"; +NET IIC_SFP_SDA LOC = "AA33" | DRIVE = "6" | IOSTANDARD = "LVCMOS25" | SLEW = "SLOW"; +NET LEDs_8Bits_TRI_O[0] LOC = "AC22" | IOSTANDARD = "LVCMOS25"; +NET LEDs_8Bits_TRI_O[1] LOC = "AC24" | IOSTANDARD = "LVCMOS25"; +NET LEDs_8Bits_TRI_O[2] LOC = "AE22" | IOSTANDARD = "LVCMOS25"; +NET LEDs_8Bits_TRI_O[3] LOC = "AE23" | IOSTANDARD = "LVCMOS25"; +NET LEDs_8Bits_TRI_O[4] LOC = "AB23" | IOSTANDARD = "LVCMOS25"; +NET LEDs_8Bits_TRI_O[5] LOC = "AG23" | IOSTANDARD = "LVCMOS25"; +NET LEDs_8Bits_TRI_O[6] LOC = "AE24" | IOSTANDARD = "LVCMOS25"; +NET LEDs_8Bits_TRI_O[7] LOC = "AD24" | IOSTANDARD = "LVCMOS25"; +NET LEDs_Positions_TRI_O[0] LOC = "AP24" | IOSTANDARD = "LVCMOS25"; +NET LEDs_Positions_TRI_O[1] LOC = "AE21" | IOSTANDARD = "LVCMOS25"; +NET LEDs_Positions_TRI_O[2] LOC = "AH27" | IOSTANDARD = "LVCMOS25"; +NET LEDs_Positions_TRI_O[3] LOC = "AH28" | IOSTANDARD = "LVCMOS25"; +NET LEDs_Positions_TRI_O[4] LOC = "AD21" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[0] LOC = "AA23" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[10] LOC = "C10" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[11] LOC = "D10" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[12] LOC = "C9" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[13] LOC = "D9" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[14] LOC = "A9" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[15] LOC = "A8" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[16] LOC = "E8" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[17] LOC = "E9" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[18] LOC = "B8" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[19] LOC = "C8" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[1] LOC = "AL9" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[20] LOC = "AD10" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[21] LOC = "AC9" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[22] LOC = "AK8" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[23] LOC = "AL8" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[2] LOC = "AF9" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[3] LOC = "AF10" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[4] LOC = "AN9" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[5] LOC = "AP9" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[6] LOC = "AG8" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[7] LOC = "AH8" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[8] LOC = "F9" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_address[9] LOC = "F10" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_ce_n LOC = "AJ12" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[0] LOC = "M23" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[10] LOC = "H25" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[11] LOC = "H24" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[12] LOC = "V24" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[13] LOC = "W24" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[14] LOC = "AF25" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[15] LOC = "AF24" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[1] LOC = "L24" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[2] LOC = "F24" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[3] LOC = "F23" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[4] LOC = "N23" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[5] LOC = "N24" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[6] LOC = "H23" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[7] LOC = "G23" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[8] LOC = "R24" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_data[9] LOC = "P24" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_oe_n LOC = "AA24" | IOSTANDARD = "LVCMOS25"; +NET Linear_Flash_we_n LOC = "AF23" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_5Bits_TRI_I[0] LOC = "G26" | IOSTANDARD = "LVCMOS15"; +NET Push_Buttons_5Bits_TRI_I[1] LOC = "A19" | IOSTANDARD = "LVCMOS15"; +NET Push_Buttons_5Bits_TRI_I[2] LOC = "G17" | IOSTANDARD = "LVCMOS15"; +NET Push_Buttons_5Bits_TRI_I[3] LOC = "A18" | IOSTANDARD = "LVCMOS15"; +NET Push_Buttons_5Bits_TRI_I[4] LOC = "H17" | IOSTANDARD = "LVCMOS15"; +NET RESET LOC = "H10" | IOSTANDARD = "SSTL15" | TIG; +NET RS232_Uart_1_sin LOC = "J24" | IOSTANDARD = "LVCMOS25"; +NET RS232_Uart_1_sout LOC = "J25" | IOSTANDARD = "LVCMOS25"; +NET SysACE_CEN LOC = "AJ14" | IOSTANDARD = "LVCMOS25"; +NET SysACE_CLK LOC = "AE16" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPA[0] LOC = "AC15" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPA[1] LOC = "AP15" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPA[2] LOC = "AG17" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPA[3] LOC = "AH17" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPA[4] LOC = "AG15" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPA[5] LOC = "AF15" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPA[6] LOC = "AK14" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPD[0] LOC = "AM15" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPD[1] LOC = "AJ17" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPD[2] LOC = "AJ16" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPD[3] LOC = "AP16" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPD[4] LOC = "AG16" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPD[5] LOC = "AH15" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPD[6] LOC = "AF16" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPD[7] LOC = "AN15" | IOSTANDARD = "LVCMOS25"; +NET SysACE_MPIRQ LOC = "L9" | IOSTANDARD = "LVCMOS25" | TIG; +NET SysACE_OEN LOC = "AL15" | IOSTANDARD = "LVCMOS25"; +NET SysACE_WEN LOC = "AL14" | IOSTANDARD = "LVCMOS25"; +# +# additional constraints +# + +NET "CLK" TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz; + diff --git a/microblaze/ethernetgmii/misc/xilinx.dts b/microblaze/ethernetgmii/misc/xilinx.dts index ab2ede9..c9ec2c6 100644 --- a/microblaze/ethernetgmii/misc/xilinx.dts +++ b/microblaze/ethernetgmii/misc/xilinx.dts @@ -54,39 +54,39 @@ compatible = "xlnx,microblaze-8.20.a"; d-cache-baseaddr = <0xc0000000>; d-cache-highaddr = <0xcfffffff>; - d-cache-line-size = <0x20>; - d-cache-size = <0x8000>; + d-cache-line-size = <0x10>; + d-cache-size = <0x4000>; device_type = "cpu"; i-cache-baseaddr = <0xc0000000>; i-cache-highaddr = <0xcfffffff>; i-cache-line-size = <0x20>; - i-cache-size = <0x8000>; + i-cache-size = <0x4000>; model = "microblaze,8.20.a"; reg = <0>; timebase-frequency = <100000000>; - xlnx,addr-tag-bits = <0xd>; + xlnx,addr-tag-bits = <0xe>; xlnx,allow-dcache-wr = <0x1>; xlnx,allow-icache-wr = <0x1>; xlnx,area-optimized = <0x0>; xlnx,avoid-primitives = <0x0>; xlnx,branch-target-cache-size = <0x0>; - xlnx,cache-byte-size = <0x8000>; + xlnx,cache-byte-size = <0x4000>; xlnx,d-axi = <0x1>; xlnx,d-lmb = <0x1>; xlnx,d-plb = <0x0>; xlnx,data-size = <0x20>; - xlnx,dcache-addr-tag = <0xd>; + xlnx,dcache-addr-tag = <0xe>; xlnx,dcache-always-used = <0x1>; - xlnx,dcache-byte-size = <0x8000>; + xlnx,dcache-byte-size = <0x4000>; xlnx,dcache-data-width = <0x0>; xlnx,dcache-force-tag-lutram = <0x0>; - xlnx,dcache-interface = <0x1>; - xlnx,dcache-line-len = <0x8>; + xlnx,dcache-interface = <0x0>; + xlnx,dcache-line-len = <0x4>; xlnx,dcache-use-fsl = <0x0>; - xlnx,dcache-use-writeback = <0x1>; - xlnx,dcache-victims = <0x8>; + xlnx,dcache-use-writeback = <0x0>; + xlnx,dcache-victims = <0x0>; xlnx,debug-enabled = <0x1>; - xlnx,div-zero-exception = <0x0>; + xlnx,div-zero-exception = <0x1>; xlnx,dynamic-bus-sizing = <0x1>; xlnx,ecc-use-ce-exception = <0x0>; xlnx,edge-is-positive = <0x1>; @@ -109,7 +109,7 @@ xlnx,icache-streams = <0x1>; xlnx,icache-use-fsl = <0x0>; xlnx,icache-victims = <0x8>; - xlnx,ill-opcode-exception = <0x0>; + xlnx,ill-opcode-exception = <0x1>; xlnx,instance = "microblaze_0"; xlnx,interconnect = <0x2>; xlnx,interconnect-m-axi-dc-aw-register = <0x0>; @@ -126,31 +126,31 @@ xlnx,mmu-itlb-size = <0x2>; xlnx,mmu-privileged-instr = <0x0>; xlnx,mmu-tlb-access = <0x3>; - xlnx,mmu-zones = <0x10>; + xlnx,mmu-zones = <0x2>; xlnx,number-of-pc-brk = <0x1>; xlnx,number-of-rd-addr-brk = <0x0>; xlnx,number-of-wr-addr-brk = <0x0>; - xlnx,opcode-0x0-illegal = <0x0>; + xlnx,opcode-0x0-illegal = <0x1>; xlnx,optimization = <0x0>; - xlnx,pvr = <0x0>; + xlnx,pvr = <0x2>; xlnx,pvr-user1 = <0x0>; xlnx,pvr-user2 = <0x0>; xlnx,reset-msr = <0x0>; xlnx,sco = <0x0>; xlnx,stream-interconnect = <0x0>; - xlnx,unaligned-exceptions = <0x0>; + xlnx,unaligned-exceptions = <0x1>; xlnx,use-barrel = <0x1>; - xlnx,use-branch-target-cache = <0x1>; + xlnx,use-branch-target-cache = <0x0>; xlnx,use-dcache = <0x1>; xlnx,use-div = <0x1>; xlnx,use-ext-brk = <0x1>; xlnx,use-ext-nm-brk = <0x1>; xlnx,use-extended-fsl-instr = <0x0>; - xlnx,use-fpu = <0x2>; + xlnx,use-fpu = <0x0>; xlnx,use-hw-mul = <0x2>; xlnx,use-icache = <0x1>; xlnx,use-interrupt = <0x1>; - xlnx,use-mmu = <0x0>; + xlnx,use-mmu = <0x3>; xlnx,use-msr-instr = <0x1>; xlnx,use-pcmp-instr = <0x1>; xlnx,use-stack-protection = <0x0>; @@ -182,7 +182,7 @@ device_type = "network"; interrupt-parent = <µblaze_0_intc>; interrupts = < 3 2 >; - local-mac-address = [ 00 0a 35 8a 76 00 ]; + local-mac-address = [ 00 0a 35 6c 2b 00 ]; phy-handle = <&phy0>; reg = < 0x41240000 0x40000 >; xlnx,avb = <0x0>; diff --git a/microblaze/ethernetgmii/system.mhs b/microblaze/ethernetgmii/system.mhs index 7da93d5..ac006f7 100644 --- a/microblaze/ethernetgmii/system.mhs +++ b/microblaze/ethernetgmii/system.mhs @@ -1,7 +1,7 @@ # ############################################################################## -# Created by Base System Builder Wizard for Xilinx EDK 13.1 Build EDK_O.40c -# Thu Jan 27 12:14:06 2011 +# Created by Base System Builder Wizard for Xilinx EDK 13.2 Build EDK_O.61xd +# Mon Jan 9 16:09:41 2012 # Target Board: xilinx.com ml605 Rev D # Family: virtex6 # Device: xc6vlx240t @@ -11,32 +11,52 @@ PARAMETER VERSION = 2.1.0 - PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1 - PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000 - PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000 - PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O - PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I - PORT DIP_Switches_8Bits_TRI_I = DIP_Switches_8Bits_TRI_I, DIR = I, VEC = [0:7] - PORT LEDs_8Bits_TRI_O = LEDs_8Bits_TRI_O, DIR = O, VEC = [0:7] - PORT LEDs_Positions_TRI_O = LEDs_Positions_TRI_O, DIR = O, VEC = [0:4] - PORT Push_Buttons_5Bits_TRI_I = Push_Buttons_5Bits_TRI_I, DIR = I, VEC = [0:4] - PORT ddr_memory_clk = ddr_memory_clk, DIR = O + PORT ddr_memory_we_n = ddr_memory_we_n, DIR = O + PORT ddr_memory_ras_n = ddr_memory_ras_n, DIR = O + PORT ddr_memory_odt = ddr_memory_odt, DIR = O + PORT ddr_memory_dqs_n = ddr_memory_dqs_n, DIR = IO, VEC = [0:0] + PORT ddr_memory_dqs = ddr_memory_dqs, DIR = IO, VEC = [0:0] + PORT ddr_memory_dq = ddr_memory_dq, DIR = IO, VEC = [7:0] + PORT ddr_memory_dm = ddr_memory_dm, DIR = O, VEC = [0:0] + PORT ddr_memory_ddr3_rst = ddr_memory_ddr3_rst, DIR = O + PORT ddr_memory_cs_n = ddr_memory_cs_n, DIR = O PORT ddr_memory_clk_n = ddr_memory_clk_n, DIR = O + PORT ddr_memory_clk = ddr_memory_clk, DIR = O PORT ddr_memory_cke = ddr_memory_cke, DIR = O - PORT ddr_memory_cs_n = ddr_memory_cs_n, DIR = O - PORT ddr_memory_odt = ddr_memory_odt, DIR = O - PORT ddr_memory_ras_n = ddr_memory_ras_n, DIR = O PORT ddr_memory_cas_n = ddr_memory_cas_n, DIR = O - PORT ddr_memory_we_n = ddr_memory_we_n, DIR = O - PORT ddr_memory_dm = ddr_memory_dm, DIR = O, VEC = [7:0] PORT ddr_memory_ba = ddr_memory_ba, DIR = O, VEC = [2:0] PORT ddr_memory_addr = ddr_memory_addr, DIR = O, VEC = [12:0] - PORT ddr_memory_ddr3_rst = ddr_memory_ddr3_rst, DIR = O - PORT ddr_memory_dq = ddr_memory_dq, DIR = IO, VEC = [63:0] - PORT ddr_memory_dqs = ddr_memory_dqs, DIR = IO, VEC = [7:0] - PORT ddr_memory_dqs_n = ddr_memory_dqs_n, DIR = IO, VEC = [7:0] - PORT ETHERNET_MDIO = ETHERNET_MDIO, DIR = IO - PORT ETHERNET_MDC = ETHERNET_MDC, DIR = O + PORT SysACE_WEN = SysACE_WEN, DIR = O + PORT SysACE_OEN = SysACE_OEN, DIR = O + PORT SysACE_MPIRQ = SysACE_MPIRQ, DIR = I + PORT SysACE_MPD = SysACE_MPD, DIR = IO, VEC = [7:0] + PORT SysACE_MPA = SysACE_MPA, DIR = O, VEC = [6:0] + PORT SysACE_CLK = SysACE_CLK, DIR = I + PORT SysACE_CEN = SysACE_CEN, DIR = O + PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O + PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I + PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1 + PORT Push_Buttons_5Bits_TRI_I = Push_Buttons_5Bits_TRI_I, DIR = I, VEC = [0:4] + PORT Linear_Flash_we_n = Linear_Flash_we_n, DIR = O + PORT Linear_Flash_oe_n = Linear_Flash_oe_n, DIR = O + PORT Linear_Flash_data = Linear_Flash_data, DIR = IO, VEC = [0:15] + PORT Linear_Flash_ce_n = Linear_Flash_ce_n, DIR = O + PORT Linear_Flash_address = Linear_Flash_address, DIR = O, VEC = [0:23] + PORT LEDs_Positions_TRI_O = LEDs_Positions_TRI_O, DIR = O, VEC = [0:4] + PORT LEDs_8Bits_TRI_O = LEDs_8Bits_TRI_O, DIR = O, VEC = [0:7] + PORT IIC_SFP_SDA = IIC_SFP_SDA, DIR = IO + PORT IIC_SFP_SCL = IIC_SFP_SCL, DIR = IO + PORT IIC_FMC_SDA = IIC_FMC_SDA, DIR = IO + PORT IIC_FMC_SCL = IIC_FMC_SCL, DIR = IO + PORT IIC_EEPROM_SDA = IIC_EEPROM_SDA, DIR = IO + PORT IIC_EEPROM_SCL = IIC_EEPROM_SCL, DIR = IO + PORT IIC_DVI_SDA = IIC_DVI_SDA, DIR = IO + PORT IIC_DVI_SCL = IIC_DVI_SCL, DIR = IO + PORT DIP_Switches_8Bits_TRI_I = DIP_Switches_8Bits_TRI_I, DIR = I, VEC = [0:7] + PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000 + PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000 +# PORT ETHERNET_MDIO = ETHERNET_MDIO, DIR = IO +# PORT ETHERNET_MDC = ETHERNET_MDC, DIR = O PORT ETHERNET_TX_ER = ETHERNET_TX_ER, DIR = O PORT ETHERNET_TXD = ETHERNET_TXD, DIR = O, VEC = [7:0] PORT ETHERNET_TX_EN = ETHERNET_TX_EN, DIR = O @@ -49,19 +69,67 @@ PORT ETHERNET_PHY_RST_N = ETHERNET_PHY_RST_N, DIR = O -BEGIN axi_interconnect - PARAMETER INSTANCE = axi4_0 - PARAMETER HW_VER = 1.03.a - PORT interconnect_aclk = clk_100_0000MHzMMCM0 - PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn +BEGIN proc_sys_reset + PARAMETER INSTANCE = proc_sys_reset_0 + PARAMETER HW_VER = 3.00.a + PARAMETER C_EXT_RESET_HIGH = 1 + PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst + PORT Dcm_locked = proc_sys_reset_0_Dcm_locked + PORT MB_Reset = proc_sys_reset_0_MB_Reset + PORT Slowest_sync_clk = clk_100_0000MHzMMCM0 + PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn + PORT Ext_Reset_In = RESET + PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET END -BEGIN axi_interconnect - PARAMETER INSTANCE = axi4lite_0 - PARAMETER HW_VER = 1.03.a - PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 - PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn - PORT INTERCONNECT_ACLK = clk_50_0000MHzMMCM0 +BEGIN axi_intc + PARAMETER INSTANCE = microblaze_0_intc + PARAMETER HW_VER = 1.01.a + PARAMETER C_BASEADDR = 0x41200000 + PARAMETER C_HIGHADDR = 0x4120ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT IRQ = microblaze_0_interrupt + PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 + PORT INTR = RS232_Uart_1_Interrupt & IIC_EEPROM_IIC2INTC_Irpt & IIC_DVI_IIC2INTC_Irpt & IIC_FMC_IIC2INTC_Irpt & IIC_SFP_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & axi_timer_0_Interrupt & axi_ethernet_0_INTERRUPT & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = microblaze_0_ilmb + PARAMETER HW_VER = 2.00.b + PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET + PORT LMB_CLK = clk_100_0000MHzMMCM0 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = microblaze_0_i_bram_ctrl + PARAMETER HW_VER = 3.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE SLMB = microblaze_0_ilmb + BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = microblaze_0_dlmb + PARAMETER HW_VER = 2.00.b + PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET + PORT LMB_CLK = clk_100_0000MHzMMCM0 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = microblaze_0_d_bram_ctrl + PARAMETER HW_VER = 3.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE SLMB = microblaze_0_dlmb + BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN bram_block + PARAMETER INSTANCE = microblaze_0_bram_block + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block + BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block END BEGIN microblaze @@ -74,33 +142,29 @@ BEGIN microblaze PARAMETER C_ICACHE_BASEADDR = 0xc0000000 PARAMETER C_ICACHE_HIGHADDR = 0xcfffffff PARAMETER C_USE_ICACHE = 1 + PARAMETER C_CACHE_BYTE_SIZE = 16384 PARAMETER C_ICACHE_ALWAYS_USED = 1 PARAMETER C_DCACHE_BASEADDR = 0xc0000000 PARAMETER C_DCACHE_HIGHADDR = 0xcfffffff PARAMETER C_USE_DCACHE = 1 - PARAMETER C_DCACHE_ALWAYS_USED = 1 - PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 0 - PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 0 - PARAMETER C_CACHE_BYTE_SIZE = 16384 - PARAMETER C_ICACHE_LINE_LEN = 8 - PARAMETER C_ICACHE_STREAMS = 1 - PARAMETER C_ICACHE_VICTIMS = 8 PARAMETER C_DCACHE_BYTE_SIZE = 16384 - PARAMETER C_DCACHE_LINE_LEN = 4 - PARAMETER C_DCACHE_USE_WRITEBACK = 0 - PARAMETER C_USE_HW_MUL = 2 - PARAMETER C_USE_DIV = 1 - PARAMETER C_USE_BRANCH_TARGET_CACHE = 0 + PARAMETER C_DCACHE_ALWAYS_USED = 1 PARAMETER C_PVR = 2 PARAMETER C_USE_MMU = 3 PARAMETER C_MMU_ZONES = 2 + PARAMETER C_ICACHE_LINE_LEN = 8 + PARAMETER C_ICACHE_STREAMS = 1 + PARAMETER C_ICACHE_VICTIMS = 8 PARAMETER C_DIV_ZERO_EXCEPTION = 1 PARAMETER C_M_AXI_I_BUS_EXCEPTION = 1 PARAMETER C_M_AXI_D_BUS_EXCEPTION = 1 PARAMETER C_ILL_OPCODE_EXCEPTION = 1 PARAMETER C_OPCODE_0x0_ILLEGAL = 1 PARAMETER C_UNALIGNED_EXCEPTIONS = 1 + PARAMETER C_USE_HW_MUL = 2 + PARAMETER C_USE_DIV = 1 BUS_INTERFACE M_AXI_DP = axi4lite_0 + BUS_INTERFACE M_AXI_IP = axi4lite_0 BUS_INTERFACE M_AXI_DC = axi4_0 BUS_INTERFACE M_AXI_IC = axi4_0 BUS_INTERFACE DEBUG = microblaze_0_debug @@ -111,56 +175,17 @@ BEGIN microblaze PORT INTERRUPT = microblaze_0_interrupt END -BEGIN lmb_v10 - PARAMETER INSTANCE = microblaze_0_ilmb - PARAMETER HW_VER = 2.00.b - PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET - PORT LMB_CLK = clk_100_0000MHzMMCM0 -END - -BEGIN lmb_v10 - PARAMETER INSTANCE = microblaze_0_dlmb +BEGIN mdm + PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.b - PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET - PORT LMB_CLK = clk_100_0000MHzMMCM0 -END - -BEGIN lmb_bram_if_cntlr - PARAMETER INSTANCE = microblaze_0_i_bram_ctrl - PARAMETER HW_VER = 3.00.b - PARAMETER C_BASEADDR = 0x00000000 - PARAMETER C_HIGHADDR = 0x00001fff - BUS_INTERFACE SLMB = microblaze_0_ilmb - BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block -END - -BEGIN lmb_bram_if_cntlr - PARAMETER INSTANCE = microblaze_0_d_bram_ctrl - PARAMETER HW_VER = 3.00.b - PARAMETER C_BASEADDR = 0x00000000 - PARAMETER C_HIGHADDR = 0x00001fff - BUS_INTERFACE SLMB = microblaze_0_dlmb - BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block -END - -BEGIN bram_block - PARAMETER INSTANCE = microblaze_0_bram_block - PARAMETER HW_VER = 1.00.a - BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block - BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block -END - -BEGIN proc_sys_reset - PARAMETER INSTANCE = proc_sys_reset_0 - PARAMETER HW_VER = 3.00.a - PARAMETER C_EXT_RESET_HIGH = 1 - PORT Ext_Reset_In = RESET - PORT MB_Reset = proc_sys_reset_0_MB_Reset - PORT Slowest_sync_clk = clk_50_0000MHzMMCM0 - PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn - PORT Dcm_locked = proc_sys_reset_0_Dcm_locked - PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst - PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET + PARAMETER C_INTERCONNECT = 2 + PARAMETER C_USE_UART = 1 + PARAMETER C_BASEADDR = 0x74800000 + PARAMETER C_HIGHADDR = 0x7480ffff + BUS_INTERFACE S_AXI = axi4lite_0 + BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug + PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst + PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 END BEGIN clock_generator @@ -196,17 +221,49 @@ BEGIN clock_generator PORT PSDONE = psdone END -BEGIN mdm - PARAMETER INSTANCE = debug_module - PARAMETER HW_VER = 2.00.b - PARAMETER C_INTERCONNECT = 2 - PARAMETER C_USE_UART = 1 - PARAMETER C_BASEADDR = 0x74800000 - PARAMETER C_HIGHADDR = 0x7480ffff +BEGIN axi_timer + PARAMETER INSTANCE = axi_timer_0 + PARAMETER HW_VER = 1.02.a + PARAMETER C_COUNT_WIDTH = 32 + PARAMETER C_ONE_TIMER_ONLY = 0 + PARAMETER C_BASEADDR = 0x41c00000 + PARAMETER C_HIGHADDR = 0x41c0ffff BUS_INTERFACE S_AXI = axi4lite_0 - BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug - PORT S_AXI_ACLK = clk_50_0000MHzMMCM0 - PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst + PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 + PORT Interrupt = axi_timer_0_Interrupt +END + +BEGIN axi_interconnect + PARAMETER INSTANCE = axi4lite_0 + PARAMETER HW_VER = 1.03.a + PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 + PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn + PORT INTERCONNECT_ACLK = clk_100_0000MHzMMCM0 +END + +BEGIN axi_interconnect + PARAMETER INSTANCE = axi4_0 + PARAMETER HW_VER = 1.03.a + PORT interconnect_aclk = clk_100_0000MHzMMCM0 + PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn +END + +BEGIN axi_sysace + PARAMETER INSTANCE = SysACE_CompactFlash + PARAMETER HW_VER = 1.01.a + PARAMETER C_MEM_WIDTH = 8 + PARAMETER C_BASEADDR = 0x41800000 + PARAMETER C_HIGHADDR = 0x4180ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 + PORT SysACE_WEN = SysACE_WEN + PORT SysACE_OEN = SysACE_OEN + PORT SysACE_MPIRQ = SysACE_MPIRQ + PORT SysACE_MPD = SysACE_MPD + PORT SysACE_MPA = SysACE_MPA + PORT SysACE_CLK = SysACE_CLK + PORT SysACE_CEN = SysACE_CEN + PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ END BEGIN axi_uartlite @@ -219,113 +276,144 @@ BEGIN axi_uartlite PARAMETER C_BASEADDR = 0x40600000 PARAMETER C_HIGHADDR = 0x4060ffff BUS_INTERFACE S_AXI = axi4lite_0 + PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 PORT TX = RS232_Uart_1_sout PORT RX = RS232_Uart_1_sin - PORT S_AXI_ACLK = clk_50_0000MHzMMCM0 PORT Interrupt = RS232_Uart_1_Interrupt END -BEGIN axi_gpio - PARAMETER INSTANCE = DIP_Switches_8Bits +BEGIN util_vector_logic + PARAMETER INSTANCE = Linear_Flash_invertor + PARAMETER HW_VER = 1.00.a + PARAMETER C_OPERATION = not + PARAMETER C_SIZE = 1 + PORT Op1 = Linear_Flash_invertor_Op1_Adhoc + PORT Res = Linear_Flash_ce_n +END + +BEGIN axi_emc + PARAMETER INSTANCE = Linear_Flash + PARAMETER HW_VER = 1.01.a + PARAMETER C_NUM_BANKS_MEM = 1 + PARAMETER C_MEM0_WIDTH = 16 + PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 + PARAMETER C_MEM0_TYPE = 2 + PARAMETER C_TCEDV_PS_MEM_0 = 130000 + PARAMETER C_TAVDV_PS_MEM_0 = 130000 + PARAMETER C_THZCE_PS_MEM_0 = 35000 + PARAMETER C_TWC_PS_MEM_0 = 13000 + PARAMETER C_TWP_PS_MEM_0 = 70000 + PARAMETER C_TLZWE_PS_MEM_0 = 35000 + PARAMETER C_MAX_MEM_WIDTH = 16 + PARAMETER C_S_AXI_MEM0_BASEADDR = 0x76000000 + PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x77ffffff + BUS_INTERFACE S_AXI_MEM = axi4lite_0 + PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 + PORT RdClk = clk_100_0000MHzMMCM0 + PORT Mem_WEN = Linear_Flash_we_n + PORT Mem_OEN = Linear_Flash_oe_n + PORT Mem_CEN = Linear_Flash_invertor_Op1_Adhoc + PORT Mem_DQ = Linear_Flash_data + PORT Mem_A = 0b0000000 & Linear_Flash_address & 0b0 +END + +BEGIN axi_iic + PARAMETER INSTANCE = IIC_SFP PARAMETER HW_VER = 1.01.a - PARAMETER C_GPIO_WIDTH = 8 - PARAMETER C_ALL_INPUTS = 1 - PARAMETER C_INTERRUPT_PRESENT = 0 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_BASEADDR = 0x40060000 - PARAMETER C_HIGHADDR = 0x4006ffff + PARAMETER C_IIC_FREQ = 100000 + PARAMETER C_TEN_BIT_ADR = 0 + PARAMETER C_BASEADDR = 0x40800000 + PARAMETER C_HIGHADDR = 0x4080ffff BUS_INTERFACE S_AXI = axi4lite_0 - PORT GPIO_IO_I = DIP_Switches_8Bits_TRI_I - PORT S_AXI_ACLK = clk_50_0000MHzMMCM0 + PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 + PORT Sda = IIC_SFP_SDA + PORT Scl = IIC_SFP_SCL + PORT IIC2INTC_Irpt = IIC_SFP_IIC2INTC_Irpt END -BEGIN axi_gpio - PARAMETER INSTANCE = LEDs_8Bits +BEGIN axi_iic + PARAMETER INSTANCE = IIC_FMC PARAMETER HW_VER = 1.01.a - PARAMETER C_GPIO_WIDTH = 8 - PARAMETER C_ALL_INPUTS = 0 - PARAMETER C_INTERRUPT_PRESENT = 0 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_BASEADDR = 0x40040000 - PARAMETER C_HIGHADDR = 0x4004ffff + PARAMETER C_IIC_FREQ = 100000 + PARAMETER C_TEN_BIT_ADR = 0 + PARAMETER C_BASEADDR = 0x40820000 + PARAMETER C_HIGHADDR = 0x4082ffff BUS_INTERFACE S_AXI = axi4lite_0 - PORT GPIO_IO_O = LEDs_8Bits_TRI_O - PORT S_AXI_ACLK = clk_50_0000MHzMMCM0 + PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 + PORT Sda = IIC_FMC_SDA + PORT Scl = IIC_FMC_SCL + PORT IIC2INTC_Irpt = IIC_FMC_IIC2INTC_Irpt END -BEGIN axi_gpio - PARAMETER INSTANCE = LEDs_Positions +BEGIN axi_iic + PARAMETER INSTANCE = IIC_EEPROM PARAMETER HW_VER = 1.01.a - PARAMETER C_GPIO_WIDTH = 5 - PARAMETER C_ALL_INPUTS = 0 - PARAMETER C_INTERRUPT_PRESENT = 0 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_BASEADDR = 0x40020000 - PARAMETER C_HIGHADDR = 0x4002ffff + PARAMETER C_IIC_FREQ = 100000 + PARAMETER C_TEN_BIT_ADR = 0 + PARAMETER C_BASEADDR = 0x40840000 + PARAMETER C_HIGHADDR = 0x4084ffff BUS_INTERFACE S_AXI = axi4lite_0 - PORT GPIO_IO_O = LEDs_Positions_TRI_O - PORT S_AXI_ACLK = clk_50_0000MHzMMCM0 + PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 + PORT Sda = IIC_EEPROM_SDA + PORT Scl = IIC_EEPROM_SCL + PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt END -BEGIN axi_gpio - PARAMETER INSTANCE = Push_Buttons_5Bits +BEGIN axi_iic + PARAMETER INSTANCE = IIC_DVI PARAMETER HW_VER = 1.01.a - PARAMETER C_GPIO_WIDTH = 5 - PARAMETER C_ALL_INPUTS = 1 - PARAMETER C_INTERRUPT_PRESENT = 0 - PARAMETER C_IS_DUAL = 0 - PARAMETER C_BASEADDR = 0x40000000 - PARAMETER C_HIGHADDR = 0x4000ffff + PARAMETER C_IIC_FREQ = 100000 + PARAMETER C_TEN_BIT_ADR = 0 + PARAMETER C_BASEADDR = 0x40860000 + PARAMETER C_HIGHADDR = 0x4086ffff BUS_INTERFACE S_AXI = axi4lite_0 - PORT GPIO_IO_I = Push_Buttons_5Bits_TRI_I - PORT S_AXI_ACLK = clk_50_0000MHzMMCM0 + PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 + PORT Sda = IIC_DVI_SDA + PORT Scl = IIC_DVI_SCL + PORT IIC2INTC_Irpt = IIC_DVI_IIC2INTC_Irpt END BEGIN axi_v6_ddrx PARAMETER INSTANCE = DDR3_SDRAM PARAMETER HW_VER = 1.03.a - PARAMETER C_MEM_PARTNO = MT4JSF6464HY-1G1 - PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 - PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 - PARAMETER C_DM_WIDTH = 8 - PARAMETER C_DQS_WIDTH = 8 - PARAMETER C_DQ_WIDTH = 64 + PARAMETER C_MEM_PARTNO = MT41J64M16XX-15E + PARAMETER C_DM_WIDTH = 1 + PARAMETER C_DQS_WIDTH = 1 + PARAMETER C_DQ_WIDTH = 8 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y8 + PARAMETER C_NDQS_COL0 = 1 + PARAMETER C_NDQS_COL1 = 0 PARAMETER C_S_AXI_BASEADDR = 0xc0000000 PARAMETER C_S_AXI_HIGHADDR = 0xcfffffff BUS_INTERFACE S_AXI = axi4_0 - PORT ddr_ck_p = ddr_memory_clk + PORT ddr_we_n = ddr_memory_we_n + PORT ddr_ras_n = ddr_memory_ras_n + PORT ddr_odt = ddr_memory_odt + PORT ddr_dqs_n = ddr_memory_dqs_n + PORT ddr_dqs_p = ddr_memory_dqs + PORT ddr_dq = ddr_memory_dq + PORT ddr_dm = ddr_memory_dm + PORT ddr_reset_n = ddr_memory_ddr3_rst + PORT ddr_cs_n = ddr_memory_cs_n PORT ddr_ck_n = ddr_memory_clk_n + PORT ddr_ck_p = ddr_memory_clk PORT ddr_cke = ddr_memory_cke - PORT ddr_cs_n = ddr_memory_cs_n - PORT ddr_odt = ddr_memory_odt - PORT ddr_ras_n = ddr_memory_ras_n PORT ddr_cas_n = ddr_memory_cas_n - PORT ddr_we_n = ddr_memory_we_n - PORT ddr_dm = ddr_memory_dm PORT ddr_ba = ddr_memory_ba PORT ddr_addr = ddr_memory_addr - PORT ddr_reset_n = ddr_memory_ddr3_rst - PORT ddr_dq = ddr_memory_dq - PORT ddr_dqs_p = ddr_memory_dqs - PORT ddr_dqs_n = ddr_memory_dqs_n + PORT clk_rd_base = clk_400_0000MHzMMCM0_nobuf_varphase + PORT clk_mem = clk_400_0000MHzMMCM0 PORT clk = clk_200_0000MHzMMCM0 PORT clk_ref = clk_200_0000MHzMMCM0 - PORT clk_mem = clk_400_0000MHzMMCM0 - PORT clk_rd_base = clk_400_0000MHzMMCM0_nobuf_varphase PORT PD_PSEN = psen PORT PD_PSINCDEC = psincdec PORT PD_PSDONE = psdone END BEGIN axi_ethernet - PARAMETER INSTANCE = ETHERNET - PARAMETER HW_VER = 2.01.a - PARAMETER C_PHYADDR = 0B00001 + PARAMETER INSTANCE = axi_ethernet_0 + PARAMETER HW_VER = 3.00.a PARAMETER C_INCLUDE_IO = 1 PARAMETER C_TYPE = 2 PARAMETER C_PHY_TYPE = 1 @@ -343,16 +431,15 @@ BEGIN axi_ethernet PARAMETER C_MCAST_EXTEND = 0 PARAMETER C_STATS = 0 PARAMETER C_AVB = 0 - PARAMETER C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC = 0 - PARAMETER C_BASEADDR = 0x41240000 - PARAMETER C_HIGHADDR = 0x4127ffff + PARAMETER C_BASEADDR = 0x75440000 + PARAMETER C_HIGHADDR = 0x7547ffff BUS_INTERFACE S_AXI = axi4lite_0 BUS_INTERFACE AXI_STR_TXD = ETHERNET_dma_txd BUS_INTERFACE AXI_STR_TXC = ETHERNET_dma_txc BUS_INTERFACE AXI_STR_RXS = ETHERNET_dma_rxs BUS_INTERFACE AXI_STR_RXD = ETHERNET_dma_rxd - PORT MDIO = ETHERNET_MDIO - PORT MDC = ETHERNET_MDC +# PORT MDIO = ETHERNET_MDIO +# PORT MDC = ETHERNET_MDC PORT GMII_TX_ER = ETHERNET_TX_ER PORT GMII_TXD = ETHERNET_TXD PORT GMII_TX_EN = ETHERNET_TX_EN @@ -374,19 +461,7 @@ BEGIN axi_ethernet PORT AXI_STR_TXC_ARESETN = AXI_STR_TXC_ARESETN PORT AXI_STR_RXD_ARESETN = AXI_STR_RXD_ARESETN PORT AXI_STR_RXS_ARESETN = AXI_STR_RXS_ARESETN - PORT INTERRUPT = ETHERNET_INTERRUPT -END - -BEGIN axi_timer - PARAMETER INSTANCE = axi_timer_0 - PARAMETER HW_VER = 1.02.a - PARAMETER C_COUNT_WIDTH = 32 - PARAMETER C_ONE_TIMER_ONLY = 0 - PARAMETER C_BASEADDR = 0x41c00000 - PARAMETER C_HIGHADDR = 0x41c0ffff - BUS_INTERFACE S_AXI = axi4lite_0 - PORT S_AXI_ACLK = clk_50_0000MHzMMCM0 - PORT Interrupt = axi_timer_0_Interrupt + PORT INTERRUPT = axi_ethernet_0_INTERRUPT END BEGIN axi_dma @@ -402,8 +477,8 @@ BEGIN axi_dma PARAMETER C_SG_LENGTH_WIDTH = 16 PARAMETER C_INCLUDE_MM2S = 1 PARAMETER C_INCLUDE_S2MM = 1 - PARAMETER C_BASEADDR = 0x41e00000 - PARAMETER C_HIGHADDR = 0x41e0ffff + PARAMETER C_BASEADDR = 0x41F00000 + PARAMETER C_HIGHADDR = 0x41F0FFFF PARAMETER C_MM2S_BURST_SIZE = 256 PARAMETER C_S2MM_BURST_SIZE = 256 BUS_INTERFACE S_AXI_LITE = axi4lite_0 @@ -426,14 +501,3 @@ BEGIN axi_dma PORT s2mm_introut = ETHERNET_dma_s2mm_introut END -BEGIN axi_intc - PARAMETER INSTANCE = microblaze_0_intc - PARAMETER HW_VER = 1.01.a - PARAMETER C_BASEADDR = 0x41200000 - PARAMETER C_HIGHADDR = 0x4120ffff - BUS_INTERFACE S_AXI = axi4lite_0 - PORT IRQ = microblaze_0_interrupt - PORT S_AXI_ACLK = clk_50_0000MHzMMCM0 - PORT INTR = RS232_Uart_1_Interrupt & ETHERNET_INTERRUPT & axi_timer_0_Interrupt & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut -END - diff --git a/microblaze/ethernetgmii/system.xmp b/microblaze/ethernetgmii/system.xmp index 98f52a1..f7536c1 100644 --- a/microblaze/ethernetgmii/system.xmp +++ b/microblaze/ethernetgmii/system.xmp @@ -24,7 +24,9 @@ UcfFile: data/system.ucf EnableParTimingError: 1 ShowLicenseDialog: 0 ICacheAddr: DDR3_SDRAM,C_S_AXI_BASEADDR +ICacheAddr: DDR3_SDRAM,C_S_AXI_CTRL_BASEADDR DCacheAddr: DDR3_SDRAM,C_S_AXI_BASEADDR +DCacheAddr: DDR3_SDRAM,C_S_AXI_CTRL_BASEADDR Processor: microblaze_0 ElfImp: ElfSim: -- 2.11.4.GIT