From 27f28e331ac8e30dd38e0b44b287aec5304d2551 Mon Sep 17 00:00:00 2001 From: jmcmullan Date: Mon, 7 Jan 2013 04:24:12 +0000 Subject: [PATCH] Revert "pciusb.device: Rearrange some OHCI data structures, to prevent cache invalidation clobbers" This reverts commit r46207 - no longer needed, now that Sam4xx used Write-Through caching. git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@46226 fb15a70f-31f2-0310-bbcc-cdcc74a49acc --- rom/usb/pciusb/ohcichip.h | 40 ++++++++++++---------------------------- 1 file changed, 12 insertions(+), 28 deletions(-) diff --git a/rom/usb/pciusb/ohcichip.h b/rom/usb/pciusb/ohcichip.h index 8e673e412c..25ca290ffe 100644 --- a/rom/usb/pciusb/ohcichip.h +++ b/rom/usb/pciusb/ohcichip.h @@ -217,18 +217,6 @@ struct OhciHCCA struct OhciED { - /* HC data, aligned to 16 bytes */ - ULONG oed_EPCaps; /* LE MaxPacketSize and other stuff */ - ULONG oed_TailPtr; /* LE PHYSICAL TD Queue Tail Pointer */ - ULONG oed_HeadPtr; /* LE PHYSICAL TD Queue Head Pointer */ - ULONG oed_NextED; /* LE PHYSICAL Next Endpoint Descriptor */ -#ifdef __powerpc__ - /* Required due to the 32-byte cache line alignment requirements - * Otherwise, cache invalidation can clobber oed_Succ etc.. - */ - ULONG oed_Align[4]; -#endif - struct OhciED *oed_Succ; struct OhciED *oed_Pred; ULONG oed_Self; /* LE PHYSICAL pointer to self */ @@ -239,31 +227,27 @@ struct OhciED IPTR oed_Continue; /* Flag for fragmented bulk transfer */ APTR oed_Buffer; /* Mirror buffer for data outside of DMA-accessible area */ struct UsbSetupData *oed_SetupData; /* Mirror buffer for setup packet */ + + /* HC data, aligned to 16 bytes */ + ULONG oed_EPCaps; /* LE MaxPacketSize and other stuff */ + ULONG oed_TailPtr; /* LE PHYSICAL TD Queue Tail Pointer */ + ULONG oed_HeadPtr; /* LE PHYSICAL TD Queue Head Pointer */ + ULONG oed_NextED; /* LE PHYSICAL Next Endpoint Descriptor */ }; struct OhciTD { - /* HC data, aligned to 16 bytes */ - ULONG otd_Ctrl; /* LE Ctrl stuff */ - ULONG otd_BufferPtr; /* LE PHYSICAL Current Buffer Pointer */ - ULONG otd_NextTD; /* LE PHYSICAL Next TD */ - ULONG otd_BufferEnd; /* LE PHYSICAL End of buffer */ -#ifdef __powerpc__ - /* Required due to the 32-byte cache line alignment requirements - * Otherwise, cache invalidation can clobber otd_Succ etc.. - */ - ULONG oed_Align[4]; -#endif - struct OhciTD *otd_Succ; IPTR otd_Length; /* Length of transfer */ ULONG otd_Self; /* LE PHYSICAL pointer to self */ /* On 64 bits a padding will be inserted here */ struct OhciED *otd_ED; /* Pointer to parent ED this TD belongs to */ -#ifdef __powerpc__ - /* Pad the structure to a multiple of 32 bytes */ - ULONG oed_Align2[4]; -#endif + + /* HC data, aligned to 16 bytes */ + ULONG otd_Ctrl; /* LE Ctrl stuff */ + ULONG otd_BufferPtr; /* LE PHYSICAL Current Buffer Pointer */ + ULONG otd_NextTD; /* LE PHYSICAL Next TD */ + ULONG otd_BufferEnd; /* LE PHYSICAL End of buffer */ }; /* pointer defines */ -- 2.11.4.GIT