From 1573d03903500847c9fe01649a111eb65548c182 Mon Sep 17 00:00:00 2001 From: schulz Date: Sun, 26 Feb 2017 20:42:28 +0000 Subject: [PATCH] Since a potentialy unsafe condition may occur (IRQ before IDT tables are set on secondary cores, or IRQ before it was actually enabled in IDT on primary core), give all cores a full one second before forced reschedule (timer based, 1kHz) occurs for the first time. git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@53923 fb15a70f-31f2-0310-bbcc-cdcc74a49acc --- arch/all-pc/kernel/apic_ia32.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/all-pc/kernel/apic_ia32.c b/arch/all-pc/kernel/apic_ia32.c index 053b57499c..7606f18146 100644 --- a/arch/all-pc/kernel/apic_ia32.c +++ b/arch/all-pc/kernel/apic_ia32.c @@ -424,7 +424,7 @@ void core_APIC_Init(struct APICData *apic, apicid_t cpuNum) ADDHEAD(&KERNELIRQ_LIST(hbHandle->in_nr), &hbHandle->in_Node); Enable(); - apic->flags |= APF_TIMER; + apic->flags |= APF_TIMER; } else { @@ -464,7 +464,7 @@ void core_APIC_Init(struct APICData *apic, apicid_t cpuNum) // TODO: Adjust based on the amount of work the APIC can do at its given frequency. schedData->Granularity = 1; schedData->Quantum = 5; - APIC_REG(__APICBase, APIC_TIMER_ICR) = (apic->cores[cpuNum].cpu_TimerFreq + 500) / 1000; + APIC_REG(__APICBase, APIC_TIMER_ICR) = (apic->cores[cpuNum].cpu_TimerFreq); #else APIC_REG(__APICBase, APIC_TIMER_ICR) = (apic->cores[cpuNum].cpu_TimerFreq + 25) / 50; #endif -- 2.11.4.GIT