| commit | a971dce2dd3eaa2fbec0067a068648fad5f0e258 | |
| author | DizzyOfCRN <DizzyOfCRN@fb15a70f-31f2-0310-bbcc-cdcc74a49acc> | |
| Wed, 12 Nov 2014 09:56:49 +0000 (12 09:56 +0000) | ||
| committer | DizzyOfCRN <DizzyOfCRN@fb15a70f-31f2-0310-bbcc-cdcc74a49acc> | |
| Wed, 12 Nov 2014 09:56:49 +0000 (12 09:56 +0000) | ||
| tree | 5719145fe6bc8882555897f3f6dd6358604944cd | treesnapshot (tar.gz zip) |
| parent | 4fb29592cd6475ff1d7fe662a1a8ff5ea9d130f9 | commitdiff |
Reintroduce platform.h in order to brake 600MHz DRAM clock (DDR3-1200), we already are beyond the advertised 400MHz but would be nice to go a bit further.
We may need to pumpup the core voltage from default 1.2V(?) before, do it while on 24MHz clock and then raise the CPU clock straight to >1GHz before DRAM init.
Platform specific parameters are in separate file loaded by the bootstrap or in the sunxi boot header, uncertain at this point.
git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@49789 fb15a70f-31f2-0310-bbcc-cdcc74a49acc
We may need to pumpup the core voltage from default 1.2V(?) before, do it while on 24MHz clock and then raise the CPU clock straight to >1GHz before DRAM init.
Platform specific parameters are in separate file loaded by the bootstrap or in the sunxi boot header, uncertain at this point.
git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@49789 fb15a70f-31f2-0310-bbcc-cdcc74a49acc
| arch/arm-sun4i/bootstrap/bootstrap.c | diffblobblamehistory | |
| arch/arm-sun4i/bootstrap/platform.h | [new file with mode: 0644] | blob |