Generation code optmization.
commitadf4681032dc334c3d35e98680de5bd70066f384
authorRodrigo Peixoto <rodrigopex@urano.(none)>
Thu, 17 Apr 2008 23:25:38 +0000 (17 20:25 -0300)
committerRodrigo Peixoto <rodrigopex@urano.(none)>
Thu, 17 Apr 2008 23:25:38 +0000 (17 20:25 -0300)
treefd67660e2d78f65f974b7f34705205ed20d59139
parent942461404f3908634ff4072538d045bb41bfbd49
Generation code optmization.
27 files changed:
src/.utils.py.swp [moved from src/.vut_parser.py.swp with 50% similarity]
src/example5.vut
src/gen/a.mem [deleted file]
src/gen/b.mem [deleted file]
src/gen/fulladder.v [deleted file]
src/gen/makefile [new file with mode: 0644]
src/gen/overflow.mem [deleted file]
src/gen/result.mem [deleted file]
src/gen/verilog.log
src/gen/vut_fulladder.v [deleted file]
src/gen/waveform.vcd [deleted file]
src/overflow.py [new file with mode: 0644]
src/overflow.pyc [new file with mode: 0644]
src/tags [new file with mode: 0644]
src/utils.py
src/utils.pyc
src/verilog.log [new file with mode: 0644]
src/vut_checker.py
src/vut_checker.pyc
src/vut_front_end.py [changed mode: 0644->0755]
src/vut_front_end.pyc [new file with mode: 0644]
src/vut_generator.py
src/vut_generator.pyc
src/vut_parser.py
src/vut_parser.pyc
src/vutg [new file with mode: 0755]
src/waveform.vcd [new file with mode: 0644]