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commit	1d7acf8ff5fbcc55089351c8e12e6ebb8f17d47f
author	Rodrigo Peixoto <rodrigopex@urano.(none)>
	Sun, 13 Apr 2008 22:01:08 +0000 (13 19:01 -0300)
committer	Rodrigo Peixoto <rodrigopex@urano.(none)>
	Sun, 13 Apr 2008 22:01:08 +0000 (13 19:01 -0300)
tree	016645849e816194e139b3277d4cda586ec1c9e6	tree \| snapshot (tar.gz zip)
parent	aea2a553910383ea7147ee5ec1f829cf08a9e672	commit \| diff

Project cleaned.

31 files changed:

.project	[deleted file]	blob \| blame \| history
.pydevproject	[deleted file]	blob \| blame \| history
.settings/org.eclipse.core.resources.prefs	[deleted file]	blob \| blame \| history
gedit_plugin/verilog_unit_test.gedit-plugin	[deleted file]	blob \| blame \| history
gedit_plugin/verilog_unit_test.py	[deleted file]	blob \| blame \| history
src/grammar.vut	[moved from src/grammar.xml with 100% similarity]	blob \| blame \| history
src/teste2.xml	[deleted file]	blob \| blame \| history
src/teste_simple.xml	[deleted file]	blob \| blame \| history
src/utils.pyc	[deleted file]	blob \| blame \| history
src/val.py	[deleted file]	blob \| blame \| history
src/verilog.log	[deleted file]	blob \| blame \| history
src/vut.dtd	[deleted file]	blob \| blame \| history
src/vut_checker.pyc	[deleted file]	blob \| blame \| history
src/vut_generator.pyc	[deleted file]	blob \| blame \| history
src/vut_parser.pyc	[deleted file]	blob \| blame \| history
verilog_src/fulladder_2b.v	[deleted file]	blob \| blame \| history
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verilog_src/in_a.mem	[deleted file]	blob \| blame \| history
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verilog_src/out_overflow.mem	[deleted file]	blob \| blame \| history
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verilog_src/out_result.mem	[deleted file]	blob \| blame \| history
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verilog_src/test	[deleted file]	blob \| blame \| history
verilog_src/teste_mem.v	[deleted file]	blob \| blame \| history
verilog_src/teste_mem.v~	[deleted file]	blob \| blame \| history
verilog_src/verilog.log	[deleted file]	blob \| blame \| history
verilog_src/veriwell.key	[deleted file]	blob \| blame \| history
verilog_src/veriwell.log	[deleted file]	blob \| blame \| history
verilog_src/waveform.vcd	[deleted file]	blob \| blame \| history

Verilog Unit Test generator

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