arm: tegra30: pcie: do not disable clk after deasserting resetsl4t/l4t-r16-r2daily-2014.11.07.0_l4t/l4t-r16tegra-l4t-r16-16.5
| commit | c7460e0d6afd754ebf5555477129579bc83c47b9 | |
| author | Shreshtha SAHU <ssahu@nvidia.com> | |
| Wed, 3 Sep 2014 12:15:17 +0000 (3 17:45 +0530) | ||
| committer | Winnie Hsu <whsu@nvidia.com> | |
| Tue, 14 Oct 2014 01:50:01 +0000 (13 18:50 -0700) | ||
| tree | 4a1c5741ee017013f697813c85a5d975f0401f96 | treesnapshot (tar.gz zip) |
| parent | 36a8e8ba4538d17acaac60ffca6835cf21f33709 | commitdiff |
arm: tegra30: pcie: do not disable clk after deasserting resets
Do not disable and re-enable clocks after deasserting
PCIE, AFI and PCIEX resets. Deasserting the resets should
be followed by programming the PCIE.
Bug 1521306
Change-Id: Idc43bc9b21cac3818852ed059fe512f4cd75b748
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/495616
GVS: Gerrit_Virtual_Submit
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Do not disable and re-enable clocks after deasserting
PCIE, AFI and PCIEX resets. Deasserting the resets should
be followed by programming the PCIE.
Bug 1521306
Change-Id: Idc43bc9b21cac3818852ed059fe512f4cd75b748
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/495616
GVS: Gerrit_Virtual_Submit
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
| arch/arm/mach-tegra/powergate.c | diffblobblamehistory |